Thesis Organization

In Chapter 2, several A/D converters are reviewed. The architecture of the proposed pipelined ADC is also presented. In Chapter 3, the design and analysis of the circuits in each building block will be described. In Chapter 4, the layout consideration and floor plan will be presented. In Chapter 5, the measurement results of the fabricated pipelined A/D converter will be presented. In Chapter 6, the conclusion and perspectives are presented.

Chapter 2

Fundamentals

2.1 Overview [1]

Analog-to-Digital converters find wide applications in many fields. There are several architectures for different applications. The requirements of ADC versus different fields of application are shown in Fig. 2.1. The properties of different architectures are shown in Fig.

2.2.

In Fig. 2.2, there are many kinds of Nyquest A/D converter architectures. Some converters are suitable for high resolution and some are used for high-speed application. Here, we briefly discuss operation and characteristics of these architectures as follows.

Fig. 2.1 The requirements of ADC versus the fields of application

Fig. 2.2 The properties of different architectures

2.1.1 Delta-Sigma Architecture

Delta-Sigma ADC is based on the principle of highly over-sampling the input signal followed by a digital filter/decimator to obtain the digital code equivalent. Delta-Sigma ADC is ideal for low-bandwidth signals and is capable of very high resolution, 16- to 24-bits. This converter technology allows for a trade-off between signal bandwidth and resolution that is often externally programmable. A digital filter can have greater complexity than its analog equivalent at lower cost, and is always exactly reproducible over temperature and time.

Complex filter functions (i.e. 50-/60-Hz notch filter) are readily achieved and are often tailored to a specific application. Applications for Delta-Sigma ADCs include industrial process control, analytical and test instrumentation, medical imaging and acquisition, communications, and professional and consumer audio. DSP compatibility makes them ideal choices for system solutions.

Fig. 2.3 Delta-Sigma architecture

2.1.2 SAR Architecture

SAR-type converters are frequently the architecture of choice for medium-to–high- resolution applications with medium sampling rates. SAR ADCs most commonly range in

resolution from 10- to 16-bits. They provide low power consumption and a small form factor.

A SAR has little sample-to-conversion latency compared to a pipeline or delta-sigma converter. This combination makes them ideal for real-time applications such as industrial control, motor control, power management, portable/ battery-powered instruments, PDA, test equipment and data/signal acquisition. In a successive approximation register (SAR) ADC, the bits are decided by a single high-speed, high-accuracy comparator bit by bit, from the MSB down to the LSB. This is done by comparing the analog input with a DAC whose output is updated by previously decided bits and successively approximates the analog input.

Fig. 2.4 SAR Architecture

2.1.3 Flash Architecture

Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. They are suitable for applications requiring very large bandwidths. However, flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. This limits them to high frequency applications that typically cannot be addressed any other way. Examples include data acquisition,, satellite

communication, radar processing, sampling oscilloscopes, and high-density disk drives.

2.1.4 Pipeline Architecture

This converter type offers high speed, high resolution and excellent performance, along with modest levels of power dissipation and small die size. Within reasonable design limits, they also offer excellent dynamic performance. Pipeline latency is typically six or more clock cycles. Target applications for pipeline ADCs include CCD-based imaging systems, ultrasonic medical imaging, digital receiver, base station, digital video, xDSL, cable modem and fast Ethernet. Additionally, communication systems in which total harmonic distortion (THD), spurious-free dynamic range (SFDR) and other frequency-domain specifications are significant. Pipeline ADCs consist of numerous consecutive stages, each containing a sample and hold (S/H), a low-resolution ADC and DAC, and a summing circuit that includes an inter-stage amplifier to provide gain.

Fig. 2.5 Pipeline Architecture

2.1.5 A Simple ADC Comparison Matrix [2]

DELTA SIGMA SAR PIPELINE FLASH (Parallel)

Pick This Architecture if

you want:

High resolution, low to medium speed, no resolution (8 to 16bit), 5Msps and under, low power, small size. 5-Hz - 60Hz rejection programmable data increase by a factor of 2 for each bit. expense of power and

latency. output rate and noise

free resolution with every bit increase

in resolution.

Component matching requirements double with every bit increase

in resolution.

Component matching requirements double with every bit increase

in resolution.

Component matching typically limits resolution to 8

bits.

Size

Core die size will not materially change with Die size and power

increases exponentially with

resolution.

Table 2.1 ADC Comparison Matrix

2.2 Pipeline ADC versus Other ADCs

2.2.1 Versus the Delta-Sigma

Traditionally, over-sampling/delta-sigma-type converters commonly used in digital audio have a limited bandwidth of about 22 KHz or so. But recently some high-bandwidth delta-sigma -type converters have reached a bandwidth of 1MHz to 2MHz with 12 to 16 bits of resolution. These are usually very-high-order delta-sigma modulators (for example, fourth or even higher) incorporating a multi-bit ADC and multi-bit feedback DAC, and their main applications are in ADSL. Delta-sigma converters have the innate nature of requiring no special trimming/calibration, even for 16 to 18 bits of resolution. They also require no steep rolling-off anti-alias filter at the analog inputs, because the sampling rate is much higher than the effective bandwidth; the backend digital filters take care of it. The over-sampling nature of the delta-sigma converter also tends to "average out" any system noise at the analog inputs.

However, sigma-delta converters trade speed for resolution. The need to sample many times (for example, at least 16 times, but often much higher) to produce one final sample causes the internal analog components in the delta-sigma modulator to operate much faster than the final data rate. The digital decimation filter is also nontrivial to design and takes up a lot of silicon area. The fastest, high-resolution delta-sigma-type converters are not expected to have more than a few MHz of bandwidth in the near future. Like pipelined ADCs, delta-sigma converters also have latency.

2.2.2 Versus SAR

In a successive approximation register (SAR) ADC, the bits are decided by a single high-speed, high-accuracy comparator bit by bit, from the MSB down to the LSB, by comparing the analog input with a DAC whose output is updated by previously decided bits and successively approximates the analog input. This serial nature of SAR limits its operating speed to no more than a few MS/s, and still slower for very high resolutions (14 to 16bits). A

pipelined ADC, however, employs a parallel structure in which each stage works on 1 to a few bits (of successive samples) concurrently. Although there is only one comparator in a SAR, this comparator has to be fast (clocked at approximately the number of bits x the sample rate) and as accurate as the ADC itself. In contrast, none of the comparators inside a pipelined ADC needs this kind of speed or accuracy.

However, a pipelined ADC generally takes up significantly more silicon area than an equivalent SAR. A SAR also displays a latency of only one cycle, versus about N (N: number of bit) cycles in a typical pipeline. Like a pipeline, a SAR with more than 12 bits of accuracy usually requires some form of trimming or calibration.

2.2.3 Versus Flash

Despite the inherent parallelism, a pipelined ADC still requires accurate analog amplification in DACs and inter-stage gain amplifiers, and thus significant linear settling time.

A purely flash ADC, on the other hand, has a large bank of comparators, each consisting of wideband, low-gain preamps followed by a latch. The preamps, unlike those amplifiers in a pipelined ADC, need to provide gains that don't even have to be linear or accurate earning, only the comparators' trip points have to be accurate. As a result, a pipelined ADC cannot match the speed of a well-designed flash ADC.

Although extremely fast 8-bit flash ADCs (or their folding/interpolation variants) exist with sampling rates as high as 1.5GS/s, it is much harder to find a 10-bit flash, while 12-bit (or above) flash ADCs are not commercially viable products. This is simply because in a flash the number of comparators goes up by a factor of 2 for every extra bit of resolution, and at the same time each comparator has to be twice as accurate. In a pipeline, however, to a first order the complexity only increases linearly with the resolution, not exponentially.

At sampling rates obtainable by both a pipeline and a flash, a pipelined ADC tends to have much lower power consumption than a flash. A pipeline also tends to be less susceptible to comparator meta-stability. Comparator meta-stability in a flash can lead to sparkle-code errors (a condition in which the ADC provides unpredictable, erratic conversion results).

2.2.4 Conclusion

The pipelined ADC is the architecture of choice for sampling rates from a few MS/s up to 100MS/s+. Complexity goes up only linearly (not exponentially) with the number of bits, providing converters with high speed, high resolution, and low power at the same time. They are very useful for a wide range of applications, most notably in the digital communication area, where a converter's dynamic performance is often more important than traditional DC specifications like differential nonlinearity (DNL) and integral nonlinearity (INL). Their data latency is of little concern in most applications [3].

2.3 Architecture for 8-bit 40MHz ADC

2.3.1 Architecture [4][5]

The block diagram of a typical pipelined ADC is shown in Fig. 2.6. All of the pipelined stages are similar in structure. Each stage consists of a sample-and-hold amplifier, a Digital-to-Analog converter (DAC), a low resolution Analog-to-Digital sub-converter (ADSC), a subtractor, and a fix-gain amplifier. The beginning sample-and-hold relaxes the timing requirements of the first stage during its sampling phase by holding the instantaneous value of the analog input. Following the S/H, each stage samples and holds the output signals of the previous stage. The signal is coarsely quantized by the ADSC to produce the first 1 MSB’s and 1 bit for digital error correction. Then using a DAC, the quantized value is subtracted from original input signal to yield the output residue. For the output signal range is the same with the input signal range for each stage, this is made by the amplifier with gain of 2. The resulting residue signal is applied to the next stage for finer conversion on the next clock cycle. The function of the D/A, the subtraction, and the amplification of the remainder are combined into one single circuit called the multiplying DAC (MDAC). The last stage consists of a 2-bits flash ADC, and a thermometer-code-to-binary-code combinational logic.

Fig. 2.6 Architecture of 8-bit Pipeline ADC

After the signal has propagated through 8 stages, one complete conversion is produced. The total digital outputs from all stages are 14 bits. These operations work concurrently and enable the pipelined architecture to achieve a high throughput. The digital codes ate overlapped by 1 bit to perform digital error correction. Therefore, the total 14 bits from all stages are delayed properly and produced 8 bits [6][7]. Although a single-ended configuration is shown for simplicity, the actual implementation was fully differential.

The conceptual circuit of main stages of pipeline is shown in Fig. 2.7. The MDAC with SC configuration performs sample-and-hold function, DAC, subtraction and multiply by 2 functions. The ADSC consists of two flash converters. The input is sampled by the frontier S/H circuit to convert the analog signal to the two differential dc signal input. Then, the signal is compared by two comparators to decide where it is located on the residue chart. The decision level is ±1/4Vr (Vr: full swing of input voltage). The output digital codes are latched by the D-flip-flop which is used for doing pipeline. Because each stage’s output does not come out at the same time, we have to use flip-flop to latch them. From Fig.2.7, we can realize that the MDAC only needs to decide 3 conditions 2Vin-Vr, 2Vin, or 2Vin+Vr. The MDAC’s output is the next stage’s input. When the input signal is applied, each stage samples and quantizes, subtracts the quantized analog output signal of DAC, and passes the residue to the next stage with amplification for finer conversion. Every stage can get 2-bit digital output

00, 01 and 10, and be latched in to the pipeline path.

Fig 2.7 Main Stage Circuit and Transfer Curve

2.3.2 Timing Strategy

The design of our residue amplify circuit is a switch-capacitor S/H structure as shown in Fig.2.8. The basic ideal of switch-capacitor circuit is the charge transfer. The important issue is to transfer the charge totally without loss. Thus, two non-overlap clock phases clk1 clk2 are required. In order to cancel out the charge injection error, the fully differential structure and the bottom-plate technique is used in the residue amplify circuit. This will need two more advanced clock phases clk1p clk2p. For example, the clk1p control the switches on the top-plate of sample capacitors and turn off earlier before the switches on the bottom-plate so that the charge injection is signal independent. The addition phases, clk1a and clk2a, are needed for the ASDC. To avoid the noise being compared by comparators in the beginning of transferring, the comparator will start comparing until the charge redistribution has been finished and stabilized. The waveform is shown in Fig. 2.8.

Fig. 2.8 Clock Waveform

2.3.3 Digital Error Correction

Digital error correction is the name of the calibration technique that reduces the gain, keeps the voltage range constant with modified coding and tolerates greater comparator offset. A conceptual transfer function is shown in Fig.2.9. This kind of digital error correction is called the 1.5bit/stage algorithm. The comparator thresholds (ADSC) are at 1/4Vr and -1/4Vr; the DAC levels are at -1/2Vr, 0 and 1/2Vr. The codes are shown on top of the transfer function and the over-ranging part on the transfer function will be digitally corrected by the next stage except the last stage of the pipeline. The 1.5-bit/stage here represents the effective bits per stage after digital correction [8]. We can get 2-bit in each stage. The second bit is used for correction. When the input is less than the negative decision level, -1/4Vr, we simply get a 0 in the first bit and give another 0 in the second bit. The second bit is 0 means that no need to add 1 to the first bit. In the same way, when the input is greater than the positive decision level, +1/4Vr, we can get a 1 in the first bit and give another 0 in the second bit, meaning that

no need to get a 1 in the first bit and give another 0 in the second bit. When the input is in the un-distinguished region between -1/4Vr and +1/4Vr, we give a 0 in the first bit and give a 1 in the second bit. We can get 0 in this stage and residue is 2xVin. In the next stage, if the input is positive, then the first bit will be corrected because it will get a “10”. If the input is negative, then the next stage will get a “00”. And there is no need to change the “0” bit in the first stage.

The amplified residue remains within the conversion range of the next stage when the ADSC nonlinearity is between . Under these conditions, errors caused by the ADSC nonlinearity less than 1/2 LSB can be corrected. For example, see from Fig.2.9 when the input is in the “10” region and very close to the “01” region. If the comparator is wrong and decides the input as “01”. Then it will produce a residue of 2Vin. The residue voltage is the same as the real value, that it won’t affect the next few stages. And we can correct this bit by adding one to “01”.

LSB 2 /

±1

Fig. 2.9 Example of Digital Error Correction: First Stage to Next Stage

2.4 Non-ideality of Considerations

Charge Injection Error [8]

MOS switches introduce a significant amount of error due to the channel charge stored in the MOSFET device. The charge in the conductance channel is approximately^Cox(^Vgs−Vth). When the MOS switch is turned off, the amount of channel charge injected into the sampling capacitor represents an error source as a result of the sudden release of the charge under the MOS gate. The additional charge will cause a large error in the high resolution Switch-Capacitor circuit.

Clock Feed-through

The effect of clock feed-through is due to the gate-drain, gate-source parasitic capacitor.

Offset Error [9]

The offset error in a pipelined ADC results from the charge injection of reference switches and the mismatch of differential pairs.

Gain Error

The finite op-amp gain and the capacitor mismatch are the two major gain errors. The finite op-amp gain makes the settled voltage can’t reach the target level.

Chapter3

Circuit Design

3.1 Sample-and-Hold[9][10]

The most important and performance dominating circuit in the pipelined ADC is the input stage sample-and-hold (S/H) amplifier. Fig.3.1 shows the schematic diagram of the unity-gain S/H. The signal ground Vmid is the common-mode voltage of the output differential signal.

The architecture of the op-amp is a telescopic amplifier, which has an input common-mode voltage at 1.2V and an output common-mode voltage at 1.5V. The clock1, clock1p are used during the sample phase and clock2 is used during the hold phase. The clock1 and clock2 are non-overlap phases to prevent the charge loss on the path when both the clocks are at high level. The clock1p has the same rising edge to the clock1 phase, but the earlier falling edge takes the advantage of reducing the charge injection from the sampling switches. There is a switch connects output nodes during the sample phase, and then keeps the voltage of output nodes at the output common-mode and prevent saturation. That reduces the settling time when a non-saturated voltage needs to go back to the target voltage at hold phase.

Fig.3.1 Schematic diagram of sample-and-hold

3.1.1 Capacitors [11]

A certain minimum signal capacitor size is needed to maintain adequate noise performance and dynamic range. The SNR (signal to noise ratio) is calculated as

⎟⎟

where VR is the analog signal range and VN is the effective noise voltage. VN is mainly introduced by two components, one is the quantization noise and the other is thermal noise.

The quantization noise of a sine wave input is . The thermal noise is calculated as 3KT/C where one KT/C is introduced when a switch opens into a charge sampling capacitor, one KT/C is introduced when a switch opens into a charge holding capacitor, and the other one KT/C is introduced by all the possible noise sources.

12 / ) (LSB ²

By the MATLAB simulation, we can know that the SNR will be dominated by the quantization noise when the size of capacitor is from 0.1p-1p. Capacitor is found that satisfies the bandwidth requirements, capacitor matching requirements, and KT/C noise constraints. If the size is too large, the op-amp might not be able to reach the required speed. If the size is too small, the clock feed-through and charge-sharing effect will be worse. In this design, the Cs is 500fF.

3.1.2 Op-amp Gain Requirement

The DC open-loop gain of the op-amp limits the ADC resolution. Fig.3.2 simplified the S/H circuit. The capacitor Cp is the parasitic capacitor of the op-amp input differential pair.

The DC open-loop gain of the op-amp limits the ADC resolution. Fig.3.2 simplified the S/H circuit. The capacitor Cp is the parasitic capacitor of the op-amp input differential pair.