Background and motivation

By the rapid development and large demand of wireless communication, fully integrated monolithic radio transceivers are the most significant considerations for communication applications. The recent rapid growth of the wireless communication market inspires many people to research the concerned region with strong passion. Of such a many developments, enhanced operating frequency of CMOS technology encourages the designer to implement single-chip RF-to-baseband systems with it instead of bipolar or GaAs. One of the important design goals of portable wireless systems is low power consumption for long battery life. CMOS technology satisfies the requirements of low power consumption, low cost, reduced size, and also a few GHz operating frequency in wireless systems.

In typical RF front-end circuits, frequency synthesizer actions as a local oscillator (LO) for up/down conversion in communication transceivers. Fig. 1-1 shows a general block diagram of a transceiver. It contains a low-noise amplifier (LNA), a power amplifier (PA), mixers, and band-pass filters. In order not to distort the received signals, the excellent noise performance of frequency synthesizer is required. Besides, the switching time of circuit is also significant. The design of

phase-locked loops (PLLs) must generally deal with a tight tradeoff between the settling time and the amplitude of the ripple on the oscillator control line. In conclusion, we can judge a synthesizer by following three parameters: phase noise, sideband interferes (spurious tones), and locking time. Based on the above reason, we realize two integer-N type synthesizers, one sigma-delta fractional-N type synthesizer and two voltage-controlled oscillators.

LNA

System On a Chip (SOC) Receiving path

Transmitting path

QVCO

PLL

Fig. 1-1 Block diagram of a general transceiver front-end

Wireless LANs and Bluetooth provide wideband wireless connectivity between PCs and other consumer electronic devices, allowing access to core networks and other equipment in office and home environments. There are Home RF, IEEE 802.11 b/g, Bluetooth, and et cetera which operate at 2.4-GHz industrial, scientific, and medical (ISM) band. The Bluetooth standard provides a data rate of 1Mbps at 10m

distance [1]. In addition, the 802.11b standard provides data rates up to 11 Mbps with the direct sequence spread spectrum (DSSS) [2]. The 802.11a/g PHY are based on coded Orthogonal Frequency Division Multiplexing (OFDM) modulation [3-4]. The 802.11a standard operates in the 5-GHz unlicensed national information infrastructure (UNII) band, which provides a total available bandwidth of 300 MHz as compared to the 83.5 MHz available for 802.11b/g. The specifications for these standards summarize in Table 1-1.

Table 1-1 Frequency synthesizer in wireless communication systems

Parameter

spacing 1MHz 20MHz 20MHz 20MHz

Data rate 1Mbps 1 ~ 11Mbps

-120@3MHz -110@1MHz -110@1MHz -110@1MHz

Locking

time < 200µs < 200µs < 200µs < 200µs

For the noise consideration, the integer-N type has an unavoidable disadvantage that the frequency multiplication (by M) raises the phase noise level by 20log(M) dB.

In order to improve the phase noise, “Fractional-N” type frequency synthesizer was

introduced. The first work adopts a complete fractional-N frequency synthesizer, including third order sigma-delta modulator for high degree noise shaping. This architecture is used to allow a high reference frequency, fine step size, and low divided ratio to achieve low in-band phase noise. Besides, a capacitor is placed at the common mode node of the VCO to provide AC ground on this node. Therefore the phase noise of output signal is much lower. On the other hand, the power issue is also an important consideration. The frequency divider adopts the fully integrated multi-modulus type which is composed by seven stages-cascaded dual modulus asynchronous divide-by-2/3 circuits [5]. Hence, no power hunger preamplifier or buffer is needed to drive the divider. It is easy to design and integration compared with programmable pulse-swallow counter or phase-switching circuit [6-7].

Today there are many works focusing on fractional-N synthesizer, especially on sigma-delta modulation type. The in-band noise performance (such as spurious tone and phase noise) has been improved by adding sigma-delta modulator or other noise shaping circuits. Table 1-2 list this work compared with others.

Although the fractional-N type has better performance than the integer-N type, it is more complicated and more difficult to design. Furthermore, in order to improve the low phase noise, the VCO tuning range must be designed in smaller range for lower sensibility. Therefore, the multi-bits frequency bank circuits are used in this design.

Based on above reason, we realize two 2.4-GHz integer-N frequency synthesizers; one is for wide tuning range purpose and the other is for low power and low phase noise purpose. The wide tuning range synthesizer is suited for the concurrent dual-band transceiver front-end [10]. Only one synthesizer is required in

this topology. Otherwise, the wide-band means the much sensitive to phase noise performance. In order to reduce phase noise and spurious tones, we re-design the VCO part of synthesizer. Table 1-3 list these two 2.4-GHz integer-N frequency synthesizers compared with senior’s works. It shows that the power consumption is greatly reduced and noise performance is still better than senior’s works.

Table 1-2 Fractional-N frequency synthesizer: comparison of recent papers Performance

Sigma delta fractional-N synthesizer

JSSC Sep. 2004 [8] JSSC Mar. 2005 [9]

Technology CMOS 0.18µm CMOS 0.18µm SiGe BiCMOS 0.5µm

Architecture

frequency 2.4GHz 2.1GHz 2.4GHz

Reference

frequency 16MHz 35MHz 40MHz

Output frequency resolution

125kHz 35Hz 468.75kHz

3dB closed

loop BW 100kHz 700kHz 100kHz

Phase noise -118.4dBc/Hz

@1MHz

-112dBc/Hz

@1MHz

-120dBc/Hz

@1MHz

Spur tones -56.5dBc

@3.125MHz -60dBc -50dBc

Settling time 30µs 7µs 30µs

Total power

consumption 22.9mW 28mW 99mW

Table 1-3 Integer-N frequency synthesizer: comparison of senior’s works

Technology CMOS 0.18µm CMOS 0.18µm CMOS 0.25µm CMOS 0.25µm Architecture Integer-N (11

stages of %2/3)

frequency 1MHz 1MHz 1MHz 1MHz

2.123 ~ 2.786 2.371 ~ 2.678

-120.5 @3MHz -102 @1MHz -88.4 @1MHz Spurious

consumption 38.4mW 28.3mW 87.5mW 58.6mW

Recently, there are still many works focusing on integer-N type synthesizer because the system requirement is not stringent in the short-distance communication systems such as Bluetooth, ZigBee, WLAN, and etc. Table 1-4 list these two synthesizers compared with recent papers. We can see that the power consumption and phase noise of these two synthesizers is better than most of recent papers.

Table 1-4 Integer-N frequency synthesizer: comparison of recent papers

Technology CMOS 0.18µm

Architecture Integer-N Integer-N Integer-N

Fractional-N Integer-N

frequency 1MHz 1MHz 11MHz 256MHz 500kHz 13MHz

2.123 ~

Power 38.4mW 28.3mW 27.5mW 49.5mW 15mW 55mW

Voltage-Controlled Oscillator (VCO) plays an important role in communication systems because the phase noise of the VCO determines the out-of-band noise of the frequency synthesizer. In recently high-frequency operation VCO designs, high power consumption is always an unavoidable limitation, which can be obviously observed in [15-19, 21-24]. The design of VCO becomes even more challenging in RF applications, where stringent requirements of phase noise and power consumption remain as the toughest tasks that RFIC engineers have to deal with. The local

networks) LANs and Bluetooth system must have sufficient tuning ranges and good phase noise characteristics. In order to extend the tuning range of VCO, enlarge the varactor gain must be used. We choose the suitable p-n junction varactor for large varactor gain. Hence, we implement a 5.2-GHz low power, low cost, and wide tuning range voltage-controlled oscillator with 0.35-µm SiGe BiCMOS process. Table 1-5 lists this work compared with others.

In addition, fully integrated voltage-controlled oscillators (VCOs) are important building blocks for implementation of a single radio-frequency chip in today’s communication systems. In low-IF or direct conversion transceivers, quadrature signals are required for base-band (de)modulation. It is important to offer quadrature generator circuits as minimal power consumption. However, the local oscillator circuits must have sufficient lower power consumption and better phase noise characteristics. Traditional quadrature VCO used additional transistors coupling between two core circuits, so the 1/f come from coupling transistors results in worse phase noise. The new quadrature VCO architecture is presented in [21]. The back-gate (body) node of transistor is used for coupling circuit. The triple-well technique makes this idea practicable. Hence, we also implement a 2.4-GHz low power, low phase noise back-gate quadrature VCO with 0.18-µm triple-well CMOS process. Table 1-6 lists this work compared with others.

Table 1-5 Low power and wide tuning-range SiGe VCO: comparison of recent papers

Table 1-6 Low phase noise quadrature VCO with back-gate coupling: comparison of