應用於無線區域網路與藍芽系統之全積體化低功率低相位雜訊整數型及三角積分之分數型頻率合成器

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(1)國立交通大學電信工程學系碩士論文應用於無線區域網路與藍芽系統之全積體化低功率低相位雜訊整數型及三角積分之分數型頻率合成器 Fully Integrated, Low-Power, Low Phase-Noise Integer-N and Sigma-Delta Fractional-N Frequency Synthesizers for Wireless LAN and Bluetooth Applications. 研究生：連偉誠指導教授：周復芳. 中. 華. 民. 國. 九十四. 博士. 年. 六. 月.

(2) 應用於無線區域網路與藍芽系統之全積體化低功率低相位雜訊整數型及三角積分之分數型頻率合成器 Fully Integrated, Low-Power, Low Phase-Noise Integer-N and Sigma-Delta Fractional-N Frequency Synthesizers for Wireless LAN and Bluetooth Applications. 研究生：連偉誠 Student：Wei‐Cheng Lien 指導教授：周復芳博士 Advisor：Dr. Christina F. Jou 國立交通大學電信工程學系碩士班碩士論文 A Thesis Submitted to Department of Communication Engineering College of Electrical Engineering and Computer Science National Chiao Tung University In Partial Fulfillment of the Requirements For the Degree of Master of Science In Communication Engineering June 2005 Hsinchu, Taiwan, Republic of China . 中. 華. 民. 國. 九十四. 年. 六. 月.

(3) 應用於無線區域網路與藍芽系統之全積體化低功率低相位雜訊整數型及三角積分之分數型頻率合成器研究生：連偉誠. 指導教授：周復芳博士. 國立交通大學電信工程學系碩士班摘要本論文中主要提出三角積分之分數型頻率合成器，另外還提出兩種不同架構之整數型頻率合成器及兩種不同架構之壓控振盪器，這些電路皆應用於無線區域網路及藍芽無線通訊上。首先三角積分之分數型頻率合成器，利用0.18微米CMOS製程實現此頻率合成器，以低功率消耗及低相位雜訊為設計主要考量。量測結果如下：可調頻寬為 2381 ~ 2606兆赫茲(於頻率控制訊號為10時)，相位雜訊為-118.4分貝/赫茲@1兆赫茲，總功率消耗22.9毫瓦，鎖定時間為30微秒，寄生雜頻較主頻低56.5分貝。接下來是利用0.18微米CMOS製程實現兩個整數型頻率合成器：第一個為寬頻之頻率合成器，其量測結果如下：可調頻寬為2178 ~ 2629兆赫茲(於頻率控制訊號為011時)，相位雜訊為-108.8分貝/赫茲@1兆赫茲，總功率消耗38.4毫瓦，鎖定時間為40微秒，寄生雜頻較主頻低26.15分貝；第二個為低功率、低相位雜訊之頻率合成器，其量測結果如下：可調頻寬為2399 ~ 2633兆赫茲(於頻率控制訊號為10時)，相位雜訊為-114.0分貝/赫茲@1兆赫茲，總功率消耗28.3毫瓦，鎖定時間為90微秒，寄生雜頻較主頻低41.50分貝。最後利用0.35微米SiGe BiCMOS製程實現寬頻、低功率之壓控振盪器，量測結果如下：可調頻寬為4310 ~ 5430兆赫茲，相位雜訊為-114.1分貝/赫茲@1兆赫茲，總功率消耗16.7毫瓦。另外利用0.18微米CMOS製程實現四相位壓控振盪器，利用基底端做訊號耦合。量測結果如下：可調頻寬為2093 ~ 2206兆赫茲(於頻率控制訊號為100時)，相位雜訊為-124.3分貝/赫茲@1兆赫茲，總功率消耗19.8毫瓦。. I.

(4) Fully Integrated, Low-Power, Low Phase-Noise Integer-N and Sigma-Delta Fractional-N Frequency Synthesizers for Wireless LAN and Bluetooth Applications Student: Wei‐Cheng Lien . Advisor：Dr. Christina F. Jou Institute of Communication National Chiao Tung University . Abstract This thesis contents a sigma-delta fractional-N synthesizer mainly. Besides, it contents two integer-N synthesizers and two voltage-controlled oscillators. These circuits are implemented for WLAN and Bluetooth applications. First, we describe the sigma-delta fractional-N frequency synthesizer, using 0.18µm CMOS technology. Design consideriation contants low power consumption and the low phase noise. The measurement results are listed as following: the oscillation frequency is tunable between 2381 ~ 2606-MHz (as frequency bank is 10), phase noise is -118.4dBc/Hz @1-MHz offset, the power consumption is 22.9mW, locking time is approximately 30µs, and spurious tone is -56.5dBc. Then we describe two integer-N frequency synthesizers, using 0.18µm CMOS technology. One is wide tuning range frequency synthesizer. The measurement results are listed as following: the oscillation frequency is tunable between 2178 ~ 2629-MHz (as frequency bank is 011), phase noise is -108.8dBc/Hz @1-MHz offset, the power consumption is 38.4mW, locking time is approximately 40µs, and spurious tone is -26.15dBc. Another is low power, low phase noise range frequency synthesizer. The measurement results are listed as following: the oscillation frequency is tunable between 2399 ~ 2633-MHz (as frequency bank is 10), phase noise is -114.0dBc/Hz @1-MHz offset, the power consumption is 28.3mW, locking time is approximately 90µs, and spurious tone is -41.50dBc. Finally we describe a wide tuning range, low power VCO, using 0.35µm SiGe BiCMOS technology. The measurement results are listed as following: the oscillation frequency is tunable between 4310 ~ 5430-MHz, phase noise is -114.1dBc/Hz @1-MHz offset, and the power consumption is 16.7mW. Besides we also describe a low power, low phase back-gate quadrature VCO, using 0.18µm CMOS technology. The measurement results are listed as following: the oscillation frequency is tunable between 2093 ~ 2206-MHz (as frequency bank is 100), phase noise is -124.3dBc/Hz @1-MHz offset, and the power consumption is 19.8mW.. II.

(5) Acknowledgement 能夠順利取得碩士學位，首先要感謝指導教授周復芳老師給予悉心的指導與教誨，在射頻積體電路設計領域上從空有興趣直到略有所得，而能夠一探射頻積體電路領域的廟堂之美；感謝口試老師：張志揚教授、胡政吉博士在論文上的指導與建議，使得本論文得以更加完整。還有感謝國家晶片系統設計中心提供先進的半導體製程，以及研究員蕭旭峰先生在量測方面的協助，讓晶片的製作與量測得以順利完成。感謝實驗室的博士班學長鄭國華常常給予我們技術與設計環境上的幫助和意見交換，不厭其煩地帶領學弟們成長；實驗室的學長呂盈蒼、陳政良、劉炳宏、汪揚在課業、電路設計及生活上的幫忙；實驗室的同窗好友政宏、家良、欽賢、柏達、俊賢，在和你們的談話之中，常常讓我觸發出許多珍貴的靈感，課業和生活上也得到你們許多協助，有了大家的陪伴，使得平淡的研究生活多了不少樂趣，這兩年的生活因為你們而顯得多采多姿。還有實驗室可愛的學弟們：仕豪、政展、博揚、秋榜、文明、宏斌，這一年來的陪伴，你們不斷的發問是讓我努力充實自已的原動力，幫忙打理實驗室事務，讓我們才得以致力於研究工作。最重要的是感謝我的父母親，雖然他們沒受過高等教育，但是他們秉持教育子女的信念，用盡苦心撫育和教導，並提供了我穩定的環境，讓我能專心致力於自我的發展。感謝所有的親朋好友，一直給我關懷與鼓勵，千萬個感謝都無以表達我心中的感受，今日之我是你們合力所造就完成，由衷的感謝各位。. Wei-Cheng. III. June 28, 2005..

(6) CONTENTS Chinese Abstract ....................................................................................... I English Abstract .......................................................................................II Acknowledgement ..................................................................................III Contents ................................................................................................. IV List of Tables......................................................................................... VII List of Figures ......................................................................................VIII. Chapter 1 Introduction .............................................................................. 1 1.1 Background and motivation................................................................................ 1 1.2 Thesis organization ............................................................................................11. Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer.................................... 12 2.1 Architectures..................................................................................................... 12 2.2 Design considerations....................................................................................... 13 2.2.1 Voltage-controlled oscillator................................................................... 14 2.2.2 Sigma-delta modulator ........................................................................... 23 2.2.3 Fully programmable multi-modulus frequency divider.......................... 31 2.2.4 Phase frequency detector ........................................................................ 34 2.2.5 Charge pump........................................................................................... 35 2.2.6 Loop filter ............................................................................................... 37 2.3 Whole circuit simulation and layout................................................................. 39 2.4 Measurement results ......................................................................................... 44 2.4.1 VCO measurement results ...................................................................... 47 2.4.2 Whole circuit measurement results......................................................... 48 2.5 Measurement Discussion.................................................................................. 53. IV.

(7) Chapter 3 2.4GHz Wide Tuning-Range and Low Power, Low Phase-Noise Integer-N Frequency Synthesizers ................ 55 3.1 A 2.4-GHz wide tuning-range, quadrature output integer-N frequency synthesizer suited for dual band receiver front end .......................................... 55 3.1.1 Circuit description .................................................................................. 55 3.1.2 Whole circuit simulation and layout....................................................... 63 3.1.3 Measurement results ............................................................................... 67 3.1.3.1 VCO measurement results......................................................... 68 3.1.3.2 Whole circuit measurement results ........................................... 71 3.1.4 Measurement Discussion........................................................................ 76 3.2 A 2.4-GHz low power, low phase-noise, quadrature output integer-N frequency synthesizer ....................................................................................... 78 3.2.1 Circuit description .................................................................................. 78 3.2.2 Whole circuit simulation and layout....................................................... 84 3.2.3 Measurement Results.............................................................................. 87 3.2.3.1 VCO measurement results......................................................... 88 3.2.3.2 Whole circuit measurement results ........................................... 91 3.2.4 Measurement Discussion........................................................................ 97 3.3 Comparison of Measurement results ................................................................ 98. Chapter 4 5.2-GHz Low Power, Wide Tuning-Range SiGe BiCMOS VCO and 2.4-GHz Low Power, Low Phase-Noise, Quadrature Output CMOS VCO ...................................... 100 4.1 A 5.2-GHz low power, wide tuning-range SiGe BiCMOS VCO ................... 100 4.1.1 Circuit description ................................................................................ 100 4.1.2 Simulation results and layout ............................................................... 104 4.1.3 Measurement results ............................................................................. 107 4.1.4 Measurement Discussion.......................................................................115 4.2 A 2.4-GHz low phase-noise and quadrature output back-gate CMOS VCO........ ..........................................................................................................................116 4.2.1 Circuit description .................................................................................116 4.2.2 Simulation results and layout ............................................................... 120 4.2.3 Measurement results ............................................................................. 124 4.2.4 Discussion............................................................................................. 130. V.

(8) Chapter 5 Conclusions and Future Works ............................................ 132 5.1 Conclusions .................................................................................................... 132 5.2 Future works ................................................................................................... 134. REFERENCES ..................................................................................... 136. Publication Remarks ............................................................................. 140. VI.

(9) List of Table Table 1-1. Frequency synthesizer in wireless communication systems ................... 3 Table 1-2. Fractional-N frequency synthesizer: comparison of recent papers......... 5 Table 1-3. Integer-N frequency synthesizer: comparison of senior’s works............ 6 Table 1-4. Integer-N frequency synthesizer: comparison of recent papers.............. 7 Table 1-5. Low power and wide tuning-range SiGe VCO: comparison of recent papers ...................................................................................................... 9 Table 1-6. Low phase noise quadrature VCO with back-gate coupling: comparison of recent papers ..................................................................................... 10 Table 2-1. Optimized loop filter elements.............................................................. 38 Table 2-2. Performance summary of sigma-delta fractional-N synthesizer........... 43 Table 2-3. Summary of specifications.................................................................... 54 Table 2-4. DC current consumption ....................................................................... 54 Table 3-1. Optimized loop filter elements.............................................................. 62 Table 3-2. Performance summary of wide tuning range integer-N synthesizer..... 66 Table 3-3. Summary of specifications.................................................................... 77 Table 3-4. DC current consumption ....................................................................... 77 Table 3-5. Optimized loop filter elements.............................................................. 83 Table 3-6. Performance summary of low power, low phase-noise integer-N synthesizer............................................................................................. 85 Table 3-7. Summary of specifications.................................................................... 98 Table 3-8. DC current consumption ....................................................................... 98 Table 3-9. Performance summaries with two integer-N frequency synthesizer .... 99 Table 4-1. Post-simulation result of the low-power VCO with corner case ........ 106 Table 4-2. Simulation and measurement performance summary..........................115 Table 4-3. Summary of corner case performance ................................................ 123 Table 4-4. Simulation and measurement performance summary......................... 131 Table 5-1. Measurement data compared to spec requirement.............................. 133 . VII.

(10) List of Figure Fig. 1-1.. Block diagram of a general transceiver front-end..................................... 2. Fig. 2-1.. General architecture of PLL (a) Integer-N type (b) Fractional-N type ... 13. Fig. 2-2.. Behavioral model of an ideal LC oscillator ............................................ 15. Fig. 2-3.. Conventional CMOS LC-tank VCO architecture ................................... 16. Fig. 2-4.. Schematic of VCO (a) core circuit part (b) buffer stage......................... 19. Fig. 2-5.. Spiral inductor in this synthesizer (a)layout (b)equivalent circuit model ...................................................................................................... 20. Fig. 2-6.. MOS varactor in this synthesizer (a)layout (b)equivalent circuit model 20. Fig. 2-7.. Tuning curve of VCO (corner case: TT; Bank condition: 00 10 11) ...... 21. Fig. 2-8.. Tuning curve of VCO (corner case: TT, FF, SS; Bank condition: 10).... 21. Fig. 2-9.. Tuning curve of VCO (corner case & Bank condition : TT&10, FF&11, SS&00) ................................................................................................... 21. Fig. 2-10. Output swing of VCO (corner case: TT, Bank condition: 10) ................ 22 Fig. 2-11. Phase noise of VCO (corner case & Bank condition : TT&10, FF&11, SS&00) ................................................................................................... 22 Fig. 2-12. General fractional-N frequency synthesizer ........................................... 23 Fig. 2-13. Fractional-N frequency synthesizer with sigma-delta modulator ........... 24 Fig. 2-14. Noise shaping of a sigma-delta modulator.............................................. 25 Fig. 2-15. First order sigma-delta modulator........................................................... 26 Fig. 2-16. Transfer function of first order sigma-delta modulator .......................... 26 Fig. 2-17. Influence of first order sigma-delta modulator on signal power............. 28 Fig. 2-18. Influence of first order sigma-delta modulator on in-band signal .......... 28 Fig. 2-19. Third order sigma-delta modulator ......................................................... 29 Fig. 2-20. Transfer function of third order sigma-delta modulator ......................... 29 Fig. 2-21. Influence of first order sigma-delta modulator on signal power............. 30 Fig. 2-22. Influence of first order sigma-delta modulator on in-band signal .......... 30 Fig. 2-23. Schematic of sigma-delta modulator in this synthesizer......................... 31 Fig. 2-24. Fully programmable multi-modulus frequency divider .......................... 32 Fig. 2-25. Differential source coupled logic (SCL)................................................. 33 Fig. 2-26. Output signal of frequency divider simulated with VCO ....................... 34 Fig. 2-27. Phase frequency detector circuit ............................................................. 35 Fig. 2-28. Phase frequency detector timing diagram............................................... 35 Fig. 2-29. Limitation caused by dead zone.............................................................. 35 VIII.

(11) Fig. 2-30. Schematic of charge pump...................................................................... 36 Fig. 2-31. Phase difference versus average output current...................................... 37 Fig. 2-32. Third order loop filter ............................................................................. 38 Fig. 2-33. PLL loop filter design software .............................................................. 38 Fig. 2-34. Building blocks of sigma-delta fractional-N frequency synthesizer....... 39 Fig. 2-35. Whole circuit open loop simulation (Behavior level)............................. 40 Fig. 2-36. Whole circuit close loop simulation (Behavior level) ............................ 40 Fig. 2-37. Locking transient simulation (Transistor level) ...................................... 41 Fig. 2-38. Output spectrum of sigma-delta fractional-N frequency synthesizer ..... 41 Fig. 2-39. Output spectrum of traditional fractional-N frequency synthesizer ....... 42 Fig. 2-40. Layout of sigma-delta fractional-N frequency synthesizer..................... 42 Fig. 2-41. Die-photograph of sigma-delta fractional-N frequency synthesizer....... 43 Fig. 2-42. Measurement instruments (a) Agilent E5052A signal source analyzer (b)HP 8563E spectrum analyzer (c) Agilent E4407B spectrum analyzer (d) HP 54610B oscilloscope (e) HP E3611A power supply (f) HP 33120A function generator ..................................................................... 45 Fig. 2-43. Testing board of sigma-delta fractional-N frequency synthesizer .......... 46 Fig. 2-44. Measured tuning curve of VCO in this synthesizer under different bank conditions................................................................................................ 47 Fig. 2-45. Tuning curve of VCO in this synthesizer at bank 10 (Simulation vs. measurement).......................................................................................... 47 Fig. 2-46. Measured output spectrum of VCO in this synthesizer .......................... 48 Fig. 2-47. Phase noise of VCO in this synthesizer (Bank 10, at LAB) ................... 48 Fig. 2-48. Measured phase noise of VCO in this synthesizer @ 1-MHz offset (Bank 10) ................................................................................................ 48 Fig. 2-49. Measured locking spectrum (a) at 2401MHz (b) at 2403MHz (c) at 2449MHz (d) at 2451MHz (e) at 2481MHz (f) at 2483MHz................. 50 Fig. 2-50. Measured locking spectrum (a) at 2401.125MHz (b) at 2403.125MHz (c) at 2449.125MHz (d) at 2451.125MHz (e) at 2481.125MHz (f) at 2483.125MHz ......................................................................................... 51 Fig. 2-51. Measured reference spurs of locking spectrum ...................................... 51 Fig. 2-52. (a) Measurement consideration of settling time (b) Transient of settling time (c) Zoom in of the transient of settling time................................... 53 Fig. 3-1.. Block diagram of concurrent dual-band receiver.................................... 56. Fig. 3-2.. Frequency plans of dual-band receiver (a) 2.45-GHz receiving path (b) 5.25-GHz receiving path......................................................................... 56. Fig. 3-3.. Schematic of QVCO............................................................................... 58. Fig. 3-4.. MOS varactor in this synthesizer (a)layout (b)equivalent circuit model ...................................................................................................... 58 IX.

(12) Fig. 3-5.. Spiral inductor in this synthesizer (a)layout (b)equivalent circuit model ...................................................................................................... 59. Fig. 3-6.. Tuning curve of QVCO (Capacitor Bank).............................................. 59. Fig. 3-7.. Tuning curve of QVCO (Corner Case)................................................... 60. Fig. 3-8.. Output Swing of QVCO ......................................................................... 60. Fig. 3-9.. Phase noise of QVCO (Capacitor bank)................................................. 61. Fig. 3-10. Phase noise of QVCO (Corner case) ...................................................... 61 Fig. 3-11. Output signal of frequency divider simulated with VCO....................... 62 Fig. 3-12. Building blocks of wide tuning range integer-N frequency synthesizer 63 Fig. 3-13. Locking transient simulation (Behavior level) ....................................... 64 Fig. 3-14. Locking transient simulation (Transistor level)...................................... 64 Fig. 3-15. Layout of wide tuning range integer-N frequency synthesizer .............. 65 Fig. 3-16. Die-photograph of wide tuning range integer-N frequency synthesizer .............................................................................................. 65 Fig. 3-17. Testing board of wide tuning range integer-N synthesizer ..................... 67 Fig. 3-18. Measured characteristic of QVCO in this synthesizer............................ 68 Fig. 3-19. Measured tuning curve of QVCO in this synthesizer (a) under different bank conditions (b) at bank 011 (c) at bank 111 (d) at bank 000 .......................................................................................................... 69 Fig. 3-20. Measured output spectrum of QVCO in this synthesizer ....................... 69 Fig. 3-21. Phase noise of QVCO in this synthesizer (Bank 011, at CIC) ............... 70 Fig. 3-22. Phase noise of QVCO in this synthesizer (Bank 011, at LAB) .............. 71 Fig. 3-23. Measured phase noise of QVCO in this synthesizer (Bank 011, at LAB) (a) at 1-MHz offset (b) at 3-MHz offset....................................... 71 Fig. 3-24. Data measured from signal source analyzer (a) at 2400-MHz (b) at 2448-MHz............................................................................................... 72 Fig. 3-25. Measured locking spectrum at (a)2400MHz (b)2448MHz (c)2480MHz............................................................................................ 73 Fig. 3-26. Measured phase noise while locking at (a) 2400MHz (b) 2448MHz (c) 2480MHz ................................................................................................ 74 Fig. 3-27. (a) Measurement consideration of settling time (b) Transient of settling time (c) Zoom in of the transient of settling time ...................... 76 Fig. 3-28. Schematic of QVCO............................................................................... 79 Fig. 3-29. Spiral inductor in this synthesizer (a)layout (b)equivalent circuit model ...................................................................................................... 80 Fig. 3-30. MOS varactor in this synthesizer (a)layout (b)equivalent circuit model ...................................................................................................... 80 Fig. 3-31. Tuning range of QVCO (Capacitor bank) .............................................. 81. X.

(13) Fig. 3-32. Tuning range of QVCO (Corner case).................................................... 81 Fig. 3-33. Tuning range of QVCO (Corner case with bank)................................... 82 Fig. 3-34. Output Swing of QVCO ......................................................................... 82 Fig. 3-35. Phase noise of QVCO (Capacitor bank)................................................. 82 Fig. 3-36. Phase noise of QVCO (Corner case) ...................................................... 82 Fig. 3-37. Output signal of frequency divider simulated with VCO....................... 83 Fig. 3-38. Locking transient simulation (Behavior level simulation) ..................... 84 Fig. 3-39. Locking transient simulation (Transistor level simulation).................... 84 Fig. 3-40. Layout of low power, low phase-noise integer-N frequency synthesizer .............................................................................................. 86 Fig. 3-41. Die-photograph of low power, low phase-noise integer-N frequency synthesizer .............................................................................................. 86 Fig. 3-42. Testing board of low power, low phase-noise integer-N frequency synthesizer .............................................................................................. 87 Fig. 3-43. Measured characteristic of QVCO in this synthesizer............................ 88 Fig. 3-44. Measured tuning curve of QVCO in this synthesizer (a) under different bank conditions (b) at bank 10................................................. 89 Fig. 3-45. Measured output spectrum of QVCO in this synthesizer ....................... 89 Fig. 3-46. Phase noise of QVCO in this synthesizer (Bank 10, at CIC) ................. 90 Fig. 3-47. Phase noise of QVCO in this synthesizer (Bank 10, at LAB)................ 90 Fig. 3-48. Measured phase noise of QVCO in this synthesizer (Bank 10, at LAB) (a) at 1-MHz offset (b) at 3-MHz offset ................................................. 91 Fig. 3-49. Measured locking spectrum (a) All performance of synthesizer (b) Output spectrum (c) Phase noise performance ....................................... 93 Fig. 3-50. Measured phase noise (close-loop synthesizer vs. VCO only)............... 93 Fig. 3-51. (a) Measurement result while divider ratio changing from 2448 to 2480 (b) Zoom in of measurement results.............................................. 94 Fig. 3-52. Measured locking spectrum (a) at 2400-MHz (b) at 2401-MHz (c) at 2402-MHz (d) at 2403-MHz................................................................... 95 Fig. 3-53. (a) Measurement consideration of settling time (b) Transient of settling time (c) Zoom in of the transient of settling time ...................... 97 Fig. 4-1.. Schematic of the low-power VCO ........................................................ 101. Fig. 4-2.. Spiral inductor in this VCO (a) layout (b) equivalent circuit model .... 102. Fig. 4-3.. Junction varactor in this VCO (a) layout (b) equivalent circuit model 102. Fig. 4-4.. Schematic of the output buffer stage..................................................... 104. Fig. 4-5.. Layout of the low-power VCO ............................................................. 105. Fig. 4-6.. Shielded signal PAD structure .............................................................. 105. Fig. 4-7.. Tuning curve of the low-power VCO ................................................... 106 XI.

(14) Fig. 4-8.. Phase noise of the low-power VCO...................................................... 107. Fig. 4-9.. Output waveforms of the buffer stages ................................................. 107. Fig. 4-10. On wafer measurement arrangement .................................................... 108 Fig. 4-11. Die-photograph of the low-power VCO ............................................... 108 Fig. 4-12. Measured output spectrum of VCO (On wafer).................................... 108 Fig. 4-13. Tuning curve of the low-power VCO (On wafer)................................. 109 Fig. 4-14. Measured output spectrum of VCO (Bond-wire) ................................. 109 Fig. 4-15. Tuning curve of the low-power VCO (Bond-wire)................................110 Fig. 4-16. Measured phase noise of the low-power VCO (Bond-wire)..................110 Fig. 4-17. Measured consideration (Adding a DC-blocking capacitor and De-coupling capacitor) ..........................................................................111 Fig. 4-18. Testing board of the low-power VCO....................................................111 Fig. 4-19. Measured output spectrum of the low-power VCO (With DC-block and de-coupling capacitor) ....................................................................112 Fig. 4-20. Tuning curve of the low-power VCO (With DC-block and de-coupling capacitor) ...........................................................................112 Fig. 4-21. Measured phase noise of VCO (With DC-block and de-coupling capacitor) ...............................................................................................112 Fig. 4-22. Phase noise of the low-power VCO (With DC-block and de-coupling capacitor) ...............................................................................................113 Fig. 4-23. Output power level of the low-power VCO (With DC-block and de-coupling capacitor) ...........................................................................113 Fig. 4-24. (a) Measured characteristic of VCO (b) Measured Kvco of VCO ........114 Fig. 4-25. Measured phase noise of VCO ..............................................................114 Fig. 4-26. (a) Architecture of conventional quadrature VCO (b) Small-signal equivalent circuit of the circled part ......................................................117 Fig. 4-27. (a) Architecture of the fabricated back-gate coupled LC-QVCO (b) Small-signal equivalent circuit of the circled part.................................118 Fig. 4-28. Phase noise comparison of conventional QVCO, differential VCO, and back-gate coupling QVCO..............................................................118 Fig. 4-29. Schematic of the back-gate coupling quadrature VCO .........................119 Fig. 4-30. The spiral inductor in this QVCO (a) layout (b) equivalent circuit model .................................................................................................... 120 Fig. 4-31. The MOS varactor in this QVCO (a) layout (b) equivalent circuit model .................................................................................................... 120 Fig. 4-32. Tuning curve of the back-gate coupling quadrature VCO.................... 121 Fig. 4-33. Output waveform of the back-gate coupling quadrature VCO............. 121 Fig. 4-34. Phase noise of the back-gate coupling quadrature VCO ...................... 122. XII.

(15) Fig. 4-35. Layout of the back-gate coupling quadrature VCO.............................. 122 Fig. 4-36. Measurement consideration.................................................................. 124 Fig. 4-37. Die-photograph of the back-gate coupling quadrature VCO................ 124 Fig. 4-38. Measured output spectrum of the back-gate coupling quadrature VCO (On wafer)............................................................................................. 125 Fig. 4-39. Tuning curve of the back-gate coupling quadrature VCO.................... 125 Fig. 4-40. Testing board of the back-gate coupling quadrature VCO ................... 125 Fig. 4-41. Measured output spectrum of the back-gate coupling quadrature VCO...................................................................................................... 126 Fig. 4-42. Measured tuning curve of the back-gate coupling quadrature VCO .... 126 Fig. 4-43. Output power level of the back-gate coupling quadrature VCO .......... 126 Fig. 4-44. (a) Measured tuning curve compared with simulation (Bank 100) (b) Measured tuning curve compared with re-simulation (Bank 100) ....... 127 Fig. 4-45. Phase noise of the back-gate coupling quadrature VCO ...................... 128 Fig. 4-46. The measured the phase noise of the back-gate coupling quadrature VCO (Bond-wire) (a) at 1-MHz offset (b) at 3-MHz offset ................. 128 Fig. 4-47. Measured characteristic of the back-gate coupling quadrature VCO at bank 100 ............................................................................................... 129 Fig. 4-48. Measured phase noise of the back-gate coupling quadrature VCO...... 129 Fig. 5-1.. The building blocks of sigma-delta fractional-N frequency synthesizer with spurs compensation technique................................... 135. XIII.

(16) Chapter 1 Introduction. Chapter 1 Introduction. 1.1 Background and motivation By the rapid development and large demand of wireless communication, fully integrated monolithic radio transceivers are the most significant considerations for communication applications. The recent rapid growth of the wireless communication market inspires many people to research the concerned region with strong passion. Of such a many developments, enhanced operating frequency of CMOS technology encourages the designer to implement single-chip RF-to-baseband systems with it instead of bipolar or GaAs. One of the important design goals of portable wireless systems is low power consumption for long battery life. CMOS technology satisfies the requirements of low power consumption, low cost, reduced size, and also a few GHz operating frequency in wireless systems. In typical RF front-end circuits, frequency synthesizer actions as a local oscillator (LO) for up/down conversion in communication transceivers. Fig. 1-1 shows a general block diagram of a transceiver. It contains a low-noise amplifier (LNA), a power amplifier (PA), mixers, and band-pass filters. In order not to distort the received signals, the excellent noise performance of frequency synthesizer is required. Besides, the switching time of circuit is also significant. The design of. -1-.

(17) Chapter 1 Introduction. phase-locked loops (PLLs) must generally deal with a tight tradeoff between the settling time and the amplitude of the ripple on the oscillator control line. In conclusion, we can judge a synthesizer by following three parameters: phase noise, sideband interferes (spurious tones), and locking time. Based on the above reason, we realize two integer-N type synthesizers, one sigma-delta fractional-N type synthesizer and two voltage-controlled oscillators.. Band pass filter. mixer. IFip IFin. Antenna. LNA. RFp RFn. Band pass filter. mixer. Receiving path. IFqp IFqn. LOin. LOip Frequency Synthesizer. T/R switch. PLL LOqn. LOqp. Transmitting path RFp. Low pass filter. RFn. RF front-end. mixer. IFqp IFqn. mixer. PA. (MAC). QVCO Low pass filter. Baseband processor. IFip IFin. System On a Chip (SOC). Fig. 1-1 Block diagram of a general transceiver front-end Wireless LANs and Bluetooth provide wideband wireless connectivity between PCs and other consumer electronic devices, allowing access to core networks and other equipment in office and home environments. There are Home RF, IEEE 802.11 b/g, Bluetooth, and et cetera which operate at 2.4-GHz industrial, scientific, and medical (ISM) band. The Bluetooth standard provides a data rate of 1Mbps at 10m. -2-.

(18) Chapter 1 Introduction. distance [1]. In addition, the 802.11b standard provides data rates up to 11 Mbps with the direct sequence spread spectrum (DSSS) [2]. The 802.11a/g PHY are based on coded Orthogonal Frequency Division Multiplexing (OFDM) modulation [3-4]. The 802.11a standard operates in the 5-GHz unlicensed national information infrastructure (UNII) band, which provides a total available bandwidth of 300 MHz as compared to the 83.5 MHz available for 802.11b/g. The specifications for these standards summarize in Table 1-1.. Table 1-1 Frequency synthesizer in wireless communication systems IEEE 802.11 a (U-NII, USA) [4] 5150 ~5250 (lower) 5250 ~ 5350 (middle) 5725 ~ 5825 (upper). Parameter. Bluetooth (ISM) [1]. IEEE 802.11 b (ISM, USA) [2]. IEEE 802.11 g (ISM, USA) [3]. RF frequency (MHz). 2402 ~ 2480. 2400 ~ 2483.5. 2400 ~ 2483.5. 78. 6 (Max.). 6 (Max.). 12. 1MHz. 20MHz. 20MHz. 20MHz. 1Mbps. 1 ~ 11Mbps (CCK). 1 ~ 11Mbps (CCK) 6 ~ 54Mbps (OFDM). 6 ~ 54Mbps (OFDM). Quadrature outputs. Yes. No. Yes. Yes. Phase noise (dBc/Hz). -80@1MHz -120@3MHz. -110@1MHz. -110@1MHz. -110@1MHz. < 200µs. < 200µs. < 200µs. < 200µs. Number of channels Channel spacing. Data rate. Locking time. For the noise consideration, the integer-N type has an unavoidable disadvantage that the frequency multiplication (by M) raises the phase noise level by 20log(M) dB. In order to improve the phase noise, “Fractional-N” type frequency synthesizer was. -3-.

(19) Chapter 1 Introduction. introduced. The first work adopts a complete fractional-N frequency synthesizer, including third order sigma-delta modulator for high degree noise shaping. This architecture is used to allow a high reference frequency, fine step size, and low divided ratio to achieve low in-band phase noise. Besides, a capacitor is placed at the common mode node of the VCO to provide AC ground on this node. Therefore the phase noise of output signal is much lower. On the other hand, the power issue is also an important consideration. The frequency divider adopts the fully integrated multi-modulus type which is composed by seven stages-cascaded dual modulus asynchronous divide-by-2/3 circuits [5]. Hence, no power hunger preamplifier or buffer is needed to drive the divider. It is easy to design and integration compared with programmable pulse-swallow counter or phase-switching circuit [6-7]. Today there are many works focusing on fractional-N synthesizer, especially on sigma-delta modulation type. The in-band noise performance (such as spurious tone and phase noise) has been improved by adding sigma-delta modulator or other noise shaping circuits. Table 1-2 list this work compared with others. Although the fractional-N type has better performance than the integer-N type, it is more complicated and more difficult to design. Furthermore, in order to improve the low phase noise, the VCO tuning range must be designed in smaller range for lower sensibility. Therefore, the multi-bits frequency bank circuits are used in this design. Based on above reason, we realize two 2.4-GHz integer-N frequency synthesizers; one is for wide tuning range purpose and the other is for low power and low phase noise purpose. The wide tuning range synthesizer is suited for the concurrent dual-band transceiver front-end [10]. Only one synthesizer is required in. -4-.

(20) Chapter 1 Introduction. this topology. Otherwise, the wide-band means the much sensitive to phase noise performance. In order to reduce phase noise and spurious tones, we re-design the VCO part of synthesizer. Table 1-3 list these two 2.4-GHz integer-N frequency synthesizers compared with senior’s works. It shows that the power consumption is greatly reduced and noise performance is still better than senior’s works.. Table 1-2 Fractional-N frequency synthesizer: comparison of recent papers Sigma delta fractional-N synthesizer. JSSC Sep. 2004 [8]. JSSC Mar. 2005 [9]. Technology. CMOS 0.18µm. CMOS 0.18µm. SiGe BiCMOS 0.5µm. Architecture. 3-rd △-∑ fractional-N synthesizer. 3-rd △-∑ fractional-N synthesizer. 3-rd △-∑ fractional-N synthesizer. 1.15 x 1.0 mm2. 1.9 x 1.8 mm2. 2.3 x 1.4 mm2. 1.8V. 1.8V. 2.75V. 2.4GHz. 2.1GHz. 2.4GHz. 16MHz. 35MHz. 40MHz. 125kHz. 35Hz. 468.75kHz. 100kHz. 700kHz. 100kHz. Phase noise. -118.4dBc/Hz @1MHz. -112dBc/Hz @1MHz. -120dBc/Hz @1MHz. Spur tones. -56.5dBc @3.125MHz. -60dBc. -50dBc. Settling time. 30µs. 7µs. 30µs. Total power consumption. 22.9mW. 28mW. 99mW. Performance. Chip area Voltage Center frequency Reference frequency Output frequency resolution 3dB closed loop BW. -5-.

(21) Chapter 1 Introduction. Table 1-3 Integer-N frequency synthesizer: comparison of senior’s works Wide tuning range synthesizer [10]. Low power and low phase noise synthesizer. Thesis 2004 [11]. Thesis 2003 [12]. Technology. CMOS 0.18µm. CMOS 0.18µm. CMOS 0.25µm. CMOS 0.25µm. Architecture. Integer-N (11 stages of %2/3). Integer-N (11 stages of %2/3). Integer-N (11 stages of %2/3). Integer-N (11 stages of %2/3). 1.5 x 1.1 mm2. 1.45 x 0.9 mm2. 1.4 x 0.95 mm2. 1.25 x 0.96 mm2. transistor coupling. transistor coupling. transistor coupling. Poly-phase. Voltage. 1.8V. 1.8V. 2.5V. 2.5V. Reference frequency. 1MHz. 1MHz. 1MHz. 1MHz. 2.123 ~ 2.786. 2.371 ~ 2.678. 2.38 ~ 2.52 (for one bank condition). 2.35 ~ 2.53 (for one bank condition). / 27.6%. / 12.8%. / 5.7%. / 7.5%. -102 @1MHz. -88.4 @1MHz. Performance. Chip area Quadrature VCO types. Tuning range (GHz) /% Phase noise (dBc/Hz). -108.8 @1MHz -114.0 @1MHz -119.7 @3MHz -120.5 @3MHz -26.15dBc @1MHz. -41.5dBc @1MHz. ~ -40dBc @1MHz. -14dBc @1MHz. Settling time. 40µs. 90µs. 130µs. 25µs. Total power consumption. 38.4mW. 28.3mW. 87.5mW. 58.6mW. Spurious tone. Recently, there are still many works focusing on integer-N type synthesizer because the system requirement is not stringent in the short-distance communication systems such as Bluetooth, ZigBee, WLAN, and etc. Table 1-4 list these two synthesizers compared with recent papers. We can see that the power consumption and phase noise of these two synthesizers is better than most of recent papers.. -6-.

(22) Chapter 1 Introduction. Table 1-4 Integer-N frequency synthesizer: comparison of recent papers Wide tuning range synthesizer [10]. Low power and low phase noise synthesizer. JSSC Nov. 2004 [7]. JSSC Mar. 2004 [13]. JSSC Jul. 2003 [1]. RFIC 2001 [5]. Technology. CMOS 0.18µm. CMOS 0.18µm. CMOS 0.18µm. CMOS 0.35µm. CMOS 0.18µm. CMOS 0.25µm. Architecture. Integer-N. Integer-N. Integer-N. FractionalN. Integer-N. ∑-∆ fractionalN. Voltage. 1.8V. 1.8V. 1V. 3.3V. 1.8V. 2.5V. Reference frequency. 1MHz. 1MHz. 11MHz. 256MHz. 500kHz. 13MHz. 2.123 ~ 2.786. 2.371 ~ 2.678. 5.45 ~ 5.65. 2.4 ~ 2.5. 2.26 ~ 2.66. 2.24 ~ 2.50. / 27.6%. / 12.8%. / 3.6%. / 4.2%. / 16.7%. / 10.8%. -108.8 @1MHz -119.7 @3MHz. -114.0 @1MHz -120.5 @3MHz. -111 @1MHz. -97 @1MHz. -125 @3MHz. -133 @3MHz. -26.15dBc @1MHz. -41.5dBc @1MHz. -80dBc @11MHz. -55dBc @62.5kHz. -30dBc @500kHz. -68dBc @13MHz. 40µs. 90µs. 51µs. -. 120µs. -. 38.4mW. 28.3mW. 27.5mW. 49.5mW. 15mW. 55mW. Performance. Tuning range (GHz) / %. Phase noise (dBc/Hz). Spurious tone Settling time Power. Voltage-Controlled Oscillator (VCO) plays an important role in communication systems because the phase noise of the VCO determines the out-of-band noise of the frequency synthesizer. In recently high-frequency operation VCO designs, high power consumption is always an unavoidable limitation, which can be obviously observed in [15-19, 21-24]. The design of VCO becomes even more challenging in RF applications, where stringent requirements of phase noise and power consumption remain as the toughest tasks that RFIC engineers have to deal with. The local oscillator circuits used in radio frequency (RF) systems such as wireless (local area -7-.

(23) Chapter 1 Introduction. networks) LANs and Bluetooth system must have sufficient tuning ranges and good phase noise characteristics. In order to extend the tuning range of VCO, enlarge the varactor gain must be used. We choose the suitable p-n junction varactor for large varactor gain. Hence, we implement a 5.2-GHz low power, low cost, and wide tuning range voltage-controlled oscillator with 0.35-µm SiGe BiCMOS process. Table 1-5 lists this work compared with others. In addition, fully integrated voltage-controlled oscillators (VCOs) are important building blocks for implementation of a single radio-frequency chip in today’s communication systems. In low-IF or direct conversion transceivers, quadrature signals are required for base-band (de)modulation. It is important to offer quadrature generator circuits as minimal power consumption. However, the local oscillator circuits must have sufficient lower power consumption and better phase noise characteristics. Traditional quadrature VCO used additional transistors coupling between two core circuits, so the 1/f come from coupling transistors results in worse phase noise. The new quadrature VCO architecture is presented in [21]. The back-gate (body) node of transistor is used for coupling circuit. The triple-well technique makes this idea practicable. Hence, we also implement a 2.4-GHz low power, low phase noise back-gate quadrature VCO with 0.18-µm triple-well CMOS process. Table 1-6 lists this work compared with others.. -8-.

(24) Chapter 1 Introduction. Table 1-5 Low power and wide tuning-range SiGe VCO: comparison of recent papers. Performance. [14] APMC, 2004 (This work) 0.35-µm SiGe BiCMOS [15] MTT, 2001 0.25-µm CMOS [16] MTT-S, 2002 0.24-µm CMOS [17] RFIC, 2003 0.4-µm SiGe BiCMOS [18] MWCL Jul. 2003 0.18-µm CMOS [19] MWCL May 2005 0.25-µm CMOS [20] Thesis, 2002 0.25-µm CMOS [12] Thesis, 2003 0.25-µm CMOS. Center freq. (GHz). Phase noise (dBc/Hz). Tuning range / %. Core circuit power (mW). Vdd (V). 185.38 @100kHz. -96.1 @100kHz 5.35. -114.1 @1MHz. 1120MHz / 21.5%. FOM. 3.3. 3.3. 183.38 @1MHz 184.84 @3MHz. -125.0 @3MHz 5.35. 340MHz / 6.4%. -93 @100kHz. 7. 1.5. 183.12 @100kHz. 5.8. 810MHz / 14.0%. -112 @1MHz. 5. 2.5. 180.28 @1MHz. 5. 870MHz / 17.4%. -116 @1MHz. 7.5. 2.5. 179.83 @1MHz. 5.8. 166MHz / 2.9%. -110 @1MHz. 8.1. 1.8. 176.2 @1MHz. 5. 980MHz / 20.3%. -114.6 @1MHz. 7.3. 2.5. 179.9 @1MHz. 5.4. 260MHz / 4.8%. -102 @1MHz. 17.5. 2.5. 164 @1MHz. 5.68. 670MHz / 11.8%. -100 @1MHz. 3. 1.5. 170 @1MHz. -9-.

(25) Chapter 1 Introduction. Table 1-6 Low phase noise quadrature VCO with back-gate coupling: comparison of recent papers. Performance. Center freq. (GHz). Tuning range (GHz) / %. Phase noise (dBc/Hz) -99.9 @100kHz -120.2 @600kHz -124.3 @1MHz -133.9 @3MHz. Core circuit power. Vdd (V). FOM. 9mW. 1.8. -176.8 @100kHz -181.5 @600kHz -181.2 @1MHz -181.3 @3MHz. This work 0.18µm CMOS. 2.1. 2.067 ~2.232 / 7.9%. [21] JSSC Jun. 2004 0.18µm CMOS. 1.1. 1.047 ~1.39 / 32.76%. -120 @1MHz. 5.4mW. 1.8. 173.5 @1MHz. [22] JSSC Jul. 2001 0.25µm CMOS. 1.8. 1.71 ~1.99 / 15.56%. -143 @3MHz. 20mW. 2.5. 185.5 @3MHz. 6.3. 6.3 ~6.6 / 4.76%. -106 @1MHz. 6.8mW. 1.8. 176.7 @1MHz. 1.8. 1.14 ~2.46 / 73%. -126.5 1MHz. 4.8mW. 1.5. 184.8 @1MHz. [23] JSSC Jun. 2003 0.18µm SiGe BiCMOS [24] JSSC Apr. 2005 0.18µm CMOS. - 10 -.

(26) Chapter 1 Introduction. 1.2 Thesis organization This thesis constructs a fully integrated 2.4-GHz sigma-delta fractional-N frequency synthesizer, two fully integrated 2.4-GHz integer-N frequency synthesizers, and two voltage-controlled oscillators. Chapter 2 introduces the fully integrated 2.4-GHz sigma-delta fractional-N frequency synthesizer and presents the simulation results of each building block and measurement results. Chapter 3 introduces two 2.4-GHz integer-N frequency synthesizers (one is for wide tuning range purpose and the other is for low power and low phase noise purpose) and presents the simulation results of each building block and measurement results. Chapter 4 introduces two voltage-controlled oscillators (one is for wide tuning range purpose and the other is for low phase-noise purpose) and presents the simulation results and measurement results. Finally, we discuss our measurement results, self-criticisms of the shortcomings in specifications, and future prospects in Chapter5.. - 11 -.

(27) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer 2.1 Architectures The demand for high-speed wireless data communications increases dramatically in recent years. By the rapid development and large demand of wireless communication, a fully integration monolithic transceivers are the most significant considerations for communication application. Since we now have a high-quality CMOS integrated VCO and a high-speed prescaler, it is possible to realize the ultimate goal of this research, i.e. a complete PLL LO synthesizer for a mobile communication system, integrated in a standard CMOS process without any external components, trimming or extra processing steps[25]. For the noise consideration, the integer-N type has an unavoidable disadvantage that the frequency multiplication (by M) raises the phase noise level by 20 log(M ) dB. In order to improve the phase noise,. “Fractional-N” type frequency synthesizer was introduced. According to its name, this type makes the output frequency fVCO be fractional times to the reference frequency f ref and therefore decline the phase noise. A fractional-N synthesizer allows the PLL. to operate with a high reference frequency and meanwhile achieve a fine step size by constantly sweeping the loop division ratio between integral numbers, thus the - 12 -.

(28) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. average division ratio is a fractional number. At this chapter, we choose the Fractional-N type synthesizer in this thesis. Fig. 2-1 is the general architecture of the Integer-N and fractional-N type PLLs. The division ratio of frequency divider is integer in the integer-N type. Otherwise, the division ratio of frequency divider is fractional in the fractional-N type.. (a). Reference clock. PFD. Chargepump. Fdiv. Divider Ratio N .... Low-pass filter. Voltage Control Oscillator. Fout. Modulus Control. (b) Fig. 2-1 General architecture of PLL (a) Integer-N type (b) Fractional-N type. 2.2 Design considerations This chip is fabricated in February 2005. This chip provides a fully integrated low power, low phase-noise, fractional-N frequency synthesizer with spurs noise shaping technique. This frequency synthesizer which consists of six functional blocks, which includes voltage controlled oscillator (VCO), third order sigma-delta modulator, fully programmable multi-modulus divider, phase frequency detector (PFD), charge. - 13 -.

(29) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. pump and low pass loop filter (LPF). Besides the reference crystal and LPF, all the functional blocks are all integrated in a single chip. The following sections will introduce them in detail. In general, the design flow of radio frequency synthesizer is showing below: At first, determine and design the circuit architecture. Next simulate the whole circuits briefly by behavior simulation tools (ex. Simulink of Matlab). Then simulate each block in detail by transistor level simulation tools (ex. Eldo RF, Hspice, ADS, and etc.). After circuit pre-simulation, try to layout our circuit by layout tool (ex. Laker, Virtuoso, and etc.). Then use parasitic extraction tool (ex. Calibre xRC) for parasitic extraction (PEX). Finally simulate our circuits with parasitic by transistor level simulation tools. It also called post-simulation. There are three PEX levels we usually use: PEX-C (only including lumped capacitance), PEX-RC (including distributed resistance and intrinsic capacitance), and PEX-RCC (including distributed resistance and all parasitic capacitance). PEX-RCC is most accurate but it takes most time for post-simulation. Usually, simulation time with PEX-RCC is seven times than one with PEX-C. So we use PEX-C for normal circuits post-simulation and PEX-RCC for particular circuits post-simulation.. 2.2.1 Voltage-controlled oscillator Voltage-Controlled Oscillator (VCO) plays an important role in communication systems because the phase noise of the VCO determines the out-of-band noise of the frequency synthesizer. An oscillator can generate various frequencies for up/down conversion in communication transceivers. In order not to distort the received signals, the excellent noise performance of VCO is required. The design of VCO becomes. - 14 -.

(30) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. even more challenging in RF applications, where stringent requirements of phase noise and power consumption remain as the toughest tasks that RFIC engineers have to deal with. There are two kinds of CMOS RFIC oscillators in common use: One is LC-tank oscillator and the other is Resonatorless oscillator. The later has not been popular in RF design. This is because they not only exhibit an open-loop Q close to unity but contain many noisy active and passive devices in the signal path. For example, in a three-stage differential ring oscillator, the open-loop Q is approximately equal to 1.3 [26], and nine transistors (including the tail current sources) and six load resistors add noise to the carrier. Hence, we adopt the LC-tank architecture. An LC-tank oscillator is a feedback network with an LC-tank as the feedback circuit [27], as showing in Fig. 2-2. In this oscillator model, a noiseless load resistor Rp is present, so we want to provide energy replenished by a transconductor gm. The idea is that an active network generates impedance equal to -Rp so that this feedback system allow steady oscillation [25]. The oscillator frequency and gm value are: gm = 1 f0 =. Rp. 1 2 ⋅π ⋅ L ⋅ C. Fig. 2-2 Behavioral model of an ideal LC oscillator. - 15 -. (2-1). (2-2).

(31) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. Fig. 2-3 is conventional CMOS LC-tank VCO architecture. It contains an LC-Resonator with negative-Gm cross-coupled pairs of MOS transistors as active part. The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors (M1, M2, M3, M4) to enhance negative conductance, besides, only one inductor is paralleled with varactors to build the LC-resonator, instead of two inductors paralleled to signal ground. Such architecture can save large chip area. The complementary architecture mentioned above also provides several excellences over conventional structure only adopt NMOS or PMOS to be -Gm cell.. Fig. 2-3 Conventional CMOS LC-tank VCO architecture For low power consideration, the bias voltage of current source should be chosen carefully. The Vgs-Vt and the gm of MOS in cross-coupled pair must be chosen correctly in order to achieve a good compromise between power consumption, phase noise. and. tuning. range.. A. low. value. of. Vgs-Vt. gives. a. good. transconductance-to-current ratio and hence low power consumption, but results in large transistor and small tuning range. From [25], the required negative transconductance GM of MOS in negative transconductance cell must then be at least equal to. - 16 -.

(32) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. GM =. Reff. (ω0 L ). (2-3). 2. Reff means the effective resistance of the LC tank in the equation above. The safety factor in the transconductance value must be large enough to ensure proper start-up of the oscillator, and is chosen to be 2.5. In order words, gm value equals to 2.5 times of GM. The total current consumption is. I = 2 ⋅ IM1 = 2 ⋅. g m , M 1 ⋅ (Vgs − Vt ) M 1. (2-4). 2. The PMOS transistors are approximately three times larger than the NMOS transistors. Assume the oscillation amplitude is VA. The expected phase noise at ∆f kHz offset then equals to. L {∆f kHz} =. kT ⋅ Reff ⋅ (1 + A) ⋅ ( VA2 2. ω0 2 ) ω. (2-5). The parameter “A” is defined to be the negative transconductance cell noise contribution factor and usually no less than 1. Through the equations above, the bias voltage can be considered and tradeoff between low-power and low phase-noise is also taken. A widely used figure of merit (FOM) [28] to compare VCO for both phase noise and power consumption is defined as: ⎡ kT FOM = 10 ⋅ log ⎢ ⎢ Psup ⎣. 2 ⎛ f0 ⎞ ⎤ ⎥−S f ⋅⎜ ⎜ f ⎟⎟ ⎥ φ ( off ⎝ off ⎠ ⎦. Where Psup is the power consumed by the VCO, f 0 is the center frequency,. f off is the frequency offset from the center,. - 17 -. ). (2-6).

(33) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. and Sφ ( f off ) is the phase noise at a frequency f off from the center. Based on the above consideration, the circuit structure based on the LC-tank oscillator is used to implement this integrated VCO, as showing in Fig. 2-4. Besides, the CMOS is entering an era of Deep-Sub-Micron (DSM). The process variation causes serious problems and more challenge for circuit designers. The tunable range must be designed in wider range but the gain of VCO (Kvco) should keep in smaller value. In order to make sure that oscillation frequency can cover Wireless LAN and Bluetooth system requirements with no effect upon frequency variation, 2-bits frequency bank circuits are used in this design. Therefore, the overall frequency range is widened to compensate for frequency variation but the Kvco can still remain in small value for smaller sensitivity and lower phase noise. There are two control bits and enables us to set the oscillator under 4 operating conditions: 00, 01, 10, and 11. Different control bit is connected to different amount of parallel capacitors; higher bit is connected to a larger capacitance. When a control bit of capacitor bank is at high level, the capacitor is enabled and the capacitance of LC-tank is increased. In Fig. 2-4, the capacitor bank architecture adopts a MOS as a varactor. When a control bit of capacitor bank is at low level, the MOS varactor has small capacitance. Otherwise, when a control bit is at high level, the MOS varactor has large capacitance. It can prevent not start-up oscillation while some damage of switch happened. Fortunately, there are new RF models released from TSMC standard model library. The symmetric inductor is able used to enhance the quality factor of LC-tank. The spiral inductor being used is shown with its layout (Fig. 2-5(a)) and equivalent lump circuit model (Fig. 2-5(b)) with radius=60µm, width=15µm, number of turns=3, and spacing=2µm. The total inductance is about 2.2nH. Use the MOS varactor. - 18 -.

(34) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. (Blanch=25 and Group=4, as showing in Fig. 2-6). So the oscillation frequency of this VCO can oscillate at 2.4-GHz. After the trade off between low power consumption and low phase noise, the optimized bias current [25] is calculated. Each transistor in core circuit has the optimized bias condition for low power consumption. Based on this bias current, the expected phase noise at 1MHz offset can be figured out. Through the equations (2-3, 2-4), the bias voltage can be considered and tradeoff between low-power and low phase-noise is also taken.. (a). (b) Fig. 2-4 Schematic of VCO (a) core circuit part (b) buffer stage. - 19 -.

(35) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. (a) (b) Fig. 2-5 Spiral inductor in this synthesizer (a)layout (b)equivalent circuit model In Fig. 2-4, a capacitor Ctail is placed at the common mode node of the VCO. For symmetry the capacitance is distributed over both sides and connected to the power supply. Adding the capacitance provides AC ground on the common mode node. As a result, the spectrum is much cleaner, which confirms that all 1/f noise comes from the bias current source.. (a) (b) Fig. 2-6 MOS varactor in this synthesizer (a)layout (b)equivalent circuit model After Eldo RF post-simulation, it shows that the oscillator is tunable between 2.347 and 2.561-GHz (214-MHz tuning range) at bank 10. Fig. 2-7 shows the tuning curve of VCO for bank 00, 10 and 11. The corner case of tuning curve for bank 10 is shown in Fig. 2-8. The frequency variation of corner case is quite distinct. We use the capacitor to compensate this variation, as showing Fig. 2-9. The output swing of VCO is shown in Fig. 2-10.. - 20 -.

(36) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. 2800. Oscillation Frequency (MHz). 2700. Oscillation Frequency (Post-Simulation, PEX-C). 2600. 2500. 2400. Bank 00 Bank 10 Bank 11. 2300. 2200 0.0. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. 1.4. 1.6. 1.8. 2.0. Control Voltage (V). Fig. 2-7 Tuning curve of VCO (corner case: TT; Bank condition: 00 10 11) 2700. Oscillation Frequency (MHz). Oscillation Frequency (Post-Simulation, PEX-C) 2600. 2500. 2400. 2300. TT corner FF corner SS corner. 2200 0.0. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. 1.4. 1.6. 1.8. 2.0. Control Voltage (V). Fig. 2-8 Tuning curve of VCO (corner case: TT, FF, SS; Bank condition: 10) 2650. Oscillation Frequency (MHz). 2600. Oscillation Frequency (Post-Simulation, PEX-C). 2550. 2500. 2450. 2400 TT corner and Bank 10 FF corner and Bank 11 SS corner and Bank 00. 2350. 2300 0.0. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. 1.4. 1.6. 1.8. 2.0. Control Voltage (V). Fig. 2-9 Tuning curve of VCO (corner case & Bank condition : TT&10, FF&11, SS&00). - 21 -.

(37) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. Fig. 2-10 Output swing of VCO (corner case: TT, Bank condition: 10) The most critical part in the design of a low-phase noise VCO is the inductor of the resonance LC-tank. The phase noise is -118.0dBc/Hz at 1-MHz offset, and -129.0dBc/Hz at 3-MHz offset at 2.45-GHz, as showing in Fig. 2-11. The power consumption of two quadrature VCO cores is 4.6mW. The overall power consumption is 10.7mW with buffer output stages.. Phase Noise (Post-Simulation, PEX-C). Phase Noise (dBc/Hz). -90.0. -100.0. -110.0. -120.0 TT corner & Bank 10 FF corner & Bank 11 SS corner & Bank 00 -130.0 0.1. 1. Offset Frequency (MHz). Fig. 2-11 Phase noise of VCO (corner case & Bank condition : TT&10, FF&11, SS&00). - 22 -.

(38) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. 2.2.2 Sigma-delta modulator The basic idea behind fractional-N synthesis is division by fractional ratios, instead of only integer ratios. To accomplish fractional division, the same frequency divider as in an integer-N frequency synthesizer is employed, but the division is controlled differently. In the Fig. 2-12 the division modulus of the frequency divider is steered by the carry output of a simple digital accumulator of k-bit width [29]. To realize a fractional division ratio N + n , with n ∈ R[0,1] , a digital input K = n ⋅ 2k is applied to the accumulator. A carry output is produced every K cycles of the reference frequency fref, which is also the sampling frequency of the digital accumulator. This means that the frequency divider divides 2k − K times by N and K times by N+1, resulting in a division ratio Nfrac, given by Eq. (2-1).. N frac =. ( N ) × ( 2k − K ) + ( N + 1) × ( K ) 2. k. =N+. K = N +n 2k. Fig. 2-12 General fractional-N frequency synthesizer. - 23 -. (2-7).

(39) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. Eq. (2-7) states that for a given reference frequency, it is possible to make the frequency resolution arbitrary fine, by choosing the width of the accumulator sufficiently large. For example, in Bluetooth system the channel spacing of 1-MHz can be synthesized using a fref of 16-MHz, by realizing an accumulator width k of more than 4 bits. However, the overflow signal is periodic under this architecture. The spurious tone of frequency synthesizer is more terrible than integer-N architecture. This is not results we expect. In order to overcome this problem, we replace this part with a sigma-delta modulator, as showing in Fig. 2-13. The sigma-delta modulator consists of integration, quantization, and differentiation. After sigma-delta modulator, the signal power doesn’t change but quantization noise power integrates into high frequency (Fig. 2-14). The spurious problem due to the periodic overflow signal is greatly reduced.. Fig. 2-13 Fractional-N frequency synthesizer with sigma-delta modulator. - 24 -.

(40) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. 1 (1 − Z −1 ). (1 − Z ) −1. Fig. 2-14 Noise shaping of a sigma-delta modulator The relation between output and input of sigma-delta modulator is: ⎧ X+q a Y =⎨ -1 ⎩X+(1-Z )q a. (w/o Σ − ∆ modulator) (w/i Σ − ∆ modulator). (2-8). Based on above question, we can realize the schematic of sigma-delta modulator. Next we will introduce two kinds of sigma-delta modulator: one is first order SDM and the other is third order SDM. Finally we have a comparison with these two architectures.. ♦. First order sigma-delta modulator: In this architecture (Fig. 2-15), the transfer function is the same as the. accumulator architecture (Fig. 2-16). The transfer function is:. N [ Z ] = . f [ Z ] + (1 − z −1 ) × qa [ Z ] It means that the quantization noise qa transfers to qe [ Z ] = (1 − z −1 ) × qa [ Z ] .. - 25 -. (2-9).

(41) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. So the transfer function of quantization noise is: H noise ( f ) = 1 − z −1. ⎛ j 2π f H noise ( f ) = 1 − exp ⎜ − ⎜ f ref ⎝ ⎛ j 2π f H noise ( f ) = 1 − cos ⎜ ⎜ f ⎝ ref. ⎞ ⎟⎟ ⎠. ⎞ ⎛ j 2π f ⎟⎟ − j ⋅ sin ⎜⎜ ⎠ ⎝ f ref. ⎛π f H noise ( f ) = 2 ⋅ sin ⎜ ⎜ f ⎝ ref. ⎞ ⎟⎟ ⎠. ⎞ ⎟⎟ ⎠. (2-10). overflow .f[Z]. N[Z]. X. X+Y. clock. Y Z-1 Fig. 2-15 First order sigma-delta modulator. Fig. 2-16 Transfer function of first order sigma-delta modulator Assume there is the k-bit accumulator with input signal K, the ideal output frequency of prescaler is:. f div =. f vco f vco = N +.f N + K 2k. - 26 -. (2-11).

(42) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. But real output frequency of prescaler is:. f div ,r (t ) =. f vco f vco f vco = = NT + qe ( t ) N + ⎡⎣. f + qe ( t ) ⎤⎦ N + k + q t e( ) M 2 k NT = N + M 2. (2-12). To normalize the frequency error term: f vco f − fe ( t ) N + qe ( t ) q (t ) 1 = 1− T = 1− ≅ e + f ( t ) = div f vco q (t ) f div NT 1+ e NT NT. (2-13). The definition of phase error is:. θ e ( t ) 2π × ∫ + f ( t )dt = 2π ×. f div × qe ( t )dt NT ∫. (2-14). Differential both sides at the same time, we can get:. θ e' ( t ) = 2π ×. f div × qe ( t ) NT. (2-15). The Power spectrum density (PFD) of phase error is:. 1 s. θ e ( t ) = ∫ θ e' ( t ) dt ⇒ θ e ( f ) = × θ e' ( f ) ⇒ Sθ. e. ( f ) = ⎛⎜. 2. 1⎞ ⎟ × Sθe' ( f ) ⎝s⎠. (2-16). So, 2. ⎛ 2π × f div ⎞ Sθe ( f ) = ×⎜ ⎟ × Sqe ( f ) 2 ( 2π f ) ⎝ NT ⎠ 1. 2. ⎛ f ⎞ Sθe ( f ) = ⎜ div ⎟ × Sqe ( f ) ⎝ f × NT ⎠. Assume the ideal PFD of quantization noise is: S qa ( f ) =. - 27 -. (2-17). 1 12 ⋅ f ref.

(43) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. So, the PFD of phase error is: 2 ⎛ f div ⎞ ⎧⎪ 1 Sθe ( f ) = ⎜ ⎟ ×⎨ ⎝ f × NT ⎠ ⎩⎪12 ⋅ f ref. ⎡ ⎛π f ⋅ ⎢ 2 ⋅ sin ⎜ ⎜ ⎝ f ref ⎣⎢. As close to center frequency, Sθe ( f ) . ⎞⎤ ⎟⎟ ⎥ ⎠ ⎦⎥. 2. ⎫ ⎛π f f ref ⎪ sin 2 ⎜ ⎬= 2 ⎜ 3 ⋅ ( NT ⋅ f ) ⎝ f ref ⎭⎪. f ref 3 ⋅ ( NT ⋅ f ). 2. ⎛π f ⋅⎜ ⎜ ⎝ f ref. ⎞ ⎟⎟ ⎠. (2-18). 2. ⎞ π2 = ⎟⎟ 2 ⎠ 3 ⋅ NT ⋅ f ref. The in-band transfer function is flat (Fig. 2-17 and Fig. 2-18), so it can’t suppress the spurious effectively.. Fig. 2-17 Influence of first order sigma-delta modulator on signal power. Fig. 2-18 Influence of first order sigma-delta modulator on in-band signal ♦. Third order sigma-delta modulator: In order to transfer more quantization noise to high frequency offset, we adopt. the third stage accumulators, as showing in Fig. 2-19. The transfer function is: (Fig. 2-20). - 28 -.

(44) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. N [ Z ] = . f [ Z ] + (1 − z −1 )3 × qa [ Z ]. (2-19) −1 3. It means that quantization noise transfers to qe [ Z ] = (1 − z ) × qa [ Z ] 。 Hence the transfer function of quantization noise is: H noise ( f ) = (1 − z −1 ). 3. ⎛ j 2π f H noise ( f ) = 1 − exp ⎜ − ⎜ f ref ⎝ ⎛ j 2π f H noise ( f ) = 1 − cos ⎜ ⎜ f ⎝ ref. ⎞ ⎟⎟ ⎠. 3. ⎞ ⎛ j 2π f ⎟⎟ − j ⋅ sin ⎜⎜ ⎠ ⎝ f ref. ⎛π f H noise ( f ) = 2 ⋅ sin ⎜ ⎜ f ⎝ ref. ⎞ ⎟⎟ ⎠. ⎞ ⎟⎟ ⎠. 3. 3. (2-20). Fig. 2-19 Third order sigma-delta modulator. Fig. 2-20 Transfer function of third order sigma-delta modulator Assume the ideal PFD of quantization noise is: S qa ( f ) =. - 29 -. 1 12 ⋅ f ref.

(45) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. So, the PFD of phase error is: 2 ⎛ f div ⎞ ⎧⎪ 1 Sθe ( f ) = ⎜ ⎟ ×⎨ ⎝ f × NT ⎠ ⎩⎪12 ⋅ f ref. ⎡ ⎛π f ⋅ ⎢ 2 ⋅ sin ⎜ ⎜ ⎢⎣ ⎝ f ref. ⎞⎤ ⎟⎟ ⎥ ⎠ ⎥⎦. 6. ⎫ ⎛π f 16 ⋅ f ref ⎪ sin 6 ⎜ ⎬= 2 ⎜ 3 ⋅ ( NT ⋅ f ) ⎝ f ref ⎭⎪. ⎞ ⎟⎟ ⎠. (2-21). As close to center frequency,. Sθe ( f ) . 16 ⋅ f ref 3 ⋅ ( NT ⋅ f ). 2. ⎛π f ⋅⎜ ⎜ f ⎝ ref. 6. ⎞ 16 ⋅ π 6 ⋅ f 4 ⎟⎟ = 2 5 ⎠ 3 ⋅ NT ⋅ f ref. The in-band transfer function is proportional to 4th power of offset frequency (Fig. 2-21 and Fig. 2-22), so it can suppress the spurious effectively.. Fig. 2-21 Influence of first order sigma-delta modulator on signal power. Fig. 2-22 Influence of first order sigma-delta modulator on in-band signal Hence, we choose 3rd sigma-delta modulator in this fractional-N synthesizer design. The whole schematic of sigma-delta modulator is showing in Fig. 2-23.. - 30 -.

(46) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. Fig. 2-23 Schematic of sigma-delta modulator in this synthesizer. 2.2.3 Fully programmable multi-modulus frequency divider Fully programmable multi-modulus divider is adopted to achieve both high-speed frequency division and moderate power consumption. Fig. 2-24 is the block diagram of a fully programmable multi-modulus frequency divider [5]. It is composed by 7 cascaded dual modulus asynchronous divide-by-2/3 circuits. This design assures only the first two stages of the divider works at the high frequency. We can set divide modulus N by changing the input level of each program bits (b0, b1, b2…). In this design, our VCO frequency is about 2.4-GHz and divider can be programmed to all integers between 128 and 255, depending on the input bits b0 to b6 to divide the VCO frequency down to 16-MHz of reference frequency. The programmable dividing ratio is: 6. 6. N = 2 + ∑ bn ⋅ 2 = 128 + ∑ bn ⋅ 2n 7. n. n =0. (2-22). n=0. The simple logic of the AND/OR-gates assures the modulus signals of the last. - 31 -.

(47) Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer. stages are produced first and given to the next stage. Thus the delay of the first divider stage is minimized.. Fig. 2-24 Fully programmable multi-modulus frequency divider The common choice of the frequency divider architecture in frequency synthesizer is usually phase-switching circuit or programmable pulse-swallow counter. These. techniques. have. lower. flexibility.. Therefore,. fully. programmable. multi-modulus divider architecture [5] is adopted in this fully integrated integer-N synthesizer circuit, which is simple, easy to implementation. Besides, compared with other divider architecture, more important point is the delay time of every stage only related to next stage that can reduce divider error. Such architecture only requires change the number of divide-by-2/3 block for different range of divider. No power hunger preamplifier or buffer is needed to drive the divider. Frequency divider is also a critical part besides VCO because of its high operating speed. Just like mentioned above, the first stage of the divider works at the high speed (at 2.4-GHz). The maximum operating frequency is limited by the parasitic capacitance of the feedback of the first stage. In order to reach a maximum. - 32 -.