Future works

In the design of frequency synthesizer, there are several directions for future.

First, the spurious tones are still strong and seriously influence the signal performance.

We should re-design the charge pump and loop filter for lower glitches and acceptable settling time. The charging and discharging of charge pump should be more symmetrical while synthesizer is in locking state. Otherwise, we can choose higher order of the loop filter and reducing the loop bandwidth for larger spurious rejecting ability. Second, the power consumption should be reduced for lower power applications. In the first two stages of multi-modulus divider, we adopt the SCL type divider which has lager power consumption but more accuracy. We can choose the TSPC type for much lower power applications. We can also reduce the supply voltage to increase its competitiveness. Third, although the sigma-delta fractional-N type of synthesizer is implemented, the performance of synthesizer which we design, especially on phase noise performance during loop, is locked is not much better than

the commercial products for communication applications. We can add the band-gap reference for each bias voltage in our circuits. The band-gap reference voltage has lower noise component than voltage from off-chip supply voltage. It not only improves our circuit performance but also reduces the pads requirement. Besides, the frequency synthesizer with spurs compensation technique is presented in [8]. We can realize the spurs free frequency synthesizer by adding digital-to-analog circuit, as showing in Fig. 5-1. However, this circuit architecture becomes more complicated to design. This is a challenge to achieve this best architecture in recent works of frequency synthesizer.

Fig. 5-1 Building blocks of sigma-delta fractional-N frequency synthesizer with spurs compensation technique

Reference

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Publication Remarks

International conference papers:

1. Christina F. Jou, Kuo-Hua Cheng, Wei-Cheng Lien, Chun-Hsien Wu, and Chin-Hsien Yen, “A 2.45 GHz / 5.25 GHz Concurrent Dual-Band Receiver Front-End Using 0.18um CMOS,” IEEE Transaction on Microwave Theory and Techniques Mini-Special Issue on: Papers of Asia-Pacific Microwave Conference (APMC 2004), New Delhi, India, December, 15-18, 2004.

2. Christina F. Jou, Kuo-Hua Cheng, and Wei-Cheng Lien, “Design of a Low-Power and Wide Tuning Range SiGe VCO,” IEEE Transaction on Microwave Theory and Techniques Mini-Special Issue on: Papers of Asia-Pacific Microwave Conference (APMC 2004), New Delhi, India, December, 15-18, 2004.