Thesis organization

This thesis constructs a fully integrated 2.4-GHz sigma-delta fractional-N frequency synthesizer, two fully integrated 2.4-GHz integer-N frequency synthesizers, and two voltage-controlled oscillators.

Chapter 2 introduces the fully integrated 2.4-GHz sigma-delta fractional-N frequency synthesizer and presents the simulation results of each building block and measurement results.

Chapter 3 introduces two 2.4-GHz integer-N frequency synthesizers (one is for wide tuning range purpose and the other is for low power and low phase noise purpose) and presents the simulation results of each building block and measurement results.

Chapter 4 introduces two voltage-controlled oscillators (one is for wide tuning range purpose and the other is for low phase-noise purpose) and presents the simulation results and measurement results.

Finally, we discuss our measurement results, self-criticisms of the shortcomings in specifications, and future prospects in Chapter5.

Chapter 2 A 2.4-GHz Low Power, Low Phase-Noise, Sigma-Delta Fractional-N Frequency Synthesizer

2.1 Architectures

The demand for high-speed wireless data communications increases dramatically in recent years. By the rapid development and large demand of wireless communication, a fully integration monolithic transceivers are the most significant considerations for communication application. Since we now have a high-quality CMOS integrated VCO and a high-speed prescaler, it is possible to realize the ultimate goal of this research, i.e. a complete PLL LO synthesizer for a mobile communication system, integrated in a standard CMOS process without any external components, trimming or extra processing steps[25]. For the noise consideration, the integer-N type has an unavoidable disadvantage that the frequency multiplication (by M) raises the phase noise level by 20log(M dB. In order to improve the phase noise, )

“Fractional-N” type frequency synthesizer was introduced. According to its name, this type makes the output frequency f_VCObe fractional times to the reference frequency

fref and therefore decline the phase noise. A fractional-N synthesizer allows the PLL to operate with a high reference frequency and meanwhile achieve a fine step size by constantly sweeping the loop division ratio between integral numbers, thus the

average division ratio is a fractional number. At this chapter, we choose the Fractional-N type synthesizer in this thesis. Fig. 2-1 is the general architecture of the Integer-N and fractional-N type PLLs. The division ratio of frequency divider is integer in the integer-N type. Otherwise, the division ratio of frequency divider is fractional in the fractional-N type.

(a)

Fout

Reference clock

PFD Chargepump Low-pass filter

Voltage Control Oscillator

Divider Ratio N Fdiv

...

Modulus Control

(b)

Fig. 2-1 General architecture of PLL (a) Integer-N type (b) Fractional-N type

2.2 Design considerations

This chip is fabricated in February 2005. This chip provides a fully integrated low power, low phase-noise, fractional-N frequency synthesizer with spurs noise shaping technique. This frequency synthesizer which consists of six functional blocks, which includes voltage controlled oscillator (VCO), third order sigma-delta modulator, fully programmable multi-modulus divider, phase frequency detector (PFD), charge

pump and low pass loop filter (LPF). Besides the reference crystal and LPF, all the functional blocks are all integrated in a single chip. The following sections will introduce them in detail.

In general, the design flow of radio frequency synthesizer is showing below: At first, determine and design the circuit architecture. Next simulate the whole circuits briefly by behavior simulation tools (ex. Simulink of Matlab). Then simulate each block in detail by transistor level simulation tools (ex. Eldo RF, Hspice, ADS, and etc.). After circuit pre-simulation, try to layout our circuit by layout tool (ex. Laker, Virtuoso, and etc.). Then use parasitic extraction tool (ex. Calibre xRC) for parasitic extraction (PEX). Finally simulate our circuits with parasitic by transistor level simulation tools. It also called post-simulation. There are three PEX levels we usually use: PEX-C (only including lumped capacitance), PEX-RC (including distributed resistance and intrinsic capacitance), and PEX-RCC (including distributed resistance and all parasitic capacitance). PEX-RCC is most accurate but it takes most time for post-simulation. Usually, simulation time with PEX-RCC is seven times than one with PEX-C. So we use PEX-C for normal circuits post-simulation and PEX-RCC for particular circuits post-simulation.

2.2.1 Voltage-controlled oscillator

Voltage-Controlled Oscillator (VCO) plays an important role in communication systems because the phase noise of the VCO determines the out-of-band noise of the frequency synthesizer. An oscillator can generate various frequencies for up/down conversion in communication transceivers. In order not to distort the received signals, the excellent noise performance of VCO is required. The design of VCO becomes

even more challenging in RF applications, where stringent requirements of phase noise and power consumption remain as the toughest tasks that RFIC engineers have to deal with.

There are two kinds of CMOS RFIC oscillators in common use: One is LC-tank oscillator and the other is Resonatorless oscillator. The later has not been popular in RF design. This is because they not only exhibit an open-loop Q close to unity but contain many noisy active and passive devices in the signal path. For example, in a three-stage differential ring oscillator, the open-loop Q is approximately equal to 1.3 [26], and nine transistors (including the tail current sources) and six load resistors add noise to the carrier. Hence, we adopt the LC-tank architecture.

An LC-tank oscillator is a feedback network with an LC-tank as the feedback circuit [27], as showing in Fig. 2-2. In this oscillator model, a noiseless load resistor Rp is present, so we want to provide energy replenished by a transconductor gm. The idea is that an active network generates impedance equal to -Rp so that this feedback system allow steady oscillation [25]. The oscillator frequency and gm value are:

m 1

p

g = R (2-1)

0

1 f 2

π L C

= ⋅ ⋅ ⋅ (2-2)

Fig. 2-2 Behavioral model of an ideal LC oscillator

Fig. 2-3 is conventional CMOS LC-tank VCO architecture. It contains an LC-Resonator with negative-Gm cross-coupled pairs of MOS transistors as active part.

The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors (M1, M2, M3, M4) to enhance negative conductance, besides, only one inductor is paralleled with varactors to build the LC-resonator, instead of two inductors paralleled to signal ground. Such architecture can save large chip area. The complementary architecture mentioned above also provides several excellences over conventional structure only adopt NMOS or PMOS to be -Gm cell.

Fig. 2-3 Conventional CMOS LC-tank VCO architecture

For low power consideration, the bias voltage of current source should be chosen carefully. The Vgs-Vt and the gm of MOS in cross-coupled pair must be chosen correctly in order to achieve a good compromise between power consumption, phase noise and tuning range. A low value of Vgs-Vt gives a good transconductance-to-current ratio and hence low power consumption, but results in large transistor and small tuning range. From [25], the required negative transconductance GM of MOS in negative transconductance cell must then be at least equal to

(

0

)

²

Reff means the effective resistance of the LC tank in the equation above. The safety factor in the transconductance value must be large enough to ensure proper start-up of the oscillator, and is chosen to be 2.5. In order words, gm value equals to 2.5 times of GM. The total current consumption is

The PMOS transistors are approximately three times larger than the NMOS transistors. Assume the oscillation amplitude is VA. The expected phase noise at ∆f kHz offset then equals to

{ }

The parameter “A” is defined to be the negative transconductance cell noise contribution factor and usually no less than 1. Through the equations above, the bias voltage can be considered and tradeoff between low-power and low phase-noise is also taken.

A widely used figure of merit (FOM) [28] to compare VCO for both phase noise and power consumption is defined as:

2

( )

foff is the frequency offset from the center,

and S_φ

( )

foff is the phase noise at a frequency f_off from the center.

Based on the above consideration, the circuit structure based on the LC-tank oscillator is used to implement this integrated VCO, as showing in Fig. 2-4.

Besides, the CMOS is entering an era of Deep-Sub-Micron (DSM). The process variation causes serious problems and more challenge for circuit designers. The tunable range must be designed in wider range but the gain of VCO (Kvco) should keep in smaller value. In order to make sure that oscillation frequency can cover Wireless LAN and Bluetooth system requirements with no effect upon frequency variation, 2-bits frequency bank circuits are used in this design. Therefore, the overall frequency range is widened to compensate for frequency variation but the Kvco can still remain in small value for smaller sensitivity and lower phase noise. There are two control bits and enables us to set the oscillator under 4 operating conditions: 00, 01, 10, and 11. Different control bit is connected to different amount of parallel capacitors;

higher bit is connected to a larger capacitance. When a control bit of capacitor bank is at high level, the capacitor is enabled and the capacitance of LC-tank is increased.

In Fig. 2-4, the capacitor bank architecture adopts a MOS as a varactor. When a control bit of capacitor bank is at low level, the MOS varactor has small capacitance.

Otherwise, when a control bit is at high level, the MOS varactor has large capacitance.

It can prevent not start-up oscillation while some damage of switch happened.

Fortunately, there are new RF models released from TSMC standard model library. The symmetric inductor is able used to enhance the quality factor of LC-tank.

The spiral inductor being used is shown with its layout (Fig. 2-5(a)) and equivalent lump circuit model (Fig. 2-5(b)) with radius=60µm, width=15µm, number of turns=3, and spacing=2µm. The total inductance is about 2.2nH. Use the MOS varactor

(Blanch=25 and Group=4, as showing in Fig. 2-6). So the oscillation frequency of this VCO can oscillate at 2.4-GHz.

After the trade off between low power consumption and low phase noise, the optimized bias current [25] is calculated. Each transistor in core circuit has the optimized bias condition for low power consumption. Based on this bias current, the expected phase noise at 1MHz offset can be figured out. Through the equations (2-3, 2-4), the bias voltage can be considered and tradeoff between low-power and low phase-noise is also taken.

(a)

(b)

Fig. 2-4 Schematic of VCO (a) core circuit part (b) buffer stage

(a) (b) Fig. 2-5 Spiral inductor in this synthesizer (a)layout (b)equivalent circuit model

In Fig. 2-4, a capacitor Ctail is placed at the common mode node of the VCO. For symmetry the capacitance is distributed over both sides and connected to the power supply. Adding the capacitance provides AC ground on the common mode node. As a result, the spectrum is much cleaner, which confirms that all 1/f noise comes from the bias current source.

(a) (b) Fig. 2-6 MOS varactor in this synthesizer (a)layout (b)equivalent circuit model

After Eldo RF post-simulation, it shows that the oscillator is tunable between 2.347 and 2.561-GHz (214-MHz tuning range) at bank 10. Fig. 2-7 shows the tuning curve of VCO for bank 00, 10 and 11. The corner case of tuning curve for bank 10 is shown in Fig. 2-8. The frequency variation of corner case is quite distinct. We use the capacitor to compensate this variation, as showing Fig. 2-9. The output swing of VCO is shown in Fig. 2-10.

Oscillation Frequency (corner case: TT; Bank condition: 00 10 11)

Oscillation Frequency (corner case: TT, FF, SS; Bank condition: 10)

Oscillation Frequency

TT corner and Bank 10 FF corner and Bank 11 SS corner and Bank 00

Fig. 2-9 Tuning curve of VCO

(corner case & Bank condition : TT&10, FF&11, SS&00)

Fig. 2-10 Output swing of VCO (corner case: TT, Bank condition: 10)

The most critical part in the design of a low-phase noise VCO is the inductor of the resonance LC-tank. The phase noise is -118.0dBc/Hz at 1-MHz offset, and -129.0dBc/Hz at 3-MHz offset at 2.45-GHz, as showing in Fig. 2-11.

The power consumption of two quadrature VCO cores is 4.6mW. The overall power consumption is 10.7mW with buffer output stages.

Phase Noise (Post-Simulation, PEX-C)

Offset Frequency (MHz)

0.1 1

Phase Noise (dBc/Hz)

-130.0 -120.0 -110.0 -100.0 -90.0

TT corner & Bank 10 FF corner & Bank 11 SS corner & Bank 00

Fig. 2-11 Phase noise of VCO

(corner case & Bank condition : TT&10, FF&11, SS&00)

2.2.2 Sigma-delta modulator

The basic idea behind fractional-N synthesis is division by fractional ratios, instead of only integer ratios. To accomplish fractional division, the same frequency divider as in an integer-N frequency synthesizer is employed, but the division is controlled differently. In the Fig. 2-12 the division modulus of the frequency divider is steered by the carry output of a simple digital accumulator of k-bit width [29]. To realize a fractional division ratioN + n, withn R∈ [0,1], a digital input K = ⋅ is n 2^k applied to the accumulator. A carry output is produced every K cycles of the reference frequency fref, which is also the sampling frequency of the digital accumulator. This means that the frequency divider divides 2^k− times by N and K times by N+1, K resulting in a division ratio Nfrac, given by Eq. (2-1).

( ) (

²

) ⁽

¹

^{) ( )}

2 2

k

frac k k

N K N K K

N × − + + × N N n

= = + = + (2-7)

Fig. 2-12 General fractional-N frequency synthesizer

Eq. (2-7) states that for a given reference frequency, it is possible to make the frequency resolution arbitrary fine, by choosing the width of the accumulator sufficiently large. For example, in Bluetooth system the channel spacing of 1-MHz can be synthesized using a fref of 16-MHz, by realizing an accumulator width k of more than 4 bits.

However, the overflow signal is periodic under this architecture. The spurious tone of frequency synthesizer is more terrible than integer-N architecture. This is not results we expect. In order to overcome this problem, we replace this part with a sigma-delta modulator, as showing in Fig. 2-13. The sigma-delta modulator consists of integration, quantization, and differentiation. After sigma-delta modulator, the signal power doesn’t change but quantization noise power integrates into high frequency (Fig. 2-14). The spurious problem due to the periodic overflow signal is greatly reduced.

Fig. 2-13 Fractional-N frequency synthesizer with sigma-delta modulator

(

^{1 Z−1 −1}

) (

^{1 Z− −1}

)

Fig. 2-14 Noise shaping of a sigma-delta modulator The relation between output and input of sigma-delta modulator is:

a -1

a

X+q (w/o modulator) X+(1-Z )q (w/i modulator)

Y ⎧ Σ − ∆

= ⎨⎩ Σ − ∆ (2-8)

Based on above question, we can realize the schematic of sigma-delta modulator.

Next we will introduce two kinds of sigma-delta modulator: one is first order SDM and the other is third order SDM. Finally we have a comparison with these two architectures.

♦ First order sigma-delta modulator:

In this architecture (Fig. 2-15), the transfer function is the same as the accumulator architecture (Fig. 2-16). The transfer function is:

[ ] . [ ] (1 1) _a[ ]

N Z = f Z + −z⁻ ×q Z (2-9)

It means that the quantization noiseq transfers to_a q Z_e[ ] (1= −z⁻¹)×q Z_a[ ].

So the transfer function of quantization noise is:

Fig. 2-15 First order sigma-delta modulator

Fig. 2-16 Transfer function of first order sigma-delta modulator

Assume there is the k-bit accumulator with input signal K, the ideal output frequency of prescaler is:

.

But real output frequency of prescaler is:

To normalize the frequency error term:

( ) ( ) ( )

The definition of phase error is:

( )

²

( )

^{2 div}

( )

e e

T

t f t dt f q t dt

θ ^ π×

∫

⁺ = π× N ×

∫

^(2-14)

Differential both sides at the same time, we can get:

( ) ( )

The Power spectrum density (PFD) of phase error is:

( )

^'

( ) ( )

^{1 '}

( )

_e

( )

^{1 2 '}

( )

Assume the ideal PFD of quantization noise is:

( )

¹

12

So, the PFD of phase error is:

As close to center frequency,

( )

( )

The in-band transfer function is flat (Fig. 2-17 and Fig. 2-18), so it can’t suppress the spurious effectively.

Fig. 2-17 Influence of first order sigma-delta modulator on signal power

Fig. 2-18 Influence of first order sigma-delta modulator on in-band signal

♦ Third order sigma-delta modulator:

In order to transfer more quantization noise to high frequency offset, we adopt the third stage accumulators, as showing in Fig. 2-19. The transfer function is: (Fig.

2-20)

[ ] . [ ] (1 1 3) _a[ ]

N Z = f Z + −z⁻ ×q Z (2-19)

It means that quantization noise transfers to q Z_e[ ] (1= − z^{−1 3}) ×q Z_a[ ]。

Hence the transfer function of quantization noise is:

( ) (

^{1 1}

)

³

Fig. 2-19 Third order sigma-delta modulator

Fig. 2-20 Transfer function of third order sigma-delta modulator Assume the ideal PFD of quantization noise is:

( )

¹

12

So, the PFD of phase error is:

As close to center frequency,

( ) ( )

The in-band transfer function is proportional to 4^th power of offset frequency (Fig. 2-21 and Fig. 2-22), so it can suppress the spurious effectively.

Fig. 2-21 Influence of first order sigma-delta modulator on signal power

Fig. 2-22 Influence of first order sigma-delta modulator on in-band signal

Hence, we choose 3^rd sigma-delta modulator in this fractional-N synthesizer design. The whole schematic of sigma-delta modulator is showing in Fig. 2-23.

Fig. 2-23 Schematic of sigma-delta modulator in this synthesizer

2.2.3 Fully programmable multi-modulus frequency divider

Fully programmable multi-modulus divider is adopted to achieve both high-speed frequency division and moderate power consumption. Fig. 2-24 is the block diagram of a fully programmable multi-modulus frequency divider [5]. It is composed by 7 cascaded dual modulus asynchronous divide-by-2/3 circuits. This design assures only the first two stages of the divider works at the high frequency. We can set divide modulus N by changing the input level of each program bits (b0, b1, b2…). In this design, our VCO frequency is about 2.4-GHz and divider can be programmed to all integers between 128 and 255, depending on the input bits b0 to b6

to divide the VCO frequency down to 16-MHz of reference frequency. The programmable dividing ratio is:

6 6

7

0 0

2 _n 2ⁿ 128 _n 2ⁿ

n n

N b b

= =

= +

∑

⋅ = +

∑

⋅ ^(2-22)

The simple logic of the AND/OR-gates assures the modulus signals of the last

stages are produced first and given to the next stage. Thus the delay of the first divider stage is minimized.

Fig. 2-24 Fully programmable multi-modulus frequency divider

The common choice of the frequency divider architecture in frequency synthesizer is usually phase-switching circuit or programmable pulse-swallow counter.

These techniques have lower flexibility. Therefore, fully programmable multi-modulus divider architecture [5] is adopted in this fully integrated integer-N synthesizer circuit, which is simple, easy to implementation. Besides, compared with other divider architecture, more important point is the delay time of every stage only related to next stage that can reduce divider error. Such architecture only requires change the number of divide-by-2/3 block for different range of divider. No power hunger preamplifier or buffer is needed to drive the divider.

Frequency divider is also a critical part besides VCO because of its high operating speed. Just like mentioned above, the first stage of the divider works at the high speed (at 2.4-GHz). The maximum operating frequency is limited by the parasitic capacitance of the feedback of the first stage. In order to reach a maximum

operate frequency at 2.5-GHz, the first stages are realized in a differential Source Coupled Logic (SCL) and logic gates are embedded in it (Fig. 2-25). This architecture requires smaller signal swing from VCO outputs [5]. Although true single phase clock (TSPC) flip-flops divider cell architecture has less power consumption, it requires almost full swing signals to complete divided-two function. However, the maximum operating speed is limited by the parasitic capacitance of the feedback of the first stage. The very accurate layout of first stage is necessary to reduce the parasitic components.

The following 5 stages are realized with less power-hungry single ended digital cells, which provide a maximum operating frequency of several hundred MHz to lower the total current consumption.

ck

ck-vbias B B

A

A

B-A- Q

Q-Vdd

Fig. 2-25 Differential source coupled logic (SCL)

The co-simulation result of fully programmable frequency multi-modulus divider and VCO is as shown in Fig. 2-26. The VCO output frequency is set at 2400-MHz and the divide modulus is set at 150, too. We can obviously observe the period of output

divided signal is 62.5ns, this figures out our divider is working regularly.

Fig. 2-26 Output signal of frequency divider simulated with VCO

2.2.4 Phase frequency detector

We choose three state phase frequency detector (PFD) for the design. A conventional three state PFD is widely used in many purposes for its simplicity, wide linear range of ±2π radians. Another significant excellence is it detects both phase and

We choose three state phase frequency detector (PFD) for the design. A conventional three state PFD is widely used in many purposes for its simplicity, wide linear range of ±2π radians. Another significant excellence is it detects both phase and

在文檔中 應用於無線區域網路與藍芽系統之全積體化低功率低相位雜訊整數型及三角積分之分數型頻率合成器 (頁 26-0)