Background and Problems

Over the past few years, the wireless communications industry has experienced rapid and incredible growth, much of which has been driven by the rapidly-growing wireless market such as mobile telecommunications. But not only has the market for mobile telecomm grown; during the last couple of years, all kinds of previously wired connections between home and office appliances have been going wireless as well. The cellular phone has a calendar function that synchronizes automatically with the desktop calendar through a Bluetooth connection; the laptop computer accesses the Internet for multimedia services through a WLAN or emerging WiMAX connection, etc. So, there introduces a growing demand for wireless communication in today’s world.

In wireless communication systems, low cost, low power consumption, and high performance are the critical requirements due to the highly competitive market environment and limitation in battery life. In order to meet a growing demand for wireless communication, it’s desirable to implement radio transceivers monolithically with the help of improving large-scale low-cost integration technology. At present, GaAs, silicon bipolar, and BiCMOS technologies constitute a major section of the RF transceivers market because these technologies provide useful features such as high breakdown voltage and high cutoff frequency, etc. However, they are still expensive and low-density integration technologies so as not to satisfy people’s desire for low cost, small size, high portability, and good performance. Fortunately, as the deep-submicron

CMOS process evolves, CMOS technology has strong advantages of low cost and high density compared to other available technologies. Moreover, CMOS technology has the high potential to achieve a fully-integrated solution for system-on-a-chip (SOC), which realizes the addition of back-end digital function with the RF front-end circuit. So, in order to achieve the ultimate goal of SOC, many efforts have devoted to well design and implement a transceiver in CMOS process, as well as increase the integration level.

In the world of modern wireless communication, phase-locked loop (PLL) based frequency synthesizers have played an important role in RF front-ends. PLL-based frequency synthesizers are used to provide clean, stable, and precise carrier signals for frequency translation in wireless transceivers, as shown in Figure 1.1 which illustrates a generic transceiver architecture. As the wireless standards evolve, it presents an increasing challenge to meet the stringent requirements of low jitter or phase noise, fast settling time, and low power in PLL-based frequency synthesizer designs, which involve a lot of design issues and trade-offs.

Figure 1.1 Block diagram of a generic transceiver architecture

The important system performance specifications for a frequency synthesizer are timing jitter, locking time, spectral purity, power dissipation, and manufacturing cost, etc. Within different PLL-based topologies, a popular low-cost architecture is the charge-pump PLL-based (CPPLL-based) frequency synthesizers, in which an ideal phase-frequency detector (PFD) is incorporated with an ideal charge pump (CP) to provide an infinite dc gain with passive filters, resulting in an unbounded pull-in range and zero static phase error [1]. However, in reality there exist many non-idealities in both PFD and CP or PFD/CP combination, such as dead zone, blind zone, current mismatch/leakage, charge sharing/injection, etc. These non-idealities are all detrimental to the overall performance of frequency synthesizers and should be avoid or alleviated.

Here, the following brief description of how these non-idealities influence the system will give us a preliminary insight into the problems and trade-offs in CPPLL designs.

First, in a CPPLL, one of the critical building blocks is the tri-state PFD due to its frequency-detection capability. A conventional tri-state PFD suffers from the “dead zone” problem, which occurs when the loop is in a lock mode and the output of the following CP don’t change for small phase changes in the input signals at PFD. Any phase error within the dead-zone will disturb the VCO control voltage and directly translate to phase jitter in the PLL output, as shown in Figure 1.2.

Figure 1.2 PLL jitter introduced by the PFD dead zone

Second, in order to eliminate the dead-zone, an added delay is inserted in the reset path to maintain a minimum pulse width when the two input signals are in phase.

However, such a solution presents a limit on its maximum operating frequency and introduces another problem called “blind zone”, where any input transition will be overridden for large phase errors. Any input transition override results in the wrong output polarity (Figure 1.3) and longer frequency acquisition time.

Figure 1.3 The PFD blind zone and its phase characteristic

Third, in addition to the above-mentioned issues, one of the other design issues is the unwanted FM modulation, which causes the reference spurs. Any non-idealities in the PLL itself causes periodic ripples on the VCO control line, which will in turn result in undesired spurs at the upper and lower sideband of the carrier. The dominant spurious-generating block in the PLL is the charge pump, the non-idealities of which mainly are: 1) the mismatch between the CP current sources (both random and due to channel-length modulation); 2) the mismatch between the charge injection and clock feedthrough of the pMOS and nMOS switches in the CP; 3) the mismatch between the arrival times of the input control pulses; 4) the mismatch of the widths of the input control pulses. Charge sharing also exacerbates the ripples [2].