Related Works

Over the past few years, a large amount of literature has been contributed to the study of how to solve these issues and improve the PLL performance. However, there is still a lot of work to be done in the field. In view of this, the focus of our work is on finding better ways to alleviate or even completely ameliorate these issues but except the FM-modulation issue. The following subsections comes the overview of the related works referred in our thesis.

1.2.1 Review on Phase-Frequency Detectors

Figure 1.4 Circuit schematics [6] (a) a pass-transistor DFF PFD, and (b) a latch-based PFD

As stated in the previous section, a conventional tri-state PFD suffers from the dead-zone issue which worsens the PLL output jitter. Roughly, there are two ways to alleviate this problem. One way is to reduce the intrinsic reset time [3], [4], thus shortening the dead-zone. This in turn alleviates the speed and jitter limitations.

Nevertheless, such a method offers only limited improvement on the issue. The other way is to add an additional delay in the reset path for enough pulse width to drive the

following stage [1], [3]. This would be a relatively simple and effective method, which could completely eliminate the dead-zone. Unfortunately, such a way introduces the blind-zone (Figure 1.3). It’s obvious that the blind zone is detrimental to the PLL settling behavior, and will slow down the locking time. In view of this, some extensive studies have been undertaken recently and expected to address both issues together [5]-[8].

Figure 1.5 (a) Timing diagram and (b) Phase-detection characteristic of the latch-based PFD

In Figure 1.4(a) and (b) [6], two techniques for designing PFD have been presented, a pass-transistor-DFF PFD and a latch-based PFD, respectively. A pass-transistor-DFF PFD shows a smaller reset delay, only including one pass-transistor, one inverter, and one NAND gate. As a result, a reduced blind-zone and faster frequency acquisition can be achieved. In Figure 1.4(b), by using pulse latches instead of flip-flops, the latch-based PFD fundamentally changes the dependence on the reset delay. This is illustrated in the timing diagram of Figure 1.5(a).When CKref arrives during the Reset , the edge information propagates to the output as long as CKref is still high (level-sensitive) when the blind-zone duration ends. The PFD no longer loses the edge that arrives during the Reset and doesn’t output wrong polarity. The phase-detection characteristic is shown in Figure 1.5(b). It should note that the input pulse widths should be designed to be slightly smaller than the reset pulse width so that an input that triggers

the Reset would not assert the output after the Reset pulse ends; otherwise, the PFD will fail to lock at zero phase error. This design criterion results in wrong output polarity for Δθ ≥ 2π–δ. Thus, there still exhibits a very small blind-zone, whereas its operating frequency potentially approaches twice that of either the first proposed PFD or the conventional PFD for the same Reset time.

Figure 1.6 A novel precharged PFD in [7]

Figure 1.6 [7] also shows a novel precharged PFD, which employs the same idea as in [6]. Noninverting delay stages are inserted into the commonly used precharged PFD so that it generates effective control signals even when the phase error approaches 2π.

The novel precharged PFD has the same phase-detection characteristic but lower power consumption and higher precision as compared to the latch-based PFD [6]. Similarly, it also has a very small blind-zone, and the maximum operating frequency is dependent on the duty ratio of each input clock. Assume 50% duty ratio, the maximum operating frequency is half that of [6].

A robust tri-state PFD architecture [8] is shown in Figure 1.7(a), which does not

rely on any assumption on the underlying VLSI technology. The proposed PFD is divided two parts: one is the classical tri-state PFD using flip-flops with asynchronous set and reset inputs, and the other is the FZ-detector, which takes over the detection process once inside the blind-zone. The proposed PFD forces a set signal when an input transition occurs inside the blind-zone, thereby avoiding setting the wrong output and enhancing the frequency acquisition capabilities. Compared with the conventional PFD, its operating frequency shows an improvement of about 36%. Figure 1.7(b) shows the corresponding phase-detection characteristic.

(a) (b)

Figure 1.7 (a) The proposed PFD architecture [8]; (b) Its phase-detection characteristic

1.2.2 Review on Dual-Modulus Prescalers

A high-frequency CMOS PLL frequency synthesizer has stringent requirements on dual-modulus prescaler (DMP). High speed, high moduli, and low power dissipation are the challenges in DMP designs. Typically, a DMP usually comprises of a synchronous dual-modulus counter, followed by an asynchronous counter. The critical path delay and the speed of the DFFs in the synchronous counter limit its overall speed, particularly at high divide-by-value. High divide-by-value is, in general, achieved by adding flip-flops

in the asynchronous counter at the cost of additional loading to the synchronous counter which results in degraded performance. Therefore, there is a trade-off between the speed and the divide-by-value.

Conventionally, most high-moduli DMPs usually comprise of a synchronous divide-by-4/5 counter, followed by a chain of toggle flip-flops, which forms an asynchronous counter. The operating speed of DMPs is mainly limited by that of the divide-by-4/5 counter. Unlike the conventional divide-by-4/5 counter [9], a novel topology for a divide-by-3/4 counter using transmission gates (TGs) in the critical path for mode selection is proposed by R. S. Rana [10]. The author has demonstrated that the TG-based divide-by-3/4 counter provides higher speed compared to the conventional divide-by-4/5 counter. However, an alternative divide-by-3/4 counter using NOR gates in the critical path is also presented and taken into account for further comparison by R.

S. Rana [10]. With the help of Hspice simulation, the results show that the NOR-based divide-by-3/4 counter provides higher speed than the TG-based one due to smaller feedback path delay even though the critical path delay is more. For enhancing the speed of the TG-based divide-by-3/4 counter further, the author expects to shorten the D flip-flop (DFF) delay for future improvement.