Thesis Organization

To achieve a low-jitter and fast-locking frequency synthesizer, this thesis presents a new fast frequency acquisition PFD with better phase- and frequency-discriminator characteristics. It also presents a new dual-modulus prescaler for high speed operation.

This thesis is organized into the following chapters. Chapter 2 will give some general design considerations of PLL-based frequency synthesizer as well as basic behavior characteristics of its individual building blocks. A comprehensive and in-depth analysis of the noise behavior and loop stability of frequency synthesizers provides an insight into the design issues and trade-offs. Chapter 3 introduces a novel fast frequency

acquisition PFD with a detailed analysis of its phase- and frequency-discriminator characteristics. With the help of HSPICE and ADS simulation, the results demonstrate its robustness in PLL designs. Chapter 4 introduces a modified high-speed divide-by-3/4 dual-modulus prescaler and provides some simulation results to prove its improvement over the original one published by Rana [10]. Chapter 5 presents the circuit design and implementation of the building blocks of the frequency synthesizer, including voltage-controlled oscillator (VCO), frequency divider, PFD, charge pump and loop filter. Chapter 6 concludes this thesis with a summary and future work.

CHAPTER 2

Basics of Frequency Synthesizers

In a typical RF front-end circuit, the local oscillator is usually embedded in a phase-locked loop (PLL) as a tunable frequency synthesizer to provide clean, stable and more precise carrier signals for frequency up/down-conversion. The frequency synthesizer needs to be tunable in order to address all frequency channels and be fast switching to perform the addressing sufficiently fast. A basic block diagram of a PLL-based frequency synthesizer is shown in Figure 2.1. The loop provides a feedback to keep the output frequency of the synchronized oscillator to be a multiple of the reference frequency, i.e. fout=M· fref, where fout is the output frequency and fref is the reference frequency.

This chapter begins with the general design considerations of a PLL-based frequency synthesizer, following which comes the overview of two widely-used frequency synthesizer architectures. Subsequently, the behavior characteristics of individual functional blocks (in Figure 2.1) are described and discussed. In conclusion, the noise behavior and loop stability of a frequency synthesizer are analyzed then to draw some conclusions of design issues and trade-offs.

Figure 2.1 Block diagram of a PLL-based frequency synthesizer.

2.1 General Considerations

The most important design considerations of a frequency synthesizer are tuning range, phase noise, spurs, and settling time. Their impacts on general wireless communication systems are investigated in this chapter.

2.1.1 Tuning Range

The basic requirement set for a frequency synthesizer by any wireless communication system is that the synthesizer must be able to generate all required frequencies of the system with a sufficient accuracy for channel selection. Therefore, the voltage-controlled oscillator (VCO) and the prescaler must be carefully designed so as to cover the required dynamic frequency range of the synthesizer.

2.1.2 Phase Noise

A spectral purity of synthesized output signal is the most important requirement in all wireless communication systems. Ideally, the output spectrum of a frequency synthesizer should be a pure tone at the desired frequency, as shown in Figure 2.2(a). In the time domain, the output can be expressed by Eq. (2.1).

( ) cos( 0 )

vout t = ⋅A ω t (2.1) However, due to random amplitude and phase fluctuations, the actual output becomes

[ ] [ ]

( ) ( ) cos 0 ( )

out t

v = A+ε t ⋅ ω t+ t (2.2) θ , where ε( )t represents amplitude fluctuations and θ( )t represents phase fluctuations.

The actual output spectrum exhibits “skirts” around the desired carrier impulse in the frequency domain, as shown in Figure 2.2(b). Because the amplitude fluctuations can be removed or greatly reduced by a limiter, the phase fluctuations, expressed in terms of phase noise, become a bigger and dominant concern in frequency synthesizer design.

The phase fluctuations could be attributed to either the external noise at the frequency-

(a) (b)

Figure 2.2 (a) Ideal; (b) Actual output spectrum of an oscillator.

tuning input of the oscillator or the noise sources such as thermal, shot, or flicker noise of the devices in the oscillator.

The phase noise limits the quality of the synthesized signal. In order to quantify the phase noise, the total noise power within a unit bandwidth at an offset frequency (Δω) from the carrier frequency (ω₀) is compared with the carrier power. As shown in Figure 2.2(b), this quantity is defined as Eq. (2.3) in the unit of dBC / Hz.

{ }

carrier

L P

P

ω ω

ω ^{⎡ + Δ Hz)⎤}

Δ = ⋅ ⎢ ⎥

⎣ ⎦ (2.3)

, where P_sideband(ω₀+ Δω,1Hz) represents the single sideband noise power within a 1Hz bandwidth at an offset frequency (Δω).

(a) (b)

Figure 2.3 Effect of phase noise in (a) the receive path, and (b) the transmit path.

Figure 2.3 illustrates the impact of the oscillator or synthesizer phase noise in both the receive path and transmit path of a transceiver. As depicted in Figure 2.3 (a), in the receive path, the weak desired signal is accompanied by a larger interferer in the adjacent channel. Ideally, the received RF signal is down-converted with a pure LO signal into the desired pure IF signal and the down-converted interferer can be easily filtered. However, in reality, there exists a phase noise skirt around the LO signal. After down-conversion, the weak desired signal could be corrupted by the tail of the interferer spectra and even possibly swamped out if the phase noise skirt is too large. This effect is called “reciprocal mixing”, and it degrades the SNR of the desired signal. In the transmit path, the weak nearby signal of interest can be corrupted by the tail of the large-power transmitted signal, as shown in Figure 2.3 (b).

Therefore, the output spectrum of the LO or synthesizer must be extremely sharp, and a set of stringent phase noise requirements must be achieved so as to satisfy the maximum blocking signal power specified in the wireless communication system.

2.1.3 Spurs

Apart from the phase noise, the other key parameter affecting the spectral purity of synthesized output signal is the relatively high-energy spurious tones (also called spurs), appearing as spikes above the noise skirt, as shown in Figure 2.4 (a).

Figure 2.4 (a) Spurs, and (b) effect of spurs in the receive path

Any systematic disturbance on the tuning input of the oscillator will cause the periodic phase variation and thus modulate the synthesized output. In the frequency domain, it manifests itself as the undesired tones at the upper and lower sideband of the carrier. These tones can be quantified by the difference between the carrier power and the spurious power at certain frequency offset in the dBC unit. The most common type of spur is the reference spur that appears at multiples of the comparison frequency. Due to the non-ideal switching nature of the synthesizer, it may cause reference frequency feed-through, and then the resulting periodic ripples on the tuning input of the oscillator induces the reference spurs at the output, as shown in Figure 2.5.

Figure 2.5 Reference frequency feed-through

As illustrated in Figure 2.4 (b), similar to the case of phase noise, if a large interferer is close to the weak desired signal and the LO signal has spurs, then both the desired signal and interferer will be mixed down to the IF. If the spacing between the desired signal and the interferer is equal to that between the LO signal and the spur, the spur in the down-converted interferer falls into the center frequency of the desired down-converted signal, and then also degrades the SNR performance.

Phase noise and spurious tones in the synthesized signal can limit the ability to receive a weak desired signal in the presence of strong interferers and this ability is called “selectivity”. In later sections, all the contributors and causes of the phase noise and spurs will be addressed so as to specify the design trade-offs.

2.1.4 Settling Time

Transient behavior of the frequency synthesizers is also a critical performance parameter. As shown in Figure 2.1, a change in the division ratio of the frequency divider would result in a loop transient. Every time a different division ratio is set for channel selection, the synthesizer requires a finite time to lock to the new frequency.

The synthesizer needs settling to certain accuracy within the specification of the wireless standard and the overall required time is called “settling time” (also called

“locking time”). Also, one thing worth mentioning is that the locking speed requirement of synthesizers is even more stringent for a fast frequency-hopping spread-spectrum system. Accordingly, a detailed analysis to model the loop settling behavior will also be discussed in later sections.

2.2 Frequency Synthesizer Architectures

The well-known ways to implement a frequency synthesizer can be categorized into three types: the table-look-up synthesis, the direct synthesis, and the indirect or PLL-based synthesis. However, the growing call for miniaturization, low power, low cost and the move towards higher frequencies for emerging communication techniques become critical trends. Therefore, with the ability of high-integration in low-cost CMOS process, the PLL-based frequency synthesizer is the widely-used method in today’s frequency synthesis. An overview of two PLL-based synthesizer architectures:

integer-N and fractional-N synthesizer will be introduced in this section.

2.2.1 Integer-N Architecture

The generic PLL-based frequency synthesizer generates its output by phase- locking the divided output to a reference signal. Due to a low cost IC solution, a charge pump is widely used in PLL-based frequency synthesizers nowadays. As shown in

Figure 2.6, an idea charge pump combined with an ideal phase-frequency detector (PFD) provides an infinite dc gain with passive loop filters, which results in an unbounded pull-in range and zero static phase error. “Integer-N” means that the division ratio N of the frequency divider is a variable integer. In other words, the synthesized output frequency is integer multiples of the input reference frequency. In general, fref is fixed and the frequency step or channel spacing is equal to fref. Various frequencies are achieved by changing the division ratio N. In the locked state, the output frequency is as follows:

out ref

f = ⋅N f (2.4)

Figure 2.6 A simple charge pump PLL-based frequency synthesizer

In the design of integer-N frequency synthesizers, to achieve the fine frequency resolution, a low fref is needed. This low fref yields a high division ratio as well as a narrow loop bandwidth. However, a narrow loop bandwidth results in slower settling speed of transients and deteriorates the in-band phase noise. So, the loop performance of the integer-N architecture is intrinsically limited by the standard-specified frequency resolution. Generally, a larger loop bandwidth is desired to achieve a faster dynamic loop response and suppress the VCO close-in phase noise, but otherwise the reference frequency leakage becomes serious. Additionally, as a rule of thumb, the loop bandwidth should be 10 times less than fref for the consideration of the loop stability under linear, continuous-time approximation [1].

Figure 2.7 shows the generic structure of the full frequency divider (the block

“÷N” in Figure 2.6), which consists of a dual-modulus prescaler (DMP), a swallow counter and a programmable counter. The dual-modulus prescaler, which is dedicated to the high-frequency operation, follows VCO so as to relieve the constraint of the operating speed of the counters. The DMP divides by (P+1) until the swallow counter overflows after which the overflow bit (Modulus Control) will set the DMP in divide-by-P mode until the programmable counter overflows. Then, the overflow bit (Reset) will reset both two counters and the division process restarts. Therefore, the overall division ratio becomes (P+1) ·A+P· (B-A) = P·B+A. The detailed discussion of the frequency divider will be presented in section 2.3.

Figure 2.7 A full divider with a dual-modulus prescaler and two counters

2.2.2 Fractional-N Architecture

As mentioned above, the loop performance of the integer-N architecture is restricted by the given frequency resolution. Compared with the integer-N architecture, however, the fractional-N architecture [11]-[13] shown in Figure 2.8 allows a higher reference frequency for a desired fine frequency resolution. The higher reference frequency implies the wider loop bandwidth, yielding faster settling speed and more suppression of VCO close-in phase noise.

Figure 2.8 A fractional-N frequency synthesizer with an accumulator

A simplified block diagram of a fractional-N frequency synthesizer utilizing an accumulator is shown in Figure 2.9. The accumulator, which consists of an adder and a latch, is clocked by the reference frequency. The output (X+Y) of the adder is latched and then fed to the adder as an input Y. The input X contains the data (K) to be accumulated. When the total (X+Y) exceeds the maximum size (2^k) of the adder, an overflow occurs and then the division ratio of the DMP is changed. The DMP divides its input by N when the accumulator is not overflow. When an overflow occurs, the DMP divides its input by (N+1). For every 2^k clock cycles, the accumulator overflows K times.

Thus, the DMP divides K cycles by (N+1) and 2^k-K cycles by N, resulting in an average division ratio:

( 1) (2 )

2 2

k

avg k

K N K N K

N = ⋅ + + − ⋅ = +N _k (2.5)

It can be seen that, therefore, fref can be many times the frequency step resulting in a higher loop bandwidth without compromising the settling speed and the in-band phase noise. But the periodically alternating process of the DMP causes a sawtooth phase error.

This phase error will generate severe spurious tones, which are called “fractional spurs”

at all multiples of the offset frequency (

2^{k ref}

K × f ) if not filtered. This sawtooth phase

error could be predictable and further eliminated by the classical phase interpolation method [14], as shown in Figure 2.8. This compensation technique requires accurate matching of compensation signals which is sensitive to temperature and process variations. Another solution for large fractional spurs is to randomize the prescaler modulus by using a higher-order Σ-Δ modulator [13]. Its noise-shaping property shapes the noise spectrum of the carrier such that most of the noise energy can appear at large frequency offsets and be pushed outside the loop bandwidth, hence the close-in noise can be suppressed. Arbitrarily fine frequency resolution can be achieved, limited only by the size of the digital adder.

Concerning Σ-Δ Fractional-N PLLs, abundant literatures have been published, and thereby we ends up with the above discussion due to being far away from the focus of this thesis.

Figure 2.9 Classical phase interpolation method for spur cancellation

2.3 Fundamentals of Phase-Locked Loop (PLL)

When designing a PLL-based frequency synthesizer, it is very important to have the complete knowledge of the behaviors of each functional block as well as the overall closed-loop behavior. As discussed earlier, a charge pump is widely used in PLLs nowadays. Therefore, the following subsections focus on the discussion of integer-N charge pump PLL-based (CPPLL-based) frequency synthesizers.

2.3.1 Phase-frequency Detector (PFD)

An idea phase detector (PD), as shown in Figure 2.10, produces an output whose average dc value is linearly proportional to the phase difference between its two periodic inputs, namely the reference signal (R)and the divided signal (V).

out PD

v =K ⋅ Δθ (2.6) , where KPD is the gain of the phase detector (specified in V/rad) and Δθ is the input phase difference.

Figure 2.10 Characteristic of an ideal phase detector

Nowadays, the common phase detectors can be categorized to three types: the analog multiplier-type, the XOR-type, the sequential-type. However, the analog multiplier-type phase detector exhibits the nonlinear dependence of the output voltage on the phase difference and the instability, resulting from the inverted gain polarity beyond the phase difference range, ± π/2. Concerning the XOR-type phase detector, the instability issue still exists except for the nonlinear dependence.

Unlike the multiplier-type and XOR-type, which are only phase-sensitive, the phase-frequency detector (PFD) is a sequential phase detector triggered by else the rise or fall edge of the reference signal (R) and the divided signal (V). As a result, the PFD has the capability of operating as a frequency discriminator for large frequency errors or as a coherent phase detector once inside the pull-in range of the PLL, allowing a fast frequency acquisition and a full linear phase difference range, ± 2π (shown in Figure 2.11).

Figure 2.11 PFD characteristic

As illustrated in Figure 2.12, the operation of a typical PFD is as follows. If initially UP = DN = 0, then a rising transition on R leads to UP = 1, DN remains 0. The circuit remains in this state until V goes high, upon which UP returns to zero simultaneously. The behavior is similar for the V input. Thus, the average dc value of (UP-DN) is an indication of the frequency or phase difference between R and V.

Figure 2.12 Conceptual operation of a PFD

To achieve a PFD with the above behavior, at least, three logical states are required:

UP = DN = 0 (state 0); UP = 1, DN = 0 (state I); UP = 0, DN = 1 (state II). Figure 2.13 shows a state diagram summarizing the operations. If the PFD is in the state 0, then a transition on R takes it to state I. During state I, any more rising edge on R won’t changes the state at all. The PFD will remain in this state until a transition occurs on V, upon which the PFD returns to state 0 immediately. The switching sequence between state 0 and state II is similar. Such a PFD is called “tri-state phase-frequency detector”.

Figure 2.13 State diagram of a three-state PFD

2.3.2 Charge Pump (CP)

A PFD couldn’t alone provide the exact voltage (or current) signal proportional to the phase difference at its inputs. A charge pump serves to convert the difference of the two output signal UP and DN of the PFD into the corresponding error current either sourced to or sunk from the loop filter, depending on the state of the switches SU and SD

controlled by UP and DN, respectively. No current flows through the loop filter if both switches are off and the output node represents an infinite-impedance towards the loop filter.

A charge pump (CP) with a PFD and a capacity CP as the loop filter is shown in Figure 2.14, which illustrates the corresponding time-domain response. One should note that the system is nonlinear and discrete time in the strict sense. To overcome this

quandary, it can be approximated by a continuous-time model only when the loop bandwidth is much less than the reference frequency [1]. Therefore, the characteristic of the PFD and charge pump can be together approximated linearly as:

e P 2

I I θ

π

= ⋅Δ (2.7)

, where I_e is the average error current over a cycle, Δθ represents the phase error between the PFD inputs and IP = I1 =I2 is the current value of the two current sources in the charge pump.

Figure 2.14 Block diagram of PFD with CP, and the timing diagram

2.3.3 Loop Filter (LF)

The loop filter (LF) determines most of the PLL’s specifications. In CPPLLs, unlike many other feedback systems, the variable of interest changes dimension around the loop: it is converted from phase to current by the PFD/CP, processed by the LF as

such, and then converted back to phase by the VCO. More specifically, the loop filter serves to convert the error current Ie, proportional to detected phase error, into the corresponding control voltage for VCO. In general, the loop filter can be realized in either active or passive forms, and its design has a great impact on the overall system performance of CPPLLs, such as the loop stability and noise rejection. The stability issue of great concern tends to apply for low order filters, which conflicts with the noise-rejection requirement. Figure 2.15 shows three features of the passive filter commonly adopted in most CPPPLs, namely first-order, second-order, and third- order filters, respectively.

Figure 2.15 Different features of the passive filter

2.3.4 Voltage-Controlled Oscillator (VCO)

Figure 2.16 VCO characteristic

An ideal voltage-controlled oscillator, as shown in Figure 2.16, is a circuit that generates a periodic output whose frequency is a linear function of a control voltage