For active device applications similar to the conventional FETs, the semiconducting-type single-walled nanotube (SWNT) is more suitable than the metallic-type SWNT because in the former, the channel conductance can be controlled/modulated by the gate bias. It is also noted that if the CNTs are multi-walled (MWNT) in nature, they will depict metallic-type electrical behaviors and will not be suitable for many nanoelectronics applications. In general, the CNT-FET acts like a p-type conduction device when it is exposed to air [1-5]. This phenomenon is ascribed to the absorbed oxygen at the interface of metal/SWNT, causing the pinning of Fermi level near the valance band [6-10]. Once the p-type CNT-FET is annealed in vacuum, the absorbed oxygen in the interface will be removed, and the CNT-FET is transformed from the pure p-type conduction to ambipolar or n-type conduction, depending on the annealing condition and/or the amount of remaining oxygen [10,13,15-17]. It is worth noting that if a device is ambipolar, it conducts either electrons or holes depending on the gate bias (In this chapter, the gate bias corresponds to bottom-gate bias. For the conventional structure with a traditional single gate, the ambipolar phenomenon would be disastrous as the ambipolar phenomenon cannot be easily suppressed). However, the electrical characteristics of the converted CNT-FETs vary widely and uncontrollably in this process, and the across-the-chip variations of FETs often widen and become
Based on a former study of our group, we can manufacture air-stable n-type [12-13] or p-type CNT-FETs without any additional or complex annealing process (Table 3.1). However, we found that some ambipolar-type devices are always present in the Type-I devices due to process nonuniformity. And the Type-II devices always depict either n- or p-type characteristics rather than ambipolar type, depending on the passivation layer deposited on the SWNTs. For practical applications, we must eliminate the ambipolar devices by converting them to n- or p-type devices as needed.
Nonetheless, it is difficult to alter the conduction-type of individual CNT-FET located on the same chip. In contrast, the novel double-gated CNT-FET (DG CNT-FET) structure proposed in this chapter can provide a practical and reproducible method to form both n- and p-type-like CNT-FET devices as well as unipolar-type CNT-FET devices on the same chip [12,14]. The bias applied to the narrow top-gate plays the pivotal role of modulating the energy level within the CNT energy band.
With the new approach, we can control the electrical characteristics of the CNT-FETs reliably without depending on complicated and often uncontrollable processes [15-16].
3.2 Device Fabrication
Two double-gated (DG) device structures, i.e., Type-I and Type-II, were fabricated in this work. While Type-I DG device utilizes the substrate wafer as a universal bottom-gate, Type-II DG device employs a separate patterned Ti layer as its individual bottom-gate. More importantly, different dielectric layers (both oxide and nitride) were employed in both types of devices (Table 3.1), which allows us to study the effects of oxygen absorption behaviors on the devices. The key process flows for fabricating the two device types are described below:
3.2.1. DG CNT-FETs with substrate wafer as the universal bottom-gate (Type-I) The key process flow of the tunable Type-I DG CNT-FET structure with a universal substrate bottom-gate is shown in Figs. 3.1(a) – 3.1(d). Briefly, a 100nm silicon oxide was thermally grown on a 4-inch p-type silicon wafer. The silicon substrate wafer with a low resistivity of 0.02Ω-cm also serves as the universal bottom-gate (i.e., Si substrate acts as the back-gate). Then, a 150-nm Ti layer was deposited by RF sputter, patterned, and etched to serve as the source/drain metal, as shown in Fig. 3.1(a). The spacing between the source and the drain electrodes is designed to be 2µm. After the source/drain electrodes were patterned and etched, a prepared SWNT/Dimethylformamide (DMF) solution with the CNT density of
mm2
10,000 (counted by SEM pictures manually, as shown in Fig. 3.1(f)) was spun on the wafer, as shown in Fig. 3.1(b). Subsequently, a 200-nm low-temperature PE-CVD oxide was deposited at around 400 oC, as shown in Fig. 3.1(c). Next, contact holes of the source/drain regions were etched in the MERIE (magnetic enhanced RIE) dry etcher using CHF3 gas. Finally, a second 150-nm Ti layer was deposited by RF-sputter, patterned, and etched to serve as the top-gate, as shown in Fig. 3.1(d). The top-gate length is designed to be either 0.6µm or 0.8µm , and is placed in the middle between the S/D regions. The patterned second Ti layer also serves simultaneously as the pads for the source/drain contacts. In this way, a narrow top-gate was thus created on a bottom-gated SWNT FET, and the conduction type of the FET could be modulated by the bias applied to the narrow top-gate.
3.2.2 DG CNT-FETs with patterned Ti-layer as the individual bottom-gate (Type-II) In order to strengthen the modulation of CNT-FET channel conduction, we
modify the Type-I design (shown in Fig. 3.1(d) as described above) to that shown in Fig. 3.1(e). It should be noted that a separate patterned bottom-gate is adopted while Type-I employs a universal bottom-gate. More importantly, while PECVD oxide was adopted as the top-gate dielectric in Type-I devices, both PECVD oxide and nitride were tried as the top-gate dielectric layer in Type-II devices, which allowed us to study the effects of oxygen desorption on the CNT-FET behaviors. Briefly, to fabricate Type-II devices, a 600-nm SiO2 field oxide layer was first grown by wet oxidation at 985 oC on the 4-inch p-type silicon wafer. Then, a 150-nm Ti layer was deposited by RF sputtering, which was subsequently patterned and etched to serve as the bottom-gate metal. Afterwards, the wafer received a 200-nm low temperature PE-CVD oxide or nitride deposition process. A second 150-nm Ti layer was then deposited by RF sputtering, patterned, and etched to serve as the source/drain electrodes. Next, the SWNT/DMF solution was spun on the wafer, followed by another 200-nm PE-CVD dielectric deposition at around 390 oC (Table 3.1). Then, the contact holes of the source/drain regions were etched in the same MERIE dry etcher.
Finally, a third 150-nm Ti layer was deposited by RF-sputtering, patterned, and etched as the top-gate. This patterned 3rd Ti layer also serves simultaneously as the pads for the source/drain contacts, while the position and dimension of the top-gate are nominally identical to those in Type-I structure. Afterwards, the wafers were annealed at 250°C in the air to improve the metal/CNT contact. The final Type-II DG CNT-FET device structure is as shown in Fig. 3.1(e). A commercial HP-4155A was applied to measure the Id/Vg transfer curves of the CNT-FETs. The result will be discussed in the following sections.