Since we have fabricated two types of DG CNT-FET device structures, the device characteristics of both structures will be discussed. For the first device structure (Type-I, as shown in Fig. 3.1(d)), the entire substrate wafer, which serves as the bottom-gate, was biased from -5V to +5V at Vds = 1V; while the top-gate was biased from 0V to -12V, at a step of -2V. The resultant transfer curves (i.e., drain current versus bottom-gate voltage) of a Type-I CNT-FET are shown in Fig. 3.2. It can be seen that, for this particular Type-I CNT-FET, when the top-gate voltage is biased at 0V, the CNT-FET exhibits ambipolar-type FET behavior. However, when the top-gate is biased toward more negative value (e.g., from 0V to -12V), the transfer characteristics change significantly. Specifically, for a given positive bottom-gate voltage, the drain current IDS decreases as the top-gate voltage Vtg decreases from 0V to -12V, while IDS for a given negative bottom-gate voltage increases instead. It can be seen that when the top-gate is decreased to -12V, the conducting channel under positive bottom-gate voltage is effectively pinched off, while the channel under the negative bottom-gate voltage is enhanced, as shown in Fig. 3.2. In a word, ambipolar-type CNT-FET is gradually converted to p-type CNT-FET by simply changing the top-gate voltage. In Fig. 3.5(c), it can be seen that a Type-I ambipolar device could be converted to n-type CNT-FET by applying a positive top-gate voltage.
A hypothesis based on the CNT-FET band gap structure is proposed to gain insights into the physical mechanisms of the conduction-type-tunable Type-I DG CNT-FET structure shown in Fig. 3.1(d). It is worth noting that many generic (i.e., without top-gate bias) Type-I CNT-FET devices in our study exhibit ambipolar behaviors, rather than the n-type-only behaviors. This trend in Type-I devices is
believed to be the result of using PECVD oxide as the top-gate dielectric. This is because at the process temperature of around 400°C, even though high enough to desorb oxygen from CNT, a few oxygen atoms could be driven back to CNT during the PE-CVD TEOS oxide deposition process [10,13-14]. We therefore choose a generic ambipolar, rather than the n-type-only, CNT-FET to illustrate the proposed hypothesis. Its transfer characteristics (drain current versus bottom-gate voltage) are as shown in Fig. 3.3(a).
There has been increasing evidence to support that the interface behaves as a Schottky contact at the source and drain regions [10-11,13,15-17]. As shown in Fig.
3.3(b), when the bottom-gate voltage is floating, a few holes can be conducting.
However, as shown in Fig. 3.3(d), when a positive bottom-gate voltage (with the top-gate floating) is applied to the CNT-FET, the energy band corresponding to the middle CNT channel region will be pulled down, decreasing the effective electron tunneling barrier. As a result, more electrons can tunnel through the interface barrier, and the electron current increases. On the other hand, as shown in Fig. 3.3(c), when a negative bottom-gate bias is applied (with the top-gate still floating), the energy band corresponding to the middle CNT channel region will be raised, so the holes can drift through the interface barrier easily. Consequently, the DG CNT-FET with the top-gate floating exhibits ambipolar characteristics.
Fig. 3.4 shows the band diagram when the effect of the top-gate bias is superimposed to our DG CNT-FET. As mentioned above, for a given positive bottom-gate, the energy band will be pulled down, and allows the electrons to tunnel through easily. By simultaneously applying a top-gate voltage to the DG CNT-FET, the energy band of CNT region directly under the top-gate electrode is altered.
Specifically, when a positive bias is applied to the top-gate, the energy band of CNT
region directly under the top-gate electrode is pulled further down, while the barrier at the metal-CNT interface remains unchanged, as shown in Fig. 3.4(a). The current, resulting from electron flow, therefore remains essentially unchanged. If a large positive top-gate voltage is applied, the down-bending potential profile will slightly accelerate the electron flow in the CNT due to the barrier lowering effect, and the drain current will increase slightly. However, when a negative bias is applied to the top-gate, the energy band of CNT region directly under the top-gate electrode is pulled up instead, as shown in Fig. 3.4(b). Since the extra electron barrier at the conduction band is created within the CNT region itself, the electron flux inside the CNT is effectively blocked. Therefore, even though the initial CNT-FET shows ambipolar behaviors, the electron flow channel is effectively blocked off by the negative top-gate bias. At the same time, the hole current at the negative bottom-gate region remains essentially unchanged because the extra barrier exists at the conduction band only (Fig. 3.5(a)). The CNT-FET now behaves like a p-type conduction, as shown in Fig. 3.4(c) (Vds=1V). The more negative the top-gate bias is, the lower the conducting current can be obtained at a given positive bottom-gate bias.
This is consistent with the trend shown previously in Fig. 3.2. This explains why the Type-I DG CNT-FET will behave like p-type FET under the negative top-gate bias, even the generic Type-I CNT-FET (i.e., the device without the top-gate modulation) depicts ambiploar behaviors.
Fig. 3.5 shows the case for the negative bottom-gate bias. When a negative bias is applied to the top-gate simultaneously, the barrier lowering effect occurs at the drain side that results in a significant increase of hole tunneling, as shown in Fig.
3.5(a) [18]. However, when a positive bias is applied to the top-gate, as shown in Fig.
3.5(b), the hole flux is blocked. This will suppress the conductance of holes, and the
generic ambipolar CNT-FET now depicts n-type FET characteristics, as shown in Fig.
3.5(c) (Vds = 1V).
Since for the mainstream CMOS circuit applications, both p- and n-type MOSFETs are called for on the same chip. It is necessary to form n-type, in addition to p-type CNT-FETs, on the same chip for the complementary circuits. Several approaches have been previously reported to form n-type CNT-FETs by employing complex doping processes (e.g., adopting alkali metals) [19-21] or thermal/electrical annealing processes [10]. These approaches, however, require extra processing and masking steps to convert generic p-type CNT-FETs in vacuum or in the inert gas. In contrast, no extra annealing steps are needed to form air stable n-type CNT-FETs [12-13] selectively using the DG CNT-FET structure proposed in this chapter. As mentioned previously, for the Type-II structure both PE-oxide and PE-Nitride were tried as the top-gate dielectric. By using PE-Nitride as the top-gate dielectric, the process temperature of the deposition would be high enough to simultaneously remove the oxygen atoms from the CNT or CNT/metal interface in the PE-CVD deposition chamber. So we can fabricate n-type CNT-FETs by selectively converting generic Type-II structures without extra processing steps. This is because when the oxygen atoms are removed during the PE-CVD process, the Fermi-level in Type-II structure moves away from the valence band and becomes closer to the middle of the bandgap, compared with that of Type-I structure shown already in Fig. 3.3(b). So by applying a negative bias to the bottom-gate of Type-II CNT-FETs selectively, the hole cannot tunnel through the energy barrier efficiently, and we could selectively create n-type CNT-FETs on the chip.
Although we can create n-type CNT-FETs selectively, how to control the uniformity of electrical characteristics of these devices remains an open question.
Since the generic Type-I devices tend to depict ambipolar behaviors, the electrical characteristics of the Type-I devices, however, can be tuned to either n- or p-type behaviors precisely, according to the hypothesis described above.
As shown in Fig. 3.6(a), the initial transfer characteristics of the Type-II CNT-FET depict pure n-type behavior with Imax = 63.2 nA at Vbg = 10V and Vds = 1V, representing on/off ratio of greater than 105. Depending on whether a positive or negative bias is applied to the top-gate, the Type-II CNT-FET will behave differently.
When the top-gate is negatively biased, the drain current of Type-II CNT-FET decreases, and reaches complete pinch-off when the top-gate becomes more negative than Vtg = -10V. On the other hand, the drain current increases slowly as the top-gate increases toward more positive value. These trends could again be explained by the proposed hypotheses shown previously in Fig. 3.4 and Fig. 3.5. At Vtg = -10V, the down-bending energy band in the Type-II CNT FET, similar to that shown in Fig.
3.4(b) for the Type-I structure, is pulled up instead in the region directly under the top-gate, which effectively blocks the electron flow. On the contrary, when a positive top-gate is applied, the down-bending potential profile, similar to that shown previously in Fig. 3.4(a) for Type-I structure, will slightly accelerate the electron flow due to the barrier lowering effect, and the drain current increases slightly, as shown in Fig. 3.6(b). It is noticed that the current in Fig. 3.6(a) decreases in the negative bottom-gate region when the top-gate voltage increases. This is because according to Fig. 3.5(b), when the top-gate voltage becomes more positive, the energy band directly under the top-gate will be bent down further, and this down-bending potential will block the hole tunneling.
This hypothesis could also be applied to explain the suppression of the p-type behavior in Type II devices (Fig. 3.7). Fig. 3.6 shows a generic n-type Type-II device
with its n-type characteristics being gradually suppressed under negative top-gate biases, while Fig. 3.7 depicts a generic p-type Type-II device with its p-type characteristics being gradually suppressed under positive top-gate biases. These trends are consistent with our proposed hypothesis.
By resorting to DG CNT-FET structure, Vth of the device can be modulated by varying the biases of the top-gate and the bottom-gate. When the roles of the top-gate and the bottom-gate are reversed, the transfer curves (drain current versus top-gate voltage) of DG CNT-FET are plotted in Fig. 3.8. It can be seen that when the bottom-gate is floating and the top-gate voltage is swept from –8V to +8V and back to –8V, a pronounced hysteresis loop is observed [22-25]. In our work, four kinds of bottom-gate and top-gate dielectric layers (i.e., PE-oxide, PE-nitride, thermal-oxide, and thermal-nitride) were studied, and the hysteresis phenomenon persists. Here in Fig. 3.8 we only depict the data with PE-nitride as both the bottom- and top-gate dielectric layers. When Vbg > 0V, by sweeping from –Vtg to +Vtg, the corresponding energy band switches from that shown in Fig. 3.4(b) to Fig. 3.4(a); and by sweeping from +Vtg back to -Vtg, the corresponding energy band switches from that shown in Fig. 3.4(a) back to Fig. 3.4(b). The energy band shift that occurs during Vtg sweeping accounts for the observed hysteresis loop observed in Fig. 3.8. Similarly, When Vbg <
0V, by sweeping from –Vtg to +Vtg, the corresponding energy band switches from that shown in Fig. 3.5(a) to Fig. 3.5(b), and vice versa. The corresponding shift in energy band between the two cases (i.e., from Fig. 3.4(b) to Fig. 3.4(a), compared to that from Fig. 3.5(a) to Fig. 3.5(b); and vice versa) is essentially identical. This explains why the hysteresis loops between the curves with either positive or negative bottom-gate biases are essentially identical, as shown in Fig. 3.8.