Performance of CNT-FET devices

Out of a total 1173 devices produced on one test wafer, 493 metallic bundled-CNTs (42.03%), 204 semiconducting-type CNT-FETs (17.39%) with an on/off ratio of less than or equal to two orders, and 17 semiconducting-type CNT-FETs (1.45%) with an on/off ratio ranging from two to six orders, were obtained in this study. It is worth noting that in a batch of as-grown CNTs, both metallic and semiconducting type CNTs were present [17]. When at least one metallic CNT is included in the bundle, the bundled-CNTs would show a gradual transition to metallic character. It is plausible that if the number of metallic CNTs is small, the bundled-CNTs will still exhibit weak semiconducting characteristics. On the contrary, if the number of metallic CNTs is large, the bundled-CNTs will show metallic characteristics. In general, when the on/off ratio of our CNT-FETs is about 10 ~ 100, less than 5 ~ 10 metallic CNTs are included in the channel (i.e., the space between two catalyst islands). Only when all CNTs in the bundle are semiconducting can a high performance in the CNT-FETs be expected.

Since our bundled-CNTs were exposed to the air (Fig. 5.2(c)), all the as-grown CNT-FETs manufactured in this study were p-type semiconducting in nature [29,30].

Fig. 5.8(c) shows the electrical properties (i.e., I_d-V_d and I_d-V_g) of an as-grown p-type CNT-FET with five orders of on/off ratio. The bottom-gate voltage applied in Fig.

5.8(c) varies from 0V to -10V (at a step of -2V) at Vds = -1V. It should also be noted that the CNT-FETs with one to two orders of on/off ratio are rendered acceptable to serve the role of sensors. However, in order to manufacture complementary CNT-FET structure (similar to conventional silicon-based CMOS devices) for broader applications, n-type CNT-FETs are indispensable. Previously, our group has successfully manufactured air-stable n-type CNT-FETs [26-28] without resorting to any additional and complex annealing process. After measuring the electrical properties of some wafers that depict generic p-type CNT-FETs in this work, a 300 ~ 400nm-thick silicon nitride film was deposited on the wafer as passivation layer by PECVD at 390^oC. Afterwards, the contact holes of the source/drain and bottom-gate regions were etched in the same MERIE dry etcher. Our experimental data confirmed that the generic p-type CNT-FETs are converted to air-stable n-type CNT-FETs, as shown in Fig. 5.8(d). The converted n-type CNT-FETs depict one to four orders of on/off ratio when the bottom-gate is biased from 0V to 10V (at a step of 2V) at Vds = 1V. This is ascribed to the use of PE-nitride film as the passivation layer whose deposition temperature is high enough to simultaneously remove the oxygen atoms from the CNTs or CNT/metal interface in the PE-CVD deposition chamber. The approach offers a feasible method to fabricate air-stable n-type CNT-FETs by converting the generic p-type CNT-FETs.

It is worth noting that theoretically both n- and p-type CNT-FETs can be fabricated on the same chip by selectively converting some of the generic p-type CNT-FETs on the chip, while leaving other p-type CNT-FETs on the same chip untouched. The design of a new photo mask set is currently under way which will allow us to test the feasibility of the idea.

Although the device performance of our proposed process has yet to be

optimized, our initial results are encouraging and suggest a viable method of fabricating functional CNT-FETs. Using the CNT growth method proposed in this chapter, we believe it is possible, with further process refinement, to manufacture semiconducting-type CNT-FETs suitable for many applications, especially sensors. As mentioned above, the CNTs synthesized in this study contain a high percentage of metallic-type CNTs, representing about 42.03% of metallic bundled-CNTs out of the total as-grown devices. We do believe however that after optimizing the growth conditions and applying plasma treatment on the as-grown CNT-FETs, a much higher percentage and a higher on/off ratio of semiconducting-type CNT-FETs are achievable [31].

5.4 Summary

To the best of our knowledge, only SWNTs can show the semiconducting-type behaviors. And judging from our electrical measurement results and TEM pictures (Fig. 5.3(b)), we deduce that the CNTs we synthesized are mostly bundled-SWNTs.

This result is also consistent with earlier study [32].

In order to synthesize long CNTs, it is critical to balance the rate of ethanol decomposition and the rate of carbon atom diffusion. In other words, the carbon supply route needs to remain open during processing. The rate of carbon diffusion will be dominated mostly by the temperature, and the ethanol decomposition rate will be affected by both the synthesis temperature and the flow rate of the carrier gas (Ar).

In short, we have developed an integrated circuit (IC) compatible process for fabricating CNT-FETs successfully with a shorter hydrogen reduction time in this study. Longer CNT length can be obtained by optimizing carbon ratio during synthesis, and the accumulation of carbon on the catalyst tip can be controlled by

mixing inert gas with the carbon source. This IC compatible process seems to be promising for fabricating a pre-aligned single-walled carbon nanotube matrix for both n- and p-type CNT-FETs.

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Table 5.1 Co²⁺ residues in major process equipments.

Figure 5.1 The influence of moisture and stirring time on the preparation of CMT solution. (a) CMT film cracks after first soft bake (CMT was exposed to moisture when stirred). (b) Co particles aggregate together after first soft bake without proper stirring. (c) Co particles disperse well after first soft bake with proper stirring of the CMT solution. Note that the patterns in (b) and (c) are pre-defined n⁺-poly bottom gate electrodes.

Figure 5.2 Process flow for the growth of bundled-CNTs. (a) Catalyst mixed TEOS (CMT) and pure TEOS layers were spun on oxidized substrate with patterned bottom gates, followed by photolithography and RIE processes to form CMT catalyst islands. (b) Growth of suspending SWNTs connecting two neighboring catalyst islands. (c) Ti metal lift-off process to form source/drain electrodes. The inset of Fig. 5.2(c) shows two kinds of catalyst islands and S/D metal pads in our layout design. Note that the individual bottom n⁺-poly gate and the gate oxide or nitride layer were both formed before the CMT was spun.

a) b)

c)

Figure 5.3 TEM pictures for CMT layer and bridged-CNT. (a) Cobalt nanoparticle uniformly embedded in oxide layer. (b) Bundled-SWNT synthesized from CMT powders with 10 nm in diameter. (c) Many bridged SWNTs are formed between the CMT catalyst islands.

Figure 5.4 The adhesion of CMT layer on different layers. The vernier structure (i.e., the scale bars) indicates the resolution of photolithography and the finest pattern after dry etching. (a) CMT spun well on thermal oxide layer. (b) Poor adhesion of CMT layer on nitride. (c) By adding a hexamethyldisilazane (HMDS) layer before CMT spinning, good CMT catalyst islands are obtained on nitride layer suitable for bio-sensor purposes.

b) a)

Figure 5.5 SEM pictures of lateral-grown CNTs (a) Formed by dry etching. (b) Formed by wet etching. The bundled CNTs bridge the CMT layer from the catalyst.

Figure 5.5 (c)-(d) The leakage current range without any post treatment by using dry etcher to form the catalyst islands. Note the leakage current is in the µA range because of the residues of Co particle/CMT layer, which can leave a conductive layer on the wafer surface and short the CNT-FETs.

b)

Figure 5.6 (a) Lateral length of CNT versus gas composition. (b) SEM picture of CNTs when Co²⁺ concentration is 1.5M. and (c) SEM picture of CNTs when Co²⁺ concentration is 0.5M.

0 1 2 3 4 5

0.25 0.4 0.5

Carbon Ratio

C N T l en g th (u m )

5000 sccm Total flow rate :

3500 sccm

a)

c)

Figure 5.7 SEM picture of tip-growth.

Figure 5.8 The picture of an as-grown semiconducting-type CNT-FET and its Ids-Vds curve.

Insets show the corresponding transfer curves (Ids-Vg). (a) The optical microscope image of the Type-I device in Fig. 4.2(c). Note the black clusters are CNTs (without TEOS layer covering CMT catalyst islands). (b) SEM morphology of 6 µm-long CNT grown between two catalyst islands.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

Figure 5.8 (c) An as-grown p-type CNT-FET with five orders of on/off ratio. (d) Converted n-type CNT-FET after depositing a 300 nm Si3N4 film on the p-type CNT-FET shown in (c).

Chapter 6

Complementary Carbon Nanotube-Gated Carbon Nanotube Thin-Film Transistor

6.1 Backgrounds and Motivation

Single-wall carbon nanotube (SWNT) is an ideal candidate for future nanoelectronics because of its small diameter, high current-carrying capability, and high conductance in a one-dimensional nanoscale channel. The carbon nanotube (CNT) field effect transistor (FET) and several related logic gates have been fabricated by using semiconducting-type CNTs [1–3] as the building block, and the CNT-FET shows superior electrical properties over the conventional silicon metal-oxide-semiconductor field effect transistor (MOSFET). Although these CNT-FETs feature a small channel width, the gate length is usually larger than 100 nm which is limited by the lithography process [3].

Previously, our group have manufactured n-type [4–6] and p-type CNT-FETs without resorting to any additional and complex annealing process (Table 6.1). In this study, a complementary CNT-gated CNT-FET (CG-CNT-FET) structure is proposed and demonstrated. Without relying on electron-beam lithography, the gate length and the gate width of CNT-FET are easily shrunk to 20– 50 nm or less. This is achieved by using two perpendicularly-crossed SWNT bundles as the interchangeable channel and gate. The new CG-CNT-FET shows either n-or p-type FET characteristics, depending on whether the bottom CNT bundle (CNT1) or the top CNT bundle (CNT2) is used as the channel, with the other CNT bundle acting as the gate. After interchanging the roles of the gate and the channel, the upsidedown device still shows

6.2 Device Fabrication

The key fabrication process of the dual-functionality CG-CNT-FET is as follows: Briefly, a 600 nm SiO₂ field oxide layer was first grown by wet oxidation at 985 ° C on 4 in. p-type silicon wafer. Then, a 100 nm Ti layer was deposited by radio-frequency (rf) sputtering, and subsequently patterned and etched to serve as the source/drain metal pads in the upright mode (and as the gate metal pads in the upsidedown mode). The width of the source/drain metal pads is 1µm, and the spacing between source and drain pads is 2µm, as shown in Fig. 6.1(a). Afterwards, the bottom SWNT bundle (CNT1) was coated to serve as the channel in the upright mode (and as the gate in the upsidedown mode). Then, a 100 nm Si₃N₄ was deposited by plasma-enhanced chemical vapor deposition (PECVD) at 390°C to serve as the gate insulator. Next, a second 100 nm Ti layer was deposited by rf sputtering, and subsequently patterned by lithography and dry etching to serve as the gate metal pads in the upright mode (and as the source/drain metal pads in the upsidedown mode).

Afterwards, the top SWNT bundle (CNT2) was coated. It is worth noting that CNT2 was laid perpendicularly crossing the first CNT1 bundle to serve as the gate in the upright mode (and as the channel in the upsidedown mode). This is followed by a 100 nm SiO₂ deposition by PECVD at 400°C to serve as the passivation layer. Contact holes to the gate and source/drain metal pads were subsequently etched in a MERIE dry etcher. Wafers could then follow a standard back-end processing to completion. A commercial HP-4155A was applied to measure I_ds-V_ds and I_ds-V_g transfer curves of the CNT-FETs.

6.3 Experimental Results and Discussion

The top view and cross section of the completed device are shown in Figs. 6.1(a) and 6.1(b), respectively. By controlling the process, the bottom CNT1 bundle behaves as an n-type semiconductor, while the top CNT2 bundle behaves as p-type semiconductor [4-6].

Scanning electron microscopy (SEM) image of the CNT-gated CNT-FET is shown in Fig. 6.2. It can be seen that the two CNT bundles, which serve as the gate and the channel interchangeably, are placed on each side of the gate insulator. Note that the two CNT bundles are perpendicularly crossed so as to form a FET structure at the intersection. The diameter of each CNT bundle is around 20 to 50 nm. A bias voltage, which is applied to the top CNT2 bundle, modulates the bottom CNT1 bundle at the intersection. The effective gate length is only 20– 50 nm. I_ds-V_ds characteristics of the CNT-gated CNT-FET are shown in Fig. 6.3. The drain current of the CNT-FET with silicon nitride as the gate insulator increases with the gate voltage, and shows typical n-channel FET characteristics. The on/off current ratio is ~ 1000.

By interchanging the roles of the channel and the gate, i.e., the conducting channel now becomes the gate (i.e., the bottom CNT1 bundle becomes the gate), while the gate becomes the new channel (i.e., the top CNT2 now becomes the channel), the upsidedown device also shows FET characteristics, as shown in Fig. 6.4, albeit with the complementary conduction type (i.e., p type). This is because of the close proximity between CNT2 bundle and the oxide passivation layer (Table 6.1).

From the above results, we found that both the bottom and top CNT bundles in the structure can act as the channel and the gate interchangeably. This behavior is unique and differs from traditional Si-based devices. It opens up a new possibility and flexibility in circuit design. For example, the signal is usually routed from one

MOSFETs’ drain electrode (i.e., output) to the next stages’ gate electrode (i.e., input) in Si-based MOSFET circuits. It would require a via and a metal line to connect the two MOSFETs. In contrast, in the new dual-functionality CG CNT-FET structure, one CNT can act as the conduction channel of the first FET and the gate electrode of the next one simultaneously. No interconnection metal is thus needed. In addition to the small gate length and the dual-functionality CNT, the new CNT-FET also offers both n-and p-type characteristics, lending itself readily to complementary-type circuit

implementation, i.e., the CNT conducting channel is changed from n type (i.e., CNT1, as described previously) to the p type (i.e., CNT2). It is worth noting that the conduction-type of CNT can be tailored by the passivation layer in close contact with the CNT (Table 6.1), as the passivation layer greatly affects the oxygen desorption/reabsorption of the nearby SWNTs, which in turn set the conduction type.

By using plasma-enhanced (PE) nitride as the gate dielectric layer on top of CNT1, the process temperature of the deposition would be high enough (390°C) to simultaneously remove the oxygen atoms from the CNT1 and CNT1/metal interface in the PECVD deposition chamber. Therefore, we can achieve n-type CNT1 channel without extra processing steps [4-6]. For CNT2 as the channel, we adopted PECVD oxide as the passivation layer in this work. The process temperature was around 400°C. Even though this temperature was high enough to desorb oxygen from CNT2, a few oxygen atoms could be driven back to CNT2 during PECVD TEOS oxide process [7,8]. So CNT2 depicts p-type semiconducting characteristics. This is because when the oxygen atoms are reabsorbed during the PECVD oxide process, the Fermi level in CNT2 moves away from the conduction band, and becomes closer to the valence band. So, by applying a negative bias to CNT1 as the gate electrode, the hole

By using plasma-enhanced (PE) nitride as the gate dielectric layer on top of CNT1, the process temperature of the deposition would be high enough (390°C) to simultaneously remove the oxygen atoms from the CNT1 and CNT1/metal interface in the PECVD deposition chamber. Therefore, we can achieve n-type CNT1 channel without extra processing steps [4-6]. For CNT2 as the channel, we adopted PECVD oxide as the passivation layer in this work. The process temperature was around 400°C. Even though this temperature was high enough to desorb oxygen from CNT2, a few oxygen atoms could be driven back to CNT2 during PECVD TEOS oxide process [7,8]. So CNT2 depicts p-type semiconducting characteristics. This is because when the oxygen atoms are reabsorbed during the PECVD oxide process, the Fermi level in CNT2 moves away from the conduction band, and becomes closer to the valence band. So, by applying a negative bias to CNT1 as the gate electrode, the hole