In the previous chapter, the almost linear and continuous work function modulation behavior of Hf-Mo binary alloys is demonstrated. In the view of process integration, a suitable integration technique should be introduced to avoid the process induced gate dielectric integrity degradation.
Here we propose a dual metal gate technology which employs Mo and HfxMo(1-x)
as gate electrodes for p- and n-channel devices, respectively. In this case, the HfxMo(1-x) electrode in the proposed dual metal gate technology is formed by metal intermixing. Metals need not to be removed from the dielectric interface so that the uniformity and integrity of gate dielectric can be preserved. Furthermore, a parameter called the optimal annealing temperature, TA,opt, is expected to provide a prospective work function modulation without causing the EOT variation. The value of TA,opt will strongly affect the application of the proposed technique.
Moreover, since the phenomenon of metal intermixing is based on solid diffusion, we demonstrate that the optimal annealing temperature, TA,opt, can be raised by increasing the total metal thickness (TM = THf + TMo). Consequently, it is likely to
overcome the thermal stability issue in conventional CMOS process by using an appropriate metal thickness. In addition, the composition and work function of HfxMo(1-x) are demonstrated to depend on the thickness combination of metal layers.
At the top surface of the gate electrode, the oxidation of Hf which will lead to an extra Hf consumption was observed. A modified multilayer structure (TiN/Mo/Hf/Mo) was fabricated and verified to improve the immunity to metal oxidation. In addition, a quadratic equation relating the work function (Φm) to composite metal thickness ratio (TR = THf / TMo) is also derived. Good consistency with the experimental data assures the possibility of precise metal work function adjustment.
3.2 EXPERIMENT
Figure 3.1 shows a practicable fabrication process for the proposed dual metal gate technology that uses Mo and HfxMo(1-x) as gate electrodes. After LOCOS isolation and the gate dielectric deposition, the first layer metal Mo and the second layer metal Hf are deposited over the entire wafer. A non-critical lithography step is performed and the second layer metal Hf is then selectively removed from the PMOS side. After gate electrodes patterning and S/D implantation, the thermal annealing is performed for dopant activation and metal intermixing at the NMOS side simultaneously.
To demonstrate this technique, MOSCAP devices were fabricated. The process flow is similar to that of co-sputtering experiment, except that Mo and Hf are deposited in sequence. The Mo gate has been reported to possess high thermal stability (> 1000℃) on SiO2 gate dielectric [1]. Moreover, the work function value of
Mo film varies with the bulk metal microstructure and consequently depends on deposition and annealing conditions [2]. The Mo film with (110) orientation has been reported to maintain possessing high work function value suitable for p-channel devices up to 900℃ [3]. By contrast, the poor thermal stability of pure Hf gate on SiO2 has been reported [4]. Therefore, Mo is used as the first layer metal to retard the unwanted interaction between metal and SiO2 during the subsequent thermal treatment. The composition of binary alloy is modulated by varying the thickness of each metal layer as listed in Table 3.1. The Hf atomic fraction in each HfxMo(1-x) alloy is approximately predicted by
x / (1-x) = 9.38 THf / 13.44 TMo (2.1)
In eq. (2.1), factors of 13.44 and 9.38 are the molar volume of Hf and Mo, respectively. After gate electrode patterning, samples were then subjected to different rapid thermal annealing conditions in N2 ambient to lead to metal intermixing for alloy formation and simulate the possible thermal cycle in the conventional CMOS process.
3.3 RESULTS AND DISCUSSION
Figure 3.2 shows the C-V characteristics of an MOSCAP gated by Hf/Mo metal stack before and after the rapid thermal annealing. The C-V results shows that the nearly optimal annealing temperature (TA,opt) for the 50% sample is 600℃. A sufficient and prospective metal work function modulation can be achieved without the noticeable EOT variation. By contrast, smaller flat band voltage shift for
annealing temperature lower than 600℃ may be due to the insufficient thermal budget needed for expected Hf concentration diffusion to the dielectric interface. As for annealing temperature higher than 600℃, a noticeable capacitance decrease which is different with the observation in co-sputtering experiment can be observed. The abnormal increase in EOT might be attributed to the contribution of series capacitance due to metal oxidation and should be verified further.
In view of process integration, lower TA,opt will restrict the proposed technique to the gate-last process where high temperature annealing for S/D dopant activation will be performed prior to the deposition of gate dielectric and gate electrode. It should be noted that the summation of metal thickness is kept constant (500Å) for each sample as listed in Table 3.1. Since the phenomenon of metal intermixing is based on solid diffusion, the increase of first-layer metal thickness as well as the total metal thickness (TM = THf + TMo) under the same thickness ratio can be expected to raise the required thermal budget for prospective work function modulation. An investigation about the influence of the total metal thickness, TM, on the optimal annealing temperature, TA,opt, is shown in Fig. 3.3. Although the result for sample with total metal thickness of 1500Å is not optimized yet, a positive correlation can be observed.
When the total metal thickness is increased from 500Å to 1500Å, the optimal annealing temperature for the 50% sample is raised from 600 ℃ to 900 ℃ substantially. Consequently, one can possibly get around the thermal stability issue by using an appropriate total metal thickness corresponding to the total thermal budget subsequent to the gate electrode deposition.
According to the ITRS roadmap, however, the thickness of the gate electrode must be reduced with the miniaturization of MOSFET devices. To use thicker metal
thickness, an additional etch-back of the gate electrode would be required after the finish of metal intermixing. The gate electrode thin-down process without serious increase of the process complexity can be possible. For instance, one can employ the interlevel dielectric (ILD) CMP for gate electrode etch-back, and only the polish-time control is needed to achieve a prospective gate electrode thickness as shown in fig. 3.4.
Compared to the gate-last process [5], the dummy gate removal, gate electrode re-deposition and the gate electrode CMP are not required.
The work functions of HfxMo(1-x) formed by metal intermixing are listed in Table 3.1 (optimal annealing temperature: 700℃, 30s for sample 2-1 and 2-2; 600℃, 30s for samples 2-3 and 2-4). The dependence of work function value on the thickness combination of the two metal layers can be observed. Figure 3.5 shows the dependence of post-annealing capacitor-voltage characteristics on the Hf atomic fraction calculated by eq. (2). Figure 3.6 shows the dependence of extracted work function values on the Hf atomic fraction. A parallel shift of post-annealing work functions from the calculated values can be observed. This may be attributed to the extra consumption of Hf (~3%) due to surface oxidation. In Fig. 3.7, the XRD result exhibits the HfO2 peak and demonstrates the speculation. With eq. (1.1) and eq. (2.1), one can obtain the following quadratic equation:
(1.053Φm - 4.136) TR2 + (2.904Φm - 12.808) TR + (2Φm - 9.86) = 0 (2.2)
Here TR is the thickness ratio of Hf to Mo (TR = THf / TMo). If the extra consumption of Hf (~3%) due to surface oxidation is taken into account, the eq. (2.2) becomes:
(1.05Φm - 4.156) TR2 + (2.897Φm - 12.864) TR + (1.995Φm - 9.89) = 0 (2.3)
Figure 3.8 shows the dependence of the work function on the thickness ratio.
Also shown are the calculated results of eq. (2.2) and eq. (2.3). A strong consistency assures the possibility of precise work function tuning since the TR value required for an expected Φm can be precisely determined. Furthermore, to overcome the surface oxidation of Hf, MOS capacitors with triple layer metal stack (Mo/Hf/Mo) capped by TiN (20nm) were also fabricated and subjected to the same annealing conditions in the two-layer experiments. The extracted work function values are labeled in fig. 3.6 and fig.3.8. In the multilayer experiments, the thickness of Mo in the two-layer experiment is split into 10nm as first-layer metal and the remnant Mo is deposited atop Hf. Using the multilayer structure, the immunity against surface oxidation can be improved effectively. The extracted work functions will be recovered to the prospective values and can be described accurately by eq. (2.2).
3.4 SUMMARY
For the ease of process integration, HfxMo(1-x) formed by metal intermixing is evaluated, and a novel dual work function metal gate technology is proposed and demonstrated. One can be allowed to get around the thermal stability issue by using an appropriate metal thickness (TM) and possess precise controllability of metal work function by adjusting the composite metal thickness ratio (TR). This technique is not only attractive but especially important for FinFET and/or UTB-MOSFET devices application.
REFERENCES
[1] R. Beyers, “Thermaldynamic considerations in refractory metal-silicon- oxygen systems,” Journal of Applied Physics, 56(1), pp. 147-152, 1 July 1984.
[2] P. Ranade, Y. C. Yeo, Q. Lu, H. Takeuchi, T-J. King, and C. Hu, “Molybdenum metal gate MOS technology for post-SiO2 gate dielectrics,” in Mat. Res. Soc.
Symp., vol.611, 2000, pp.C3.2.1-C3.2.6.
[3] Pushkar Ranade, Yang-Kyu Choi, Daewon Ha, Aditya Agarwal, Michael Ameen, and Tsu-Jae King, “Tunable work function molybdenum gate technology for FDSOI-CMOS,” in IEDM Tech. Dig., 2002, pp.363-366.
[4] Veena Misra, Greg P. Heuss, and Huicai Zhong, “Use of metal-oxide- semiconductor capacitors to detect interactions of Hf and Zr gate electrodes with SiO2 and ZrO2,” Applied Physics Letters, vol.78, no.26, pp.4166-4168, 25 June 2001.
[5] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G.
Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura,
“High performance metal gate MOSFETs fabricated by CMP for 0.1μm regime,” in IEDM Tech. Dig., 1998, pp.785-788.
Sample TMo (Å) THf (Å) Hf atomic fraction (%) Φm (eV)
ctrl. 500 0 0 (pure Mo) 4.93
2-1 406 94 14 4.81
2-2 294 206 33 4.63
2-3 256 244 40 4.55
2-4 205 295 50 4.43
Table 3.1. Sample conditions and extracted Φm of metal intermixing experiment. (700
℃, 30s for sample 2-1 and 2-2；600℃, 30s for samples 2-3 and 2-4)
Hf
Fig. 3.1. Schematics of dual metal gate technology using metal and alloy formed by metal intermixing. Metals need not to be etched away from the dielectric surface so the uniformity and integrity of gate dielectric can be preserved.
-2 -1 0 1 0.0
5.0x10-11 1.0x10-10 1.5x10-10 2.0x10-10 2.5x10-10
Ca pac itance (F )
Voltage (Volt)
Before M.I.
500C 600C 700C
Sample 2-4 (50%) Hf =295A
Mo = 205A EOT = 49.5A
Fig. 3.2. C-V curves of Hf-295Å/Mo-205Å/SiO2 capacitor before and after thermal annealing. The optimal annealing temperature for this sample was found to be 600℃.
500 600 700 800 900
Fig. 3.3. The increase of total metal thickness under the same composite metal thickness ratio can effectively rise the optimal annealing temperature.
Fig. 3.4. Illustration of thinning down of the gate electrode using ILD CMP.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0
5.0x10-11 1.0x10-10 1.5x10-10 2.0x10-10 2.5x10-10
ctrl. (pure Mo) sample 2-1 (14%) sample 2-2 (33%) sample 2-3 (40%) sample 2-4 (50%)
Ca pacit anc e ( F )
Voltage (Volt)
Fig. 3.5. C-V curves of post-annealing Hf/Mo/SiO2 capacitors as a function of Hf atomic fraction.
0 10 20 30 40 50 60
Fig. 3.6. Comparison between experimental (Table II.) and theoretical results. A parallel shift may be attributed to the extra Hf consumption (~3%) due to surface oxidation. Also shown as open symbols are experimental results of multilayer (TiN/Mo/Hf/Mo) gated devices, good agreement on theoretical results can be achieved.
25 30 35 40 45 50 55 60 65
800C
700C 600C Metal intermixing sample_33% (Hf-206A / Mo-294A)
In te ns ity ( A rb . U ni t)
2 θ (Degree)
HfO2 Mo
Si
As-deposited 500C
Fig. 3.7 XRD spectra of metal intermixing sample (Hf-206Å/Mo-294Å/SiO2) exhibited HfO2 peak as a result of oxidation of Hf at the top surface after thermal treatment.
0.0 0.4 0.8 1.2 1.6 4.2
4.4 4.6 4.8 5.0
Experiment - two layer (Hf/Mo)
Eq. (2.3) - with extra Hf consumption (~3%)
W o rk F u nct io n (e V)
Metal Thickness Ratio, T
REq. (2.2) - no extra Hf consumption Experiment - multilayer (TiN/Mo/Hf/Mo)
Fig. 3.8 Post-annealing work functions extracted from two-layer (Hf/Mo) and multilayer (TiN/Mo/Hf/Mo) gated MOSCAP versus the composite metal thickness ratio (TR = THf / TMo). Also shown are calculated results of derived quadratic equations with and without taking extra Hf consumption into account.
Chapter 4
Novel Dual Metal Gate Technology Using MoSi
xFilms
4.1 BACKGROUNDS AND MOTIVATION
According to the ITRS roadmap [1], the introduction of high-k gate dielectric materials and dual metal gate electrodes with appropriate work functions will be required in the near future to reduce gate leakage current [2]-[4] and eliminate boron penetration and poly depletion effect [4], [5]. For conventional bulk devices, the required work functions (Φm) of n- and p-channel devices are about 4eV and 5eV, respectively. However, the required Φm values for n- and p-channel devices with advanced transistor structures, such as FinFET or ultra-thin-body (UTB) MOSFETs, are about 4.4-4.6eV and 4.8-5.0eV, respectively [6]. Since the work function of the metals cannot easily be modulated, a straightforward dual metal gate CMOS process has been proposed, but it degrades the integrity of the gate dielectric by exposing it to the metal etchant [7].
To preserve the gate dielectric integrity, the first layer metal which is deposited atop the gate dielectric should not be etched away so that the gate dielectric can be protected without exposing to the metal etchant. In this case, the work function of the deposited first layer metal in either NMOS side or PMOS side should be modulated to accomplish the dual work function metal gate technology and provide low and
symmetric threshold voltages for CMOS devices. In addition to the alloy formation mentioned in the previous chapter, the silicidation process may also possess a possibility of metal work function modulation. The straightforward dual work function metal gate technology based on silicides is shown in fig. 4.1. Atop the polysilicon gates, different metals are deposited followed with high temperature annealing to form silicides. The work function values of formed silicides depend on the chosen metal candidates. Unfortunately, most metal silicides are found to possess midgap work function values so that it is difficult to possess large enough work function difference using this approach.
A novel dual metal gate technology based on the full silicidation (FUSI) of polysilicon gates has also been reported [8]-[10] as shown in fig. 4.2. The front end process is the same with the traditional dual-doped polysilicon gates CMOS technology while the conventional salicide process is modified. The metal layer thicker than required for conventional salicide process will be deposited to allow for full silicidation of the polysilicon gates. In this case, dopants in the polysilicon are believed to be responsible for providing the difference between the work functions of n- and p-type metal-silicide (MeSi) gates [11], [12]. Both the source/drain dopant
activation annealing and the silicidation anneaing contribute to the dopant redistribution. The major advantage of the FUSI method is the ease of process integration. Moreover, since the source/drain dopant activation annealing will be performed prior to silicide formation, the requirement for the thermal stability of MeSi can be alleviated. Thermal treatment prior to silicidation process, however, results in the incomplete elimination of boron penetration in p-channel devices [13]. A noticeable boron penetration will take place during the high temperature annealing for S/D activation.
This work proposes the use of a combination of Mo-MoSix gate electrodes for dual metal gate technology. In view of process integration, the MoSix gate was formed by the full silicidation of the α-Si/Mo/gate dielectric stack to prevent the exposure of the gate dielectric in the channel region to metal etchant. Extracted Φm values for MoSix and as-deposited pure Mo gates on SiO2 are appropriate for devices with advanced transistor structures.The small increase in Φm and the negligible variation in EOT after RTA at 950℃ demonstrate the superior thermal stabilities of Mo and MoSix on SiO2. To expand the application of our proposed novel dual metal gate technology, the introduction of n-type metal silicide was also investigated. An additional arsenic pre-implantation prior to silicidation annealing was used for n-type metal silicide formation. Extracted Φm values for n-type MoSix and as-deposited pure Mo gates on SiO2 are found to be suitable for conventional bulk devices. The use of Mo-MoSix gate electrodes combination effectively solves the problems encountered in the FUSI method, and the possessed work function combination can be suitable for devices with advanced transistor structures and conventional bulk devices if additional arsenic pre-implantation prior to silicide annealing was performed.
4.2 EXPERIMENT
Fig. 4.3 schematically depicts the proposed novel dual metal gate technology that combines metal and metal silicide. The first layer metal and α-Si are deposited over the entire wafer in sequence on the gate dielectric. A non-critical lithography step is performed and an appropriate wet etching recipe should be investigated to remove selectively the α-Si from the p-MOS side. Since only Mo remains in the p-MOS region, it solely determines the work function of the p-MOS gate electrode. The
remaining α-Si/Mo stack in the n-MOS region will be subsequently transformed into molybdenum silicide and determine the work function of the n-MOS gate electrode.
In this process, the gate dielectric in the channel region will not be exposed to the metal etchant so the side-effects encountered in the straightforward dual metal gate technology [7] can be prevented.
It is worth to note that the thermal stability of the selected metal film on the gate dielectric should be sufficiently high to ensure that no interaction occurs between metal and the gate dielectric during the silicidation and following high temperature processes. The (110) Mo gate has been reported to have a work function that is appropriate for p-channel device [14], and exhibit high thermal stability (1000℃) on the SiO2 gate dielectric [15]. Accordingly, pure Mo will be adopted as the first layer metal in this work so that the Φm value and the thermal stability of the formed MoSix
become the main issue.
It is also worth to note that the implementation of the proposed novel dual metal gate technology will be more complex than the schematic illustration shown in fig.
4.3. For instance, the re-deposition of Mo in the p-MOS region is needed after the selective removal of α-Si, to equalize the thickness of the gate electrode across the entire wafer. Consequently, potential gate patterning and spacer formation challenges can be prevented. For this reason, a more practical integration process is also proposed as shown in fig. 4.4.
To evaluate the proposed concept, the electrical characteristics of Mo and MoSix
gates were extensively investigated. MOS capacitors with Mo/SiO2/n-Si and α-Si/Mo/SiO2/n-Si structures were fabricated on 6-in Si wafers. After LOCOS isolation, thermal SiO2 (3nm, 6nm, 9nm) was deposited as the gate dielectric.
According to the ITRS roadmap, the thickness of the gate electrode must be reduced as the MOSFET devices are miniaturized. To meet this criterion, a thin (10nm) layer of Mo was sputter-deposited on top of the gate dielectrics for all samples. Some samples were followed by sputter-deposition of α-Si (25nm). Gate electrodes were then patterned by reactive ion etching (RIE) using Cl2-based chemistry. Following gate electrode patterning, some of the samples with an α-Si/Mo/SiO2 stack were then subjected to arsenic implantation (1x1015, 5x1015cm-2). The low implantation energy (10KeV), corresponding to a projected implant range (Rp) value of one half of the thickness of the α-Si layer, was employed to avoid the direct implantation of dopants into the channel region. Samples with an α-Si/Mo/SiO2 stack were then subjected to successive rapid thermal annealing (600℃, 1 min. + 700℃, 1 min. + 800℃, 1 min.) in N2 ambient for MoSix formation. All samples were then subjected to 950℃ RTA for 30s to evaluate the thermal stabilities of gate electrodes. The flat band voltage (VFB) and equivalent oxide thickness (EOT) were extracted from the measured C-V curve using the quantum mechanical C-V (QMCV) simulator [16]. The Φm values of the gate electrodes were then extrapolated from the VFB－EOT plots by setting the electron affinity (χ) of the Si substrate to 4.05eV.
4.3 RESULTS AND DISCUSSION
Before executing the major experiment, a test run for silicidation conditions was performed. MOS capacitors with α-Si/Mo/SiO2/n-Si structures were fabricated on dummy wafers. The thickness of first layer Mo was kept constant as 10nm and the thickness of capped α-Si layer was split into 15nm and 25nm. The successive rapid