Chapter 1 Introduction
1.4 Organization of the Thesis
Two novel dual-work function metal gate technologies are proposed and investigated in this dissertation. First, the dual metal gate technology based on the use of Hf-Mo binary alloys is demonstrated. Second, the silicidation technique is used to implement a dual metal gate technology with metal-metal silicide combination.
In chapter 1, an introduction to the gate candidate evolution and a brief review of state-of-the-art metal gate technologies are discussed. Basic requirements of novel metal candidates are also addressed. Moreover, the used work function extraction technique in this dissertation is also mentioned.
In chapter 2, the electrical and chemical characteristics of Hf-Mo binary alloys are investigated. The continuous and almost linear work function adjustment using HfxMo(1-x) is demonstrated for the first time. The work function value of Hf-Mo binary alloy deposited by co-sputtering ranges from 3.93eV (Φm of pure Hf) to 4.93eV (Φm of pure Mo) and depends on the sputtering power ratio of each target. The thermal stabilities of Hf-Mo binary alloys on SiO2 degrade with the increase of Hf atomic fraction, but all of them possess thermal stabilities at least higher than 400℃.
The Hf-Mo binary alloys can still be suitable for the gate-last SiO2 CMOS process.
In chapter 3, the integration of Hf-Mo binary alloys into dual metal gate technology is proposed. For the ease of process integration, HfxMo(1-x) formed by metal intermixing is evaluated, and a novel dual work function metal gate technology is proposed and demonstrated. One can be allowed to get around the thermal stability issue by using an appropriate metal thickness, and possess precise controllability of metal work function by adjusting the composite metal thickness ratio. This technique is not only attractive but especially important for FinFET and/or UTB-MOSFET applications.
In chapter 4, a novel dual metal gate technology based on silicidation technique is proposed. The α-Si/Mo stack was fabricated and thermal annealed to allow for the formation of MoSix. Combining MoSix with the pure Mo, a practical integration of Mo-MoSix gate combination into dual metal gate technology is also proposed. On the SiO2 gate dielectric, Mo-MoSix combination can possess considerable work function shift and be suitable for devices with advanced transistor structures. The thermal stabilities of pure Mo and MoSix on SiO2 are evaluated to be higher than 950℃.
Moreover, the additional arsenic pre-implantation into the amorphous silicon layer
prior to silicidation annealing is demonstrated to make the application of the proposed novel dual metal gate technology also suitable for the conventional bulk devices. The new structure along with the ruling out of p-type metal silicides can effectively eliminate the boron penetration problem encountered with the FUSI method.
In chapter 5, the proposed dual metal gate technology gated by Mo and MoSix is demonstrated to keep providing the considerable work function shift on the high-k gate dielectric materials. The extracted Φm value of pure Mo or MoSi2 gate on HfO2 is slightly lower than that on SiO2, but the Φm difference between Mo and MoSix is almost the same with that on SiO2 regardless of the underlying gate dielectric materials. The use of arsenic pre-implantation for the modulation of Φm of metal silicide on HfO2 is also demonstrated, even though the modulation range is a little smaller than that on SiO2.
In chapter 6, we conclude our results and summarize the main contributions in this dissertation. Suggestions for further studies are also discussed.
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Fig. 1.1 Illustration of gate misalignment.
Fig. 1.2 Illustration of self-aligned process.
Fig. 1.3 Illustration of polysilicon gate technology using only n+-poly for both n- and p-channel devices.
Fig. 1.4 Illustration of dual-doped polysilicon gate technology.
Fig. 1.5 Illustration of the boron penetration.
Fig. 1.6 Illustration of the poly depletion effect.
Chapter 2
Investigation of Hf
xMo
(1-x)Binary Alloys
2.1 BACKGROUNDS AND MOTIVATION
With the sustained scaling of CMOS technology for device performance improvement, the conventional polysilicon/SiO2 structure keeps suffering a variety of challenges. Novel metal/high-k gate stack has been extensively investigated as a potential solution. The introduction of high-k gate dielectric can effectively reduce the tunneling leakage current due to its larger physical thickness under the same electrical thickness [1, 2]. On the other hand, the inherent drawbacks of polysilicon gates such as poly depletion effect and boron penetration which will lead to an undesired increase of EOT [3] and degrade device performance [4] can be eliminated. In addition, polysilicon gates have been reported to be thermodynamically unstable on many high-k materials [5, 6] so that metals are expected to provide a turning point in possessing better thermal stability and a lower gate resistance for the enhancement of device performance at high frequency.
The major superiority of the traditional polysilicon gate electrode is the ability of Fermi-level adjustment by either donor or acceptor implantation. By contrast, the adjustment of the metal work function is not easily achievable. For bulk devices, the required metal work functions for replacing the conventional n+- and p+- polysilicon gates are about 4eV and 5eV, respectively. On the other hand, for FinFET and/or
ultra-thin-body (UTB) MOSFET devices, the gate-over-channel controllability is enhanced so that the required gate work function for n-channel (p-channel) devices have been increased (reduced) to 4.4~4.6eV (4.8~5.0eV) compared with conventional bulk devices [7]. Since the required work function values for n- and p-channel devices are different in both cases, the dual metal gate technology with suitably chosen metal work function values has been proposed. However, the process integration will lead to the unwanted gate dielectric integrity degradation [8] due to the direct removal of metal from the dielectric surface. It is worth to note that, the adjustment of the substrate doping is no longer an effective way of threshold voltage control in FinFET and/or UTB-MOSFET devices so that the importance of metal gate work function engineering will be more pronounced.
Recently, several metal work function modulation techniques have been widely investigated. The Ru-Ta alloy proposed by H. Zhong et al. can possess the superior thermal stability and a wide work function tuning range [9, 10]. However, the modulation of work function seems not to be continuous. The work function values with interest for advanced transistor structures (4.4-5eV) would be unachievable.
Moreover, the Pt-Ta alloy proposed by B-Y. Tsui et al. has been demonstrated to possess a wide and continuous work function modulation [11], but the issue of gate dielectric integrity degradation mentioned in [8] would be problematic due to the lack of suitable integration methods. Similarly, S. H. Bae et al. proposed that the laminated metal gate stacks HfN/Ti/TaN and Ti/Ta can possess p- and n-MOS compatible work function values (5.1eV and 4.35eV) [12]. However, the process integration of these two distinct laminated metal stacks into dual metal gate CMOS process are still problematic [8]. Otherwise, a novel work function modulation using nitrogen implanted Mo has been proposed by P. Ranade et al. [13]. The major advantage of this
method is the ease of process integration, while the Φm value strongly depends on the implantation parameters and subsequent annealing conditions. A precise work function modulation would not be easily achievable.
In this chapter, the continuous and almost linear work function adjustment using Hf-Mo binary alloys deposited by co-sputtering is demonstrated for the first time. The work function value of Hf-Mo binary alloy deposited by co-sputtering ranges from 3.93eV (Φm of pure Hf) to 4.93eV (Φm of pure Mo). Moreover, thermal stabilities of Hf-Mo binary alloys on SiO2 gate dielectric are also evaluated. Although the thermal stability of HfxMo(1-x) on SiO2 degrades with the increase of Hf atomic fraction, HfxMo(1-x) can still be appropriate for the gate-last SiO2 CMOS process.
2.2 EXPERIMENT
MOSCAP devices were fabricated on p-type (100) 6-in Si wafers and high frequency (1MHz) capacitance-voltage characteristics were measured using an Agilent 4284A precision LCR meter. After LOCOS isolation, SiO2 with different thicknesses were thermally grown at 950℃ to serve as the gate dielectric. HfxMo(1-x)
(~50nm) alloys were then deposited by co-sputtering in Ar ambient. The sputtering power of each target was varied as listed in Table 2.1 to modulate the composition of the deposited binary alloy. The HfxMo(1-x) gate electrodes were then patterned by reactive ion etching (RIE) using Cl2-based chemistry. All samples were then subjected to 400℃ annealing in N2 ambient. The flat-band voltage (VFB) and effective oxide thickness (EOT) of each capacitor were extracted from the measured C-V curve using the quantum mechanical C-V (QMCV) simulator so that one can avoid overestimating
the EOT as well as the metal work function value [14].
2.3 RESULTS AND DISCUSSION
The as-deposited high frequency (1MHz) C-V characteristics of capacitors gated by Hf-Mo binary alloys, pure Mo, and pure Hf films are shown in Fig. 2.1. The negative flat-band voltage shift with the increase of Hf power ratio can be observed.
To eliminate the contribution of oxide fixed charges, C-V measurements of MOSCAP devices with several oxide thicknesses were performed to generate the VFB versus EOT plot as shown in Fig. 2.2. All samples exhibit linear relationships from which work function values of binary alloys can be extracted as listed in Table 2.1.
Figure 2.3 exhibits the (110) morphology for the pure Mo film. The extracted work function value (4.93eV) of the (110) oriented Mo is closely consistent with previous reports [13]. However, the as-deposited Mo with (110) orientation is different from the previous report [15], and this would be attributed to the different deposition conditions. Figure 2.4 exhibits the small the hysteresis for the 50% Hf power ratio co-sputtering sample, which is believed to suffer from the most series sputtering damage. Accordingly, the good process quality can be demonstrated.
The C-V curves of as-deposited and post-400 ℃ sintering pure Hf gated capacitor are shown in Fig. 2.5. Obvious EOT variation along with the VFB shift after annealing illustrates the poor thermal stability of Hf on SiO2 and exclude Hf from gate candidates even in the gate last process [16]. By contrast, HfxMo(1-x) gated capacitors exhibit better thermal stability on SiO2 as shown in Fig. 2.6. The dependence of Φm
and EOT variation on annealing conditions for HfxMo(1-x) also indicates that the thermal stability of all alloy samples can be at least higher than 400℃ as shown in Fig. 2.7.
In Fig. 2.7, the decreases of EOT at certain temperature for alloy samples, except for the one with 25% Hf power ratio, are similar to that for the pure Hf sample. The noticeable EOT decrease and the corresponding work function variation might be attributed to that partial SiO2 gate dielectric was transformed into high-k materials, such as HfO2 or HfSixOy, due to the Hf-SiO2 interaction. For the 25% alloy sample, the abnormal EOT increase along with relative small work function variation can be observed. We speculate that the lower Hf concentration might make the effect of Hf-SiO2 interaction be masked by the extra Si-substrate oxidation due to the oxygen contamination. In the case of sample gated by pure Mo, the small amount of Φm
increase (18meV) and the negligible EOT variation (0.08nm) after 950℃ RTA demonstrate the superior thermal stability of Mo on SiO2 gate dielectric. Although the thermal stability seems to be degraded with the increasing of the Hf atomic fraction in the Hf-Mo binary alloy, HfxMo(1-x) still can be adopted as gate material in a gate-last SiO2 CMOS process. It is worth to note that, alloy samples with Hf power ratio lower than 50% can possess work function value suitable for advanced devices and exhibit thermal stability up to 700℃. In comparison with other reported candidates, the thermal stability of Hf-Mo alloy is lower than that for Ru-Ta alloy [9], but higher than that for Pt-Ta alloy [11].
In 1974, Gelatt and Ehrenreich proposed that the work function of an AxB(1-x)
alloy can be approximately expressed as [17] :
( ) ( ) ( ) ( ) ( )
respectively. ρA and ρB are effective density of states in Fermi level for pure element A and B, respectively. In this equation, the first two terms represent that the work function of the binary alloy is a linear combination of that of each pure element. On the other hand, the last term will lead to a deviation from the linear relationship.According to the theory of heat capacity of metal, the observable Sommerfeld factor γ of a metal is directly proportional to its density of state in Fermi level ρ [18].
The calculated results of eq. (1) are shown in fig. 2.8 where several γ ratios are
The calculated results of eq. (1) are shown in fig. 2.8 where several γ ratios are