In this research, we propose modified FR-Vector model, named FR-Vector with BAM which combined the advantage of FR-Vector - glitch processing in non-zero delay model, and the advantage of Boolean approximation method - the ability of processing correlation among convergent circuit. This model could analyze the switching activities in combinational circuit in probabilistic way with few data.
We have solved the correlation due to temporal dependence (using switching probability) and spatial correlation due to internal spatial dependence (using BAM to solve reconvergent circuit). Though it still has input spatial correlations, we have successively improved the error percentage in each gate from 5.05 to 2.27 and from 6.09 to 2.78 which represents input pattern with glitches and without glitches
respectively. The peak value of error percentage also decreases from 23.74 to 13.24 %.
In time issue, for we use the concept of Taylor expansion to approximate the spatial correlation, we do not need to build OBDD of the whole circuit which adopted in most techniques. Thus, the time spend by FR-Vector with BAM is closed to the original FR-Vector, and compare to the simulation time of NC-VHDL, it could up to 33.73 times faster. Indeed, the larger the circuit is or the more input patterns there is, we will get the more speed-up for the time is depend on the size of circuits.
As mentioned before, there is still something which could be improved in
FR-Vector with BAM, that is, the spatial dependency among inputs. Thought in larger circuit (may be long depth or a big number of gates), the input correlations could only do little affect. But in special case, such as small circuits or circuits with specific input patterns, it still would be a serious problem. For circuits without specific input
patterns, we could simulate them in various input patterns to eliminate the error
caused by input spatial correlations, but for circuits with specific input patterns, we could only find out some way to process the dependency for controlling the error.
Another point could be improved is the way represent signal transition or the way we propagate the BAM data structure. In probabilistic calculation, the most correct consequence would appear when the probabilities in each state are balance.
However, in FR-Vector, the probability of transition F and R would be by far smaller than the probability of transition 1 and 0 in no doubt, and result in an inaccuracy. So we should find a new way to represent the transition probabilities, or we should find a method that could calculate diverge values of probabilities without losing accuracy.
Reference:
[1] Radu Marculescu, Diana Marculescu, and Massoud Pedram, “Probabilistic Model of Dependencies During Switching Activity Analysis”,Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume:
17, Issue: 2, Feb. 1998 Pages:73 – 83.
[2] Farid N. Najm, Member, IEEE,“A survey of Power Estimation Techniques in VLSI Circuit,”Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 2, Issue: 4, Dec. 1994 Pages:446 – 455.
[3] A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, “On average power dissipation and random pattern testability of CMOS combinational logic networks,”
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers, 1992 IEEE/ACM International Conference on, 8-12 Nov. 1992 Pages: 402 – 407.
[4] S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, “Testability Measures in Pseudorandom Testing,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 11 , Issue: 6, June 1992 Pages:794 – 800.
[5] Landy Huang, Zheng-Lun Lin, Chan-Shian Huang, and Chang-Jin Chen,
“FR-vector A new Model for Switching Activity Analysis”, The 14th VLSI Design/ CAD Symposium, Session P2-14.
[6] T. Uchino, F. Minami, T. Mitsuhashi, and N. Goto, “Switching Activity Analysis using Boolean Approximation Method,” Computer-Aided Design, 1995.
ICCAD-95. Digest of Technical Papers, 1995 IEEE/ACM International Conference on, 5-9 Nov. 1995 Pages: 20 – 25.
[7] S. M. Kang, “Accurate Simulation of Power Dissipation in VLSI Circuits”, Solid-State Circuits, IEEE Journal of, Volume: 21, Issue: 5 , Oct 1986 Pages:889 – 891.
[8] Ashok K. Murugavel and N. Ranganathan, “Petri Net Modeling of Gate and Interconnect Delays for Power Estimation”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume: 11, Issue: 5 , Oct. 2003 Pages:921 – 927.
[9] Jose C. Costa, Jose C. Monteiro, and Srinivas Devadas, “Switching Activity Estimation using Limited Depth Reconvergent Path Analysis”, Low Power Electronics and Design, 1997. Proceedings, 1997 International Symposium on, 18-20 Aug. 1997 Pages:184 – 189.
[10] S. Theoharis , G. Theodoridis , D. Soudris, and C. Goutis, A. Thanailakis “A fast and accurate delay dependent method for switching estimation of large combinational circuits,” Computers and Digital Techniques, IEE Proceedings-, Volume: 147, Issue: 6, Nov. 2000 Pages:444 – 450.
[11] Jer Min Jou, Shung-Chih Chen, and Chih-Liang Wang, “Fast delay-dependent power estimation of large combinational circuits” Circuits and Systems, 1998.
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on, Volume:
6, 31 May-3 June 1998 Pages: 53 - 56 vol.6.
[12] Ki-Seok Chung, Tae-Whah Kim, and C.L Lin, “G-vector: a new model for glitch analysis,” ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International, 15-18 Sept. 1999 Pages:159 – 162
[13] C. Ding, C. Tsui, and M. Pedram, “Gate-level power estimation using tagged probabilistic simulation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 17 , Issue: 11 , Nov. 1998 Pages:1099 – 1107.
[14] MCNC, http://www.cbl.ncsu.edu
[15] Tan-Li Chou and Roy. K, “Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 15, Issue:
10 , Oct. 1996 Pages:1257 - 1265.
[16] K. P. Parker and E. J. McCluskey, “Probabilistic treatment of general combinational networks,” IEEE Transactions Comput. on, Volume: C-24, June 1975 Pages: 668-670.
[17] F. Najm, “Transition density, a stochastic measure of activity in digital circuits,”
in 28th ACM/IEEE Design Automation Conference, San Francisco, CA , June 17-21, 1991 Pages:644-649.