The proposed switching activities analyzing method is implemented by JAVA language, for its flexibility to various environment. To prove the accuracy of the proposed method, we compare our method with simulation results and FR-Vector. The former one could tell us the real switching number which would be gotten according to the given input pattern and benchmark, and the latter shows how much we could improve the accuracy than the original FR-Vector. We get the simulation results from the commercial tool, Cadence NC-VHDL 5.0, as a counterpart. All of these experiments are executed in a Linux-x86 computer. We simulate experiments based on 18 combinational circuits from MCNC [14].
In the first experiment, we tested on 18 MCNC benchmark circuits shown in the first column of Table 4.1. We generate 1000 random vectors for all inputs in each benchmark circuits, the frame number of a clock cycle is 20, and every gate delay is 1 frame. The second column in Table 4-1 is the simulated result gotten by NCVHDL , the third to the fourth column is the analysis result from the FR-Vector and FR-Vector with BAM, where the estimated numbers of switching activities in FR-Vector are shown in the third column; the forth column is defined as the error percentage of FR-Vector over NC-VHDL; the estimated numbers of switching activities in our method are shown in the fifth column, and the last column is defined as the error percentage of our method over NC-VHDL . The row “avg” represent the average of the error percentage, and “W-avg” is weighted average which is gotten by equation
“W-avg” shows the average error percentage in gate. Because in normal circuit there
would be no glitch input, thus we control the input generator and make every input pattern to have at most one switching in a clock cycle.
circuit
cm138a 7676 7441 3.06 7441 3.06
cm150a 55311 61587 11.35 56395 1.96
Table 4-1: Switching activity comparisons between NC-VHDL logic simulator, FRM model
In first experiment, we could see that FR-vector improve the accuracy of most circuits. Additionally, in original FR-Vector, the maximum percentage of error happens in “cmb”, which could up to 23.74%. In the same circuit, FR-Vector with BAM improves the accuracy greatly to 13.24 %, and it is the highest one in
FR-Vector with BAM too. As for averages of error percentage, it also decreases from 5.54 to 4.17. Further more, if we consider the “weight-averages” which shows the average error percentage in each gate, they further decrease from 6.09 to 2.78.
Lemma 5.1 The error percentage of FR-Vector over the real simulation is
FR BAM real
where swFR and swreal represent the switching number estimated by FR-Vector and the real switching number,CBAMis the value that BAM correct.
Indeed, considering for signal correlation, we should have:
Lemma 5.2 swFR−dFR+CBAM −dBAM =swreal, where dFRand dBAMis the distance causes by signal correlation.
In FR-Vector with BAM, we wish we could get closer todFR =CBAM. Thus, if we could ignoredBAM, we could getswFR−dFR+CBAM =swreal. However,
indFR =dcon+dinputwheredconis the distance caused by convergent anddinputis the
distance caused by input spatial correlation, BAM could only solvedcon, and
ignoredinput. Even in BAM itself, dBAMwould arise for input spatial correlation too. In
some case, as small circuit for it low distance from input to output, the effect of dinput would be more serious. We could see this phenomenon happens in circuit －
“b1”,”cm42a”, and “cm82a”. Moreover, swFR ≅swreal might happen asdcon
approach todinputoccasionally. Thus, by lemma 5.2 we could know asswFR ≅swreal, the
switching number analyzed by FR-Vector with BAM will
beswFR+CBAM =swreal+CBAM ≠swreal. We could see this phenomenon happens in circuit －”c17”,“cm152”,”cm163a”,”cm42a”, and “cu”.
In the third experiment, we examine the most four complex circuits with 100000 input vectors. The derived CPU time for NC-VHDL simulation, FR-Vector and our methods are listed in Table 4-2 to Table 4-4, respectively. Table 4-5 shows the speed-ups of our estimation method against the NC-VHDL simulation. We could see that the time cost by FR-Vector with BAM is close to FR-Vector but it is by far faster than the simulate result gotten from NC-VHDL.
NC-VHDL(seconds)
1 2 3 4 5 average
c8 62.50 58.30 55.50 56.80 60.40 58.70
cht 30.50 30.30 30.40 30.00 29.90 30.22
count 23.10 23.90 23.60 23.50 22.90 23.40
sct 33.00 32.10 32.60 32.20 32.00 32.38
Table 4-2: The CPU Time for NC-VHDL simulation
FR-Vector(seconds)
1 2 3 4 5 average
c8 1.515 1.437 1.480 1.533 1.521 1.497
cht 1.763 1.703 1.699 1.736 1.740 1.728
count 1.701 1.667 1.724 1.652 1.687 1.686
sct 1.142 1.166 1.162 1.193 1.113 1.155
Table 4-3: The CPU Time for FR-Vector simulation
FR-Vector with BAM(seconds)
1 2 3 4 5 average
c8 1.783 1.750 1.708 1.687 1.773 1.740
cht 1.935 1.955 1.925 1.912 1.947 1.935
count 1.873 1.806 1.865 1.822 1.781 1.829
sct 1.328 1.349 1.341 1.347 1.347 1.342
Inputs Outputs Gates FR FR-
Table 4-5: The comparison with FR-Vector and with NC-VHDL.
Finally, we compare FR-Vector and FR-Vector with BAM with other techniques.
These techniques include the most basic and earliest technique, “signal probability”
[16], and the other technique is “transition density” [17]. However, these two
techniques doesn’t process unexpected transition, glitch. To recover glitches, we use G-Vector [12] to find these unexpected transitions in circuit, and add these glitches with switch number computed by “signal probability” or “transition density” to represent the estimate value. The result is listed in Table 4-6, the experimental result of “signal probability” is in the 7th and the 8th column, and the last two columns is the result of “transition density”. From this experiment, we could see the switch number gotten from “signal probability” and “transition density” is very unaccurat comparing to FR-Vector and our method. This is because “signal probability” try to use signal probability to compute switching numbers in circuit, however the switching activity in circuit could be very different in the same signal probability. “Transition density”
adds the information about how many transition in a time unit to each gate in the circuit, and this information is gotten from the signal probability and transition density of the immediate input of the gate itself. Though it indeed improves the error percentage, it still based on signal probability. In FR-Vector and our method, we use switching probability to analyze switching activity. This conforms to real situation substantially, and this is one of the reasons why we take FR-Vector as out basic model.
#switching #switching error #switching error #switching error #switching error circuit
(logic sim.) (FRM) (FRM)% (F.B) (F.B)% (Sig.+G) (Sig.+G)% (T.D+G) (T.D+G)%
b1 11509 10783 6.31 10504 8.73 8095 29.78 11611 0.89
C17 3768 3718 1.33 3656 2.97 1212 67.83 1887 49.92
c8 151074 158345 4.81 151838 0.51 103180 31.7 177586 17.55
cht 75046 82600 10.07 76205 1.54 52521 30.01 85200 13.53
cm138a 7676 7441 3.06 7441 3.06 5161 32.76 7917 3.14
cm150a 55311 61587 11.35 56395 1.96 32426 41.38 66267 19.81
cm152a 14287 14452 1.15 14597 2.17 10250 28.26 16190 13.32
cm162a 29718 30385 2.24 29947 0.77 19848 33.21 38668 30.12
cm163a 30432 30378 0.18 29505 3.04 15716 48.36 28186 7.38
cm42a 8723 8743 0.23 7829 10.23 8493 2.64 12044 38.07
cm82a 15801 14541 7.97 14021 11.23 9475 40.04 15392 2.59
cm85a 25555 26558 3.92 24953 2.36 18192 28.81 31554 23.47
cmb 17230 21321 23.74 19511 13.24 22019 27.79 35722 107.32
count 53781 51343 4.53 51321 4.57 44798 16.7 72563 34.92
cu 31490 31532 0.13 31033 1.45 30055 4.2 44133 40.15
pm1 32168 34464 7.14 33206 3.23 28665 10.89 41735 29.74
sct 98575 103872 5.37 100568 2.02 70435 28.55 108871 10.44
tcon 27165 28830 6.13 27461 1.09 24979 8.05 33446 23.12
avg 5.54 4.12 28.39 25.86
w-avg 6.09 2.77 27.21 23.94
Table 4-6: Comparison among different technique.