In circuit design, the decreasing of the feature size leads to the increasing of chip density. While the operating frequency growing rapidly and the feature size getting smaller, these factors make the power consumption to be taken into account seriously.
Especially, with the rapid, strong demand development in market sectors such as wireless application, laptop and portable medical devices, it makes the power consumption to be one of the most critical topics in digital system design [1].
Time-to-Market requirement could be achieved by low power design techniques and power estimation methodology. With the aid of power estimation function of CAD tools, it can help designers to meet the power specification earlier in designing phase, and further reduce redesign cost at the same time.
Power consumption in a CMOS circuit can be classified into following three categories:
1. Static leakage power;
2. Short-circuit power;
3. Dynamic power.
In a well-designed circuit, if we don’t consider the special case such as the power lost when portable device is in a dormant state, the total power dissipation cost by the dynamic power consumption of the nodes, which arises due to the charging and discharging of the parasitic capacitance during switching, will by far exceed the first two factors. In [2], the average power consumption at a gate is given byP x( )=0.5V f Cdd2 clk loadsw x( ), whereVdd is the supply voltage, fclk is the clock frequency, Cload is load capacitance, and sw x( ) is the switching activity of the
output node x[2], so we could know sw x is a very important factor in power ( ) estimation.
In power estimation, both speed and accuracy are the most important factors, but obviously, they conflict with each other. The easiest and most direct method of how to estimating power consumption is to simulate the operation of the whole circuit.
However, though this method has the most accurate outcome, it also takes too much time. Today, the techniques of power estimation could be divided into two categories:
dynamic (statistic) and static (probabilistic) [1] [2]. Dynamic techniques explicitly simulate the circuit under a “typical” input stream. These techniques provide a high level of accuracy but it also takes a very high run time which is because the required number of simulation vectors is usually large. Static techniques would calculate the input patterns first, and use a probability to represent a signal state, and then it propagates or calculates these probabilities from the primary inputs to the output of the whole circuit. In final, it uses these probabilities to get the number of switching.
These techniques could provide fast measurement without losing accuracy too much.
Gate delay is an important factor about the accuracy in estimations, but it’s very hard to consider the delays in a circuit. For this reason, many papers tried to ignore the impact caused by gate delays [1] [3] [6][9][10][15].
z Zero delay models: all the gate delays of the circuit are taken as zero.
z Non-zero delay model: each gate delay of the circuit is a positive number or zero. We suppose that non-zero delay model with inertial mode in this paper.
The most important drawback to activities analysis when without considering gate delay is glitch ignoring. However, in non-zero delay model, glitches could happen from the difference of arrival time between two (or more) input signals, and
special cases, like specific adder, the additional consuming power could be up to 70%
[3].
In additional to glitches, another important factor to power estimation techniques is correlations between signals. There might be two kinds of correlations between signals: temporal dependence and spatial dependence.
z Temporal dependency: Signals may be temporally dependent; in other words, the next value of a signal may depend on its current or previous values.
z Spatial dependency: Spatial dependency comes from two aspects:
9 Structure dependency is due to reconvergent fanout in the circuit;
9 Input dependency is that spatial and/or temporal correlations among the input signals which result from the actual input sequence applied to the target circuit.
The input of a counter is an example of dependencies between inputs; Table 1-1 shows the transition of a two-bit counter. In inputC2, the next state is depended on the current state, this is a kind of temporal dependency, and in inputC1, its next state is not just depended on the current state, it would also depend onC2, this is a kind of spatial dependency.
Figure 1-1shows another kind of spatial dependency. In this circuit, the logic value of node m and n are not dependent due to they are diverge node from node b. m and n convergent at node z for a while. For this reason, we should process the correlation between node m and node n to analyze the switching activities in node z precisely.
The aim of this thesis is to propose a modified FR-vector [5]. FR-vector is a model for power consumption which uses probability technique. It could operate under multiple input switching, non-zero gate delay and even glitches happen in a
combinational circuit. We combine the advantages of FR-vector
Current state Next state
C1 C2 C1 C2
1 1 0 0
0 0 0 1
0 1 1 0
1 0 1 1
Table 1-1: The switching state of a 2-bit counter.
Figure 1-1: A simple reconvergent circuit.
and the Boolean Approximation Method (BAM) [6], which is a data structure to process signal correlation ,then propose a new modified FR-vector － FR-vector with BAM.
The rest of this thesis is organized as follows. Chapter 2 introduces some estimation methods and reviews FR-vector and BAM. Chapter 3 describes new modified FR-model. Chapter 4 shows some experimental results. Chapter 5 gives our conclusions and the directions for future development.