Several different transient triggering modes have been proven to be able to initiate TLU [3]-[6], [20], [21], [27]. These transient triggering modes include power-on transition [3], [4], transmission line reflections [5], [6], supply voltage overshoots [20] or undershoots [27], and cable discharge event (CDE) [21]. In most of these transient triggering modes, their corresponding measurement setups have been also developed to evaluate the TLU immunity of CMOS ICs. In addition to these transient triggering modes, a new TLU-triggering mode called system-level electrostatic discharge (ESD) event [28], [29] has been analyzed in this dissertation. These TLU-triggering modes are introduced below.
1.2.1. Power-On Transition [3], [4]
When power-supply voltage ramps up from 0V to its normal circuit operating voltage during the power-on transition, the displacement current will be formed due to the rapid-increasing power-supply voltage. The time-dependent power-supply voltage during the power-on transition is shown in Fig. 1.3. The ramp rate (RA) of the power-supply voltage during the power-on transition can be expressed as
DD
r
RA V
≡ T . (1.1) VDD is the normal circuit operating voltage, and Tr is the rise time of power-supply voltage.
Once RA is above some critical value, TLU will be triggered on by the large enough displacement current that flows through the well/substrate junction capacitance (CWell-Sub) of CMOS ICs, as shown in Fig. 1.4. By applying different ramp rates of the power-supply voltage, the threshold ramp rate to initiate TLU can be evaluated. The susceptibility of this TLU is strongly dependent on the ramp rate of the power-supply voltage, because TLU can occur even if the normal circuit operating voltage is far below the required latchup trigger
voltage in DC latchup I-V characteristic.
1.2.2. Transmission Line Reflections [5], [6]
When the transmission line reflections take place due to impedance mismatch during signal propagation, transient voltage overshoots or undershoots can occur on the I/O pins of CMOS ICs, as shown in Fig. 1.5. Because the I/O pins are directly connected to P+ (N+) diffusions in N-well (P-substrate), such transient voltage overshoots (undershoots) can make the emitter-base junction of the parasitic PNP (NPN) BJT momentarily forward-biased. Once the forward-biased emitter-base junction of one parasitic BJT provides enough diffusion current to turn on the other parasitic BJT, the positive-feedback regeneration mechanism can induce TLU. The techniques to simulate transient voltage overshoots and undershoots on the I/O pins of CMOS ICs are shown in Fig. 1.6(a) and 1.6(b), respectively. The transient voltage overshoots (undershoots) can be simulated by applying a rectangular voltage pulse on the emitter-base junction of parasitic PNP (NPN) BJT in CMOS ICs. Thus, the threshold voltage amplitude and pulse width to initiate TLU can be determined. In general, when the pulse width decreases, the threshold voltage amplitude required to induce TLU will increase.
However, when the pulse width is long enough, a quasi-static situation could be reached. As a result, the threshold voltage amplitude required to induce TLU is approximate to the DC bias (~0.7V) required to turn on the emitter-base junction of the parasitic BJT in CMOS ICs.
1.2.3. Supply Voltage Overshoots/Undershoots [20], [27]
The transient overshoots or undershoots on power-supply voltage can take place due to the noise coupling under system or environment disturbance, as shown in Fig. 1.7. Such transient overshoots or undershoots on power-supply voltage can induce the junction diffusion or displacement current within the CMOS ICs. If the diffusion or displacement current is large enough to activate the parasitic PNP or NPN BJT, TLU can be triggered on and sustained via the regeneration feedback. The techniques to simulate the transient overshoots and undershoots on power-supply voltage are shown in Fig. 1.8(a) and 1.8(b), respectively. The power-supply voltage overshoots (undershoots) can be simulated by applying a positive (negative) rectangular pulse voltage which is superposed on the normal circuit operating voltage (VDD). The positive rectangular pulse voltage can simulate a rapid-increasing power supply voltage, leading to the excitation of transient displacement current. The negative rectangular pulse voltage can simulate a power-supply voltage undershoot with a negative peak voltage, leading to the excitation of P-substrate/N-well
junction diffusion current. Related experimental results show that the threshold voltage amplitude required to initiate TLU will decrease with the pulse width, regardless of positive or negative voltage pulse.
1.2.4. Cable Discharge Event [21]
Large number of charges can accumulate in cables when the un-terminated cables are dragged on the floor (known as triboelectricity). CDE is the phenomenon in which the accumulated charges in cables are discharged into another object in proximity. An example of the CDE event occurring on the Ethernet interface of computer systems is shown in Fig. 1.9.
Once the accumulated static charges in cables are discharged into the I/O pins of the CMOS ICs, TLU can be easily initiated within the CMOS ICs due to the injection of the transient positive or negative current.
CDE-induced TLU is a typical off-chip signal latchup-triggering event, the injection of the CDE-induced current can induce TLU on I/O or internal circuits of CMOS ICs. For the general off-chip signal latchup-triggering events, most CMOS IC products use the EIA/JESD78 latchup test [26] to evaluate the product robustness. Compared with the other off-chip signal latchup-triggering events, however, CDE-induced latchup is a more severe latchup condition because the injection of CDE-induced current can possess peak current of several amperes. Thus, the EIA/JESD78 latchup test standard is unsuitable for evaluations of the CDE-induced latchup robustness, and so far there is no established component-level test standard for CDE-induced latchup. In the state-of-the-art CMOS technologies where the TLU issues are more severe, design methodologies to suppress CDE-induced TLU are necessarily developed.
1.2.5. System-Level ESD Event [28], [29]
ESD is a phenomenon due to the electrostatic charges transferring from one object to another with different electric potentials [30], [31]. Usually, huge transient current or electromagnetic interferences (EMI) accompany ESD phenomenon. In real world, electronic products or systems could malfunction or be damaged when subject to ESD events. Thus, system-level ESD event is an important interference source to evaluate the electromagnetic sustainability (EMS) of electronic products. Thus, for electronic products to satisfy the electromagnetic compatibility (EMC) regulations, system-level ESD test [32] is necessary to evaluate the system-level ESD robustness of electronic products.
An example of the system-level ESD test with direct contact discharge test mode on an
electronic product is shown in Fig. 1.10. Compared with the component-level ESD tests [33], [34] where the objects under test are ICs, the system-level ESD test aims to evaluate the robustness of electronic products. The equivalent circuit of ESD gun used in the system-level ESD test is shown in Fig. 1.11. The ESD gun has the charging (energy-storage) capacitor of 150pF and discharge resistor of 330Ω. The equivalent circuit of human body model (HBM) in the component-level ESD test is shown in Fig. 1.12. In the HBM component-level ESD test, however, the charging capacitor (discharge resistor) is a smaller (larger) value of 100pF (1.5kΩ). Thus, compared with the ESD current in component-level ESD test, ESD current in system-level ESD test has much larger peak current and shorter rise time, leading to more severe damages for electronic products or their interior ICs. Additionally, ESD protection designs for system- and component- level ESD tests are quite different. It has been proven [35] that a robust CMOS IC product with high component-level ESD levels could be very susceptible to the system-level ESD test. Thus, efficient ESD protection methodologies against system-level ESD events are very significant for electronic products.
During the system-level ESD test, the ESD-generated transient current can induce TLU in CMOS ICs within the electronic products, leading to temporary shutdown or permanent damage of the equipment under test (EUT). However, so far there is no literature to clarify the physical mechanism of TLU under the system-level ESD test. Additionally, no component-level measurement setup has been developed to evaluate the TLU immunity of CMOS ICs under the system-level ESD test. Thus, a clear understanding of TLU physical mechanism is necessary to help system or IC designers to solve TLU issues under the system-level ESD test.