This dissertation is composed of seven chapters. This dissertation (chapter 2 ~ chapter 5) focuses on the analysis and characterization of TLU under the system-level ESD test. Several major topics including: (1) clarification of TLU physical mechanism (chapter 2), (2) development of component-level TLU measurement setup (chapter 3), (3) evaluations of board-level noise filters to suppress TLU (chapter 4), (4) and TLU dependency on power-pin damping frequency and damping factor (chapter 5), are discussed in this dissertation. In addition to the TLU topic, latchup is a very significant reliability issue in a high-voltage (HV) CMOS process [36], [37]. Thus, this dissertation (chapter 6) also investigates the dependences of the device structures on latchup immunity in a HV 40-V CMOS process with
drain-extended MOSFETs (DEMOS). Chapter 7 gives the conclusions and future works of this dissertation. The outlines of each chapter are summarized below.
In chapter 2, the physical mechanism of TLU in CMOS ICs under the system-level ESD test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal (bipolar) voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific “sweep-back” current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated in a 0.25-μm CMOS process.
Chapter 3 optimizes an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger. The developed measurement setup can accurately evaluate the immunity of CMOS ICs against TLU under the system-level ESD test. Current-blocking diode and current-limiting resistance, which are generally suggested to be used in TLU measurement setup with bipolar trigger, are investigated for their impacts to both bipolar trigger waveforms and TLU immunity of device under test (DUT). All the experimental results have been successfully verified with device simulation. From the experimental and simulation results, TLU measurement setup without a current-blocking diode but with a small current-limiting resistance is suggested, which can accurately evaluate the TLU immunity of CMOS ICs without over estimation or EOS damage to DUT. The suggested measurement setup has been verified with the SCR test structures and the real circuitry (ring oscillator) fabricated in a 0.25-μm CMOS technology.
In chapter 4, different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under the system-level ESD test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the SCR test structures and the ring oscillator circuit fabricated in a 0.25-μm CMOS technology. Some of such board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products.
In chapter 5, TLU dependency on power-pin damping frequency and damping factor is characterized by device simulation and verified by experimental measurement. Damping frequency and damping factor are two dominant parameters of bipolar transient noises, and they are strongly dependent on the system shielding, board-level noise filter, chip-/board-
level layout, etc. From the simulation results, bipolar trigger waveform with damping frequency of several tens of megahertz can trigger on TLU most easily. However, TLU is less sensitive to bipolar trigger waveform with an excessively large damping factor, an excessively high damping frequency, or an excessively low damping frequency. The simulation results have been experimentally verified with the SCR test structures fabricated in a 0.25-μm CMOS technology.
In chapter 6, the dependence of device structures on latchup immunity in a 0.25-μm HV 40-V CMOS process with DEMOS transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS (n-DEMOS) with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process.
Chapter 7 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter.
Fig. 1.1 Device cross-sectional view of an inverter circuit in CMOS technologies. Two parasitic BJTs are a vertical PNP (Qpnp) and a lateral NPN (Qnpn) BJT.
Fig. 1.2 Equivalent circuit of the parasitic SCR in CMOS technologies.
Fig. 1.3 Time-dependent power-supply voltage during the power-on transition.
Fig. 1.4 Displacement current generated by the rapid-increasing power-supply voltage on the well/substrate junction capacitance (CWell-Sub).
Fig. 1.5 Transient voltage overshoots or undershoots on the I/O pins of CMOS ICs due to the transmission line reflections.
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Fig. 1.6 Techniques to simulate the transient (a) overshoots, and (b) undershoots, on the I/O pins of CMOS ICs.
Fig. 1.7 Transient overshoots or undershoots on the power-supply voltage due to the noise coupling under system or environment disturbance.
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Fig. 1.8 Techniques to simulate the transient (a) overshoots, and (b) undershoots on power-supply voltage of CMOS ICs. VDD is the normal circuit operating voltage.
Fig. 1.9 Example of the CDE event occurring on the Ethernet interface of computer systems.
Fig. 1.10 Example of the system-level ESD test with direct contact discharge test mode on an electronic product.
Fig. 1.11 Equivalent circuit of ESD gun used in the system-level ESD test. The ESD gun has the charging (energy-storage) capacitor of 150pF and discharge resistor of 330Ω.
Fig. 1.12 Equivalent circuit of human body model (HBM) in the component-level ESD test.
The charging capacitor (discharge resistor) is a smaller (larger) value of 100pF (1.5kΩ).