HV Latchup Test Structures

In HV CMOS ICs, latchup can be triggered on due to the inherent existence of the parasitic SCR between n-DEMOS and p-DEMOS. The device cross-sectional view of the inverter logic circuit, which consists of a non-isolated asymmetric n-DEMOS and an isolated asymmetric p-DEMOS, is shown in Fig. 6.4. The parasitic SCR composed of two cross-coupled bipolar junction transistors (BJTs) is also depicted in Fig. 6.4. Such an inverter circuit is the basic logic component in CMOS ICs. It is well known that the parasitic SCR within it, however, is the origin of latchup [15]. Once latchup is triggered on by large enough substrate or well current, a positive feedback mechanism will lead to a large current conducting through a low-impedance path from V_DD (source of p-DEMOS) to GND (source of n-DEMOS). As a result, HV CMOS ICs will malfunction or even be burned out due to the latchup-generated high power.

In this chapter, three different HV SCR test structures (test structures A, B, and C) are used to investigate the dependence of DEMOS device structures on latchup immunity. These three latchup test structures can simulate each possible case of the parasitic SCR in HV CMOS ICs with different DEMOS device structures, including asymmetric, symmetric, non-isolated, and isolated device structures. Table 6.1 summarizes the device structures of DEMOS transistors in test structures A, B, and C. Additionally, layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. All the latchup test structures are fabricated in a 0.25-μm 40-V CMOS process.

The device cross-sectional views and their layout top views of test structures A, B, and C are depicted in Figs. 6.5, 6.6, and 6.7, respectively. The P+ anode (N+ cathode) is used to simulate the P+ source of p-DEMOS (N+ source of n-DEMOS). Once latchup occurs, huge current will conduct from the P+ anode to the N+ cathode. To gain a better latchup immunity, both anode and cathode in test structures A, B, and C are surrounded by their base guard rings

for complying with foundry’s design rules, as shown in Figs. 6.5(b), 6.6(b), and 6.7(b). In addition, the spacing from anode (cathode) to its surrounding guard ring in each test structure is kept at its minimum allowable distance according to foundry’s design rules.

Test structure A is used to simulate the parasitic SCR resulting from the non-isolated asymmetric n-DEMOS and isolated asymmetric p-DEMOS. Due to the “asymmetric” device structures in both p- and n-DEMOS, there is no P-well (N-well) region enclosing the P+

anode (N+ cathode) for source-extended region. In addition, due to the “isolated” device structure in the p-DEMOS, the P+ anode and N+ guard rings are fabricated on the NBL above the P-substrate. However, because of the “non-isolated” device structure in the n-DEMOS, the N+ cathode and P+ guard rings are fabricated on the P-epi. layer instead of NBL. Test structure B is used to simulate the parasitic SCR resulting from the non-isolated symmetric n-DEMOS and isolated symmetric p-DEMOS. Due to the “symmetric” device structures in both p- and n-DEMOS, the P+ anode and N+ cathode are enclosed with the P-well and N-well region, respectively, for the source-extended regions. Test structure C is used to simulate the parasitic SCR resulting from the isolated asymmetric p-DEMOS and n-DEMOS.

Compared with test structures A and B where the n-DEMOS has the “non-isolated” device structure, the n-DEMOS in test structure C has the “isolated” device structure. Thus, the N+

cathode in test structure C is enclosed (i.e. isolated) by the NBL and its peripheral N-well regions, but not only fabricated on the P-epi. layer as in test structures A and B.

6.4. Experimental Results

To investigate the latchup characteristics of DEMOS transistors in HV CMOS ICs, the latchup I-V curves are measured in three different latchup test structures A, B, and C, with various layout parameters. In these test structures, P+ anode and N+ guard rings are connected to VDD, whereas N+ cathode and P+ guard rings are connected to GND. By extracting two dominant parameters of the latchup robustness, latchup trigger voltage and holding voltage, from the measured latchup I-V curves, the dependence of DEMOS device structures and their layout styles on latchup immunity can be well evaluated. Latchup trigger voltage represents the minimum applied voltage that can “trigger” the device under test (DUT) into a latchup state. Latchup holding voltage represents the minimum applied voltage needed for the DUT to “hold” a latchup state. Thus, a higher latchup trigger or holding voltage means a better latchup robustness for the DUT. All the latchup measurements are performed at the room temperature of 25^oC.

Compared with the LV devices, HV devices usually require a much larger minimum-allowable spacing between the adjacent n-DEMOS and p-DEMOS (i.e. much larger anode-to-cathode spacing) because of the ultra-high circuit operating voltage.

According to foundry’s design rule, guard ring structures are also forced for each DEMOS transistor to enhance its latchup robustness. As a result, latchup I-V curves in HV CMOS ICs usually have a much higher holding voltage and holding current (i.e. much higher latchup holding power) than those in LV CMOS ICs. Due to such high latchup power in HV ICs, when the continuous-type curve tracer (e.g. Tektronix 370A) is used to measure the latchup I-V curves in HV ICs, HV devices are usually damaged before the latchup I-V curves are certainly observed or extracted. In order to avoid the HV devices being damaged so easily under the long-period (μs~ms) latchup overstress of continuous-type curve tracer, the TLP generator [62] with a pulse width (rise time) of 100ns (~10ns) is used instead in this chapter to measure latchup I-V curves of HV latchup test structures. Such 100ns-TLP generator is commonly used for ESD characterization. Compared with the general continuous-type curve tracer whose stress time approximates to μs~ms range, the TLP generator has much shorter stress time of 100ns and limited energy. Thus, by using the TLP generator for latchup I-V characterizations, the HV devices will not be damaged so easily under a latchup state, so the latchup trigger and holding voltage can be certainly extracted.

6.4.1. Relationships between Latchup Trigger (Holding) Voltage and Anode-to-Cathode Spacing

The relationships between TLP-measured latchup trigger (holding) voltage and anode-to-cathode spacing for test structures A, B, and C are shown in Fig. 6.8. Obviously, test structure C (considering the parasitic SCR resulting from isolated asymmetric n-DEMOS and p-DEMOS) has the best latchup immunity due to its highest latchup trigger and holding voltage. For example, latchup trigger voltage (holding voltage) can be as high as 97V (48V) for test structure C, even though the anode-to-cathode spacing is only as short as 27.5μm, as its TLP-measured latchup I-V curve shown in Fig. 6.9. Because of a high latchup holding voltage of 48V, which is higher than 40V of the normal circuit operating voltage, the test structure C can be latchup-free. However, latchup trigger voltage (holding voltage) can be only enhanced up to 71V (36V) for test structure A, and 70V (37V) for test structure B, even though the anode-to-cathode spacing is as long as 31.6μm, as their TLP-measured latchup I-V curves shown in Figs. 6.10 and 6.11. For test structures A, B, and C, increasing

anode-to-cathode spacing can improve the latchup immunity. However, it cannot help the test structures A and B to gain a good latchup immunity as in test structure C.

Compared with the test structures A and B which have the traditional four-layer p-n-p-n latchup path, the test structure C has a six-layer p-n-p-n-p-n latchup path due to the isolation region in isolated n-DEMOS. This six-layer latchup path consists of P+ anode, N-well, P-well, NBL, P-well, and N+ cathode in sequence. Due to the isolation region in isolated n-DEMOS, both holes and electrons need to overcome an additional NBL/P-well junction barrier to initiate a positive feedback latchup event. Such unique characteristics will lead to a prominent latchup immunity, i.e. high latchup trigger and holding voltage, in test structure C. In addition, compared with the test structure A, test structure B has a shorter base width in its parasitic vertical pnp and lateral npn BJTs because of the additional source-drift region (i.e. longer emitter width). A shorter base width will lead to a higher current gain of the parasitic BJTs, hence degrading the latchup robustness [15] (i.e. lower latchup trigger and holding voltage) in test structure B. In test structures A and B, however, such difference of the base width is not obvious under a larger anode-to-cathode spacing. As a result, test structure A has a better latchup immunity (i.e. higher latchup trigger and holding voltage) than test structure B under a shorter anode-to-cathode spacing of <25.6μm, as shown in Fig. 6.8. For a larger anode-to-cathode spacing of >25.6μm, however, both test structures A and B have almost the same latchup trigger and holding voltage.

6.4.2. Relationships between Latchup Trigger (Holding) Voltage and Guard Ring Width

Fig. 6.12 shows the relationships between TLP-measured latchup trigger (holding) voltage and guard ring width for test structures A, B, and C with anode-to-cathode spacing (parameter “X”) of 19.6μm, 25.6μm, and 27.5μm, respectively. For test structures A and B, increasing guard ring width can moderately improve the latchup immunity. For example, when guard ring width increases from 0.8μm to 3μm, latchup trigger voltage (holding voltage) can be enhanced from 73V (26V) to 83V (34V) in test structure A, and from 67V (32V) to 74V (35V) in test structure B. For test structure C, however, increasing guard ring width only has little improvement on latchup immunity. Thus, in test structure C, the dominant factor to gain a good latchup immunity is the isolation region of isolated n-DEMOS, but not the guard ring structure.

From the comprehensive experimental results in Figs. 6.8 and 6.12, Table 6.2

summarizes the dependence of DEMOS device structures on latchup robustness. HV ICs with isolated n-DEMOS (test structure C) have much better latchup immunity than those with non-isolated n-DEMOS (test structures A and B). Thus, the isolated n-DEMOS in test structure C is the dominant factor to enhance the latchup robustness in HV ICs. However, symmetric or asymmetric DEMOS in test structures A and B has no great impact to improve the latchup immunity, even though asymmetric DEMOS has better latchup immunity than symmetric DEMOS under a shorter (<25.6μm) anode-to-cathode spacing, as shown in Fig.

6.8. Additionally, increasing both anode-to-cathode spacing and guard ring width can enhance the latchup immunity. However, continuously increasing anode-to-cathode spacing or guard ring width will lead to a larger layout area and higher cost. More importantly, using the isolated n-DEMOS in HV ICs can gain much better latchup robustness than only increasing anode-to-cathode spacing or guard ring width in layout schemes. Thus, using the isolated n-DEMOS in HV ICs can not only gain a good latchup immunity, but can save the total chip layout area.