Charge Pumping Current, I cp (pA)

High Level Gate Voltage, V

gh

(V)

High Level Gate Voltage, V

gh

(V)

C harge Pum p ing Current, I

(nA)

EOT=10.7A

Charge Pumpi ng Current , I

(pA)

High Level Gate Voltage, V

gh

(V)

Charge Pumpi ng Current , I

(pA)

High Level Gate Voltage, V

gh

(V)

25

10 100 1000

6.5x10^-15 7.0x10^-15 7.5x10^-15 8.0x10^-15 8.5x10^-15 9.0x10^-15

Frequency (kHz)

C h a rge R e co mbin ed per Cycl e (I

/F)

EOT=10.7A

Frequency=10k to 1MHz W/L=10/1 um

Fig.3.2 The recombined charge per cycle (Qcp) for the high-k device. The charge-pumping current is seen to increase for lower frequencies indicating that the charge pumping current is the sum of an interface trap component and a bulk trap in high-k dielectric.

26

Beside, at low frequency, nMOS exhibits significantly higher Nt. Such charge trapping in nMOS not only reduces the amount of free carriers in the channel but also serves as additional coulomb scattering centers to lower the electron mobility. Nt of nMOS can be divided into two parts based on its dependence on frequency: one is frequency independent part named as interface traps (N_it), which locates at Si/IL interface next to channel with very short time constant. Another is frequency dependent part, which is referred to as oxide traps (N_hk) of the HfSiON layer. In this thesis, we will separate the influence of the traps in HfSiON from the influence of interface traps on the charge recombined per cycle in a charge-pumping experiment. Since, by varying the charge-pumping frequency we can sense different fractions of the trap density. Therefore, using the above skill and the time constant of the electron trap-to-band tunneling detrapping process, it will help us to obtain the trap density in the HfSiON away from the interfacial layer.

3.4 Depth Profiling of Traps in MOSFET with High-k Gate Dielectric

3.4.1 Basic Theory

According to the model in [24], the extracted depth profile of border traps in the gate dielectric can be calculated by

( ) 1

where A is the gate area, Qcp the charge pumped per cycle, f the measurement frequency, / 2 2

n mn n

λ =h Φ the attenuation coefficient, Φ the potential barrier, and _n m the effective mass of _n electrons. The factor ∆ represents the energy gap in which traps will be allocated by electrons. The E_t rise/fall times of gate pulse in the CP technique of this paper are 10 ns. Such a transient time scans an energy gap of ∆ =E_t 0.8eV[25]. In order to obtain the tunneling distance, x as a function of gate _m frequency was calculated as follows [8], [26]:

27 section, v the thermal velocity, and n the carrier density. Table 3.1 lists the needed constants.

Fig. 3.3 shows the variation in the volume densities of bulk traps (Nhk) along the track of the distance from Si surface. It can be seen that the N_hk density in the native oxide (≈ 1.5–3.7A) varied rapidly near the HfSiON/IL. This is probably caused by the in-complete bonding near the interface [4], [27], [28]. We find a special point (x_m ≈3A) that has the lowest trap density because it is center of IL.

A lot of studies have reported that traps in SiO2 are less than traps in HfSiON can prove above phenomenon. In deeper depth (about 4–6.5 A), a uniform distribution of trap densities about 5*10²⁰/cm³ is observed in the HfSiON bulk layer. This indicates that the bulk trap related reliability issues of high-k gated MOSFETs are the same as the formation of the HfSiON/IL interface.

3.4.2 Investigate Short Channel Effect in H-k Dielectric

Fig.3.4 shows the interfacial traps distribution in short channel and long channel length devices.

Since the mechanical stress in the edge region is more critical than the center region, the interface traps in the edge is larger than that in the center region. The relation can be distribute asN_it,11 ≈ N_it,21,

it,12 it,11

N >> N , N_it,22 >> N_it,21. Fig.3.5(a) shows the trap densities of different channel length devices at varied frequencies. At lower frequencies, C-P measurement senses higher Nt. The flat region, higher frequencies can be as Si/IL interfacial trap density. It is the same as we know that show channel length device has larger interface traps. The Si/IL interface traps of short channel devices (L=0.5 um and L=0.16 um) are more than long channel device (L=1 um). The increase amount of interface traps compared with L=1um are 14% and 20% in L=0.5um and L=0.16um respectively. Than we investigate high-k dielectric traps by N_cp minus N_it, it is the same as above concept. Fig.3.5(b) shows that. Fig.3.6

28

shows depth profiling of dielectric traps in different channel length devices. The lager Nhk occurs in (IL/HfSiON) interface no matter different channel length. And all the points of lowest N_hk are about 3A.

It lets us believe that the point is interfacial layer center.

3.5 Dielectric Degradation Phenomenon in nMOS High-k Devices under Static PBTI Stress

3.5.1 Basic Theory

Bias Temperature Instability (BTI) is a degradation phenomenon in MOS Field Effect Transistors (MOSFETs), known since the late sixties on SiO2 dielectrics. Even though the root causes of the degradation are not yet well understood, it is now commonly admitted that under a constant gate voltage and an elevated temperature a build up of charges occurs either at the interface Si/SiO2 or in the oxide layer leading to the reduction of MOSFET performances.

As a consequence of both the nitridation process step and the use of surface-channel devices, many researchers ascribed an accelerated BTI-like degradation of pMOSFETs under negative bias and elevated temperatures, the so-called NBTI (Negative Bias temperature Instabilities) effect [29], [30].

Unlike SiO₂, the high-K dielectrics such as Hf-based dielectrics present serious instabilities for negative and positive bias, after NBT and PBT (Positive Bias Temperature) stresses. The trapped charges are sufficiently high to represent one of the high-K integration's most critical showstopper. The instability is worrying, especially in the case of nMOS PBTI. In this section we present a review of process optimizations found in the literature. A new experimental methodology is also presented in order to asses with accuracy the real degradation and allows us to argue on possible PBTI mechanisms.

29

Table 3.1 Parameters of constant and physical in depth profiling of traps.

30

3 4 5 6 7

10¹⁹ 10²⁰ 10²¹

HfSiON n-MOSFET W/L=10/1 um EOT=10.7A