High Level Gate Voltage, V

gh

(V) Ch arge P u mp in g C u rrent , I

(n A )

SiO₂ Dielectric NMOS L=10um

W=10um Frequency =1M

Fig.2.9 Charge-pumping measurement in long channel SiO₂ gate dielectric NMOS device.

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Chapter 3

Investigation of the Properties in HfSiON Film

3.1 Introduction

Device scaling is a driving force of semiconductor industry in productivity and performance as predicted by Moor’s law. Nano-scale MOSFET transistor and MOS capacitor have reached their fundamental limits and the introduction of new gate dielectric materials has been surveyed and investigated for a continued scaling. As a trade-off for very short channel device length, ultra-thin and high quality gate oxide is strongly needed. Among them, high-K materials as a gate stack has attracted great interest. Recently, HfSiON has been successfully integrated into CMOS as gate dielectrics for low power applications, with good reliability and comparable mobility.

Threshold voltage (Vt) instability induced by charge trapping has been recognized as one of the critical reliability issue in Hf-based high-k gate dielectrics, especially for nMOSFETs under positive bias stress [16]. In general, a defect band filled with plenty of pre-existing high-k traps is positioned above the Si conduction band edge in energy and in the HfSiON bulk layer in space [17]. In other words, these pre-existing high-k traps are distributed in a wide range of space and energy, thus making the charge trapping model different from that of SiO₂. The high-k traps located at deep energy levels are believed to responsible for the C-V hysteresis or V_t instability determined by static I_D-V_G characteristics [3], [18]. And the high-k traps located at shallow energy levels are indicated as the physical origins of stress-induced leakage current (SILC) in HfSiON/IL high-k gate stacks [19]. In addition, the initial high-k bulk trap density has been demonstrated to be highly associated with the event of dielectric breakdown in HfSiON high-k gate dielectrics, thus influencing the device reliability and yield [15].

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As reported in literatures, Si atoms could be in corporate into the HfSiON high-k gate dielectric to suppress the dielectric re-crystallization during high temperature rapid thermal annealing (RTA) and to reduce the high-k bulk trap density [20], [21]. Moreover, the thickness of base oxide (IL) plays a significant role in the charging and discharging dynamics of threshold voltage instability, and the tunneling time constant decreases exponentially with the decrease of base oxide thickness [22].

Although thin base oxide thickness is preferred for the continuous scaling of equivalent oxide thickness (EOT) below 1.0nm, this may further degrade the problem of threshold voltage instability due to fast charge trapping, Both the composition of high-k bulk layer and base oxide thickness are being modified to obtain the appropriate high-k gate stack structure with required EOT value and reduce threshold voltage instability.

Although, high-k dielectrics increase the physical thickness, the direct tunneling leakage still exists with EOT (equivalent oxide thickness) scaling down to below 16Å. Therefore, the leakage current will induce measurement error for ultra-thin gate dielectrics CMOS devices. To investigate the properties of HfSiON correctly, we need to eliminate the leakage current during the measurement by the IFCP method. The traps in the HfSiON and interface will be evaluated.

3.2 Device Fabrication

The devices used in this work were fabricated using 90nm CMOS technology. Test samples is nMOSFET which has halo implant with SiO₂ and the effective oxide thickness is 10.7Å. Furthermore, both of the high-k films is HfSiON with different halo implant species including light AMU and heavy AMU.

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3.3 Extraction of the Traps in High-K Dielectrics

The technique of charge pumping is frequently used in the study of interface traps by applying a square wave to the gate of the device and measuring the resulting current through the source and drain.

The interface traps charge and discharge with a charge pumping current (ICP) directly proportional to frequency f; however, the charge recombined per cycle (Q_CP = I_CP/f remains the same irrespective of the measurement frequency [10]. In a device, with traps located spatially near Si/IL (interfacial layer) interface, is held in inversion for a period of time longer than the tunneling time constant, then communication may occur between the interface traps and traps in the high-K film. This results in an additional current component and gives rise to an increase of the charge recombined per cycle. In this work, devices fabricated with the HfSiON film are characterized by a high concentration of traps in the high-k film with a well-defined trapping distance, corresponding to the interfacial layer.

Because Icp is proportional to frequency so gate leakage would affect that at lower frequency. In order to gat the accurate product, fig.3.1 shows the lowest (10k Hz) and biggest (1MHz) frequency Charge-Pumping measurements. Fig.3.2 shows the charge pumped per cycle (Qcp) as a function of frequency ranging from 10k Hz to 1MHz. The objective of the latter definition is to eliminate the effects caused by the gate leakage and the tunneling dc currents from source/drain-to-gate overlap [23].

As can be seen in the figure, when the frequency is lower than 500k Hz (this frequency can be regarded as the break-point frequency), Qcp increases clearly with decreasing frequency.

The increase in Q_cp can be attributed to the trap-to-trap tunneling of the border-trapped charges close to the HfSiON/ interfacial layer andHfSiON bulk. As the frequency decreases to 10k Hz and lower, data does not show due to the large derivative disturbance resulted from noise signal.

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High Level Gate Voltage, V

gh

(V)

C harge Pum p ing Current, I

(nA)

EOT=10.7A