Chapter 5 RF T/R Switch
5.3.1 Circuit Design
The schematic of the T/R switch is shown in Figure 5-1. The TX and RX-side switches are nearly identical for extension to multi-pole multi-throw applications. On the RX side, an additional shunt transistor (MRP) improves isolation to the LNA during transmit mode. In this
Figure 5-1. Schematic of the proposed SPDT T/R switch.
mode, the RX node voltage swing is very small. Two transistors are stacked in series (MR1–MR2) to absorb the large voltage swing from the ANT node. Thick-oxide NMOS transistors with a highly isolated body are employed (MR1, MR2, MT1, and MT2). The gate voltages are controlled through large-valued resistors (RG). Thus, the body and gate nodes are AC bootstrapped and follow the drain/source node voltages, reducing the voltage across the drain/source-to-body junctions and drain/source-to-gate oxide. Therefore, power handling capability is improved without breakdown.
The body isolation is a key technique enabling the MOS transistors to handle high power.
In CMOS technology this can be achieved by using a mask which blocks a high dosage P implant. This is sometimes referred to as an “RF block” and used for the implementation of on-chip high-Q inductors. The P region underneath an NMOS transistor is approximately
“isolated” from the global P implant, as shown in Figure 5-2(a). Therefore, the connection of the body to ground is via the P-substrate beneath, which has a higher resistivity of about 80Ω-cm.
An accurate impedance model of the body isolation was created/verified since the P region is still of finite resistance. An EM simulator was used to accomplish this. For this design, the body isolation impedance was analyzed as a two-port network because there are two transistors in series which have body connections to model. The frequency-independent equivalent circuit model is shown in Figure 5-2(b). The values of the elements in this model correlate closely to the geometric parameters in Figure 5-2(a), including the clearance, space, and body area of the P region. It is interesting that a larger clearance doesn’t ensure a higher Rsub: the maximal Rsub
value appears for a clearance close to 100µm in the process we use. By varying the geometric parameters, their optimal values can be obtained as well. The actual geometric optimization also takes die area into account.
The other important performance metric for a T/R switch is the low insertion loss. To achieve less than 1dB insertion loss a very large NMOS transistor is typically required, particularly when a longer gate, thick-oxide device is employed. When these transistors are turned off, their significant parasitic capacitance severely deteriorates the isolation of the switch.
Inductors (LTX, LRX) in parallel with the series transistors are introduced to solve this problem.
clearance P Bodies (P Well) Remotely
Biased Through P Substrate
Figure 5-2. Fulfillment of body isolation technique. (a) Layout of P-bodies for sufficient isolation; (b) Frequency-independent circuit model for parameter extraction.
Therefore, isolation and insertion loss are managed to an acceptable level.
Degraded isolation in RX-mode can also be caused when switch transistors that are off are turned on by a large RF signal. In this case, the source and drain of the transistors are reversed and the large RF signal turns the off transistors on. This can be avoided or postponed by biasing the drain and source terminals to a relatively large voltage (2.5V) while biasing the gates at a low voltage (0V). The control-“ON” voltage is consequently elevated to a higher voltage (5V).
This arrangement also helps to prevent the drain/source-to-body junction from forward biasing, which leads to additional nonlinearity.
At the ANT node there’s an additional shunt inductor, LANT. This inductor improves input/output matching and provides ESD protection. The three tank circuits associated with the three inductors in this switch design were targeted for the same resonance frequency at 5.5GHz.
The switching speed of the T/R switch is set by the gate resistors RG. These were chosen to
Figure 5-3. Transistor inside inductor coil for chip area reuse.
applications. The turn-on/turn-off time is defined as the time from 50% control signal to when the 90%/10% signal power level is achieved. The simulated turn-on/turn-off time are both less than 15ns.
5.3.2 Chip Implementation and Measurement Results
The T/R switch is fabricated in a 90nm, seven metal CMOS process where the NMOS switch transistors coexist in a common P substrate. From the previous section it was mentioned that the isolated-body transistors and the parallel inductors both occupy large chip area but don’t operate simultaneously. Thus, they can share the same chip area in layout as shown in Figure 5-3. The layout of the transistors inside the inductor coils do not form closed loops, which would increase losses from eddy currents and degrade the quality factor of the inductors.
Metal current density is important with a 30dBm signal, which gives rise to a peak current of
Figure 5-4. Micrograph of the fabricated chip under test.
200mA. The current in the resonance tank was also evaluated carefully and considered in the inductor design. Finally, a full-chip EM simulation was performed as part of a post-layout simulation for best accuracy.
A micrograph of the fabricated T/R switch is shown in Figure 5-4. The active die area is approximately 0.5×0.4 mm2. All the performance tests, including insertion loss, isolation, and linearity are conducted with an Agilent E8362B network analyzer. A PA is used for compression testing and the signal power fed into the switch input is calibrated with a power meter. Figure 5-5 shows the insertion loss and the input/output port reflection of the T/R switch.
Each port in the turned-on path in both transmit (TX) and receive (RX) modes is well matched to 50Ω. Figure 5-6 shows the isolation in TX and RX modes. It can be seen that the resonance of the RX switch transistor is approximately 500MHz lower than the deign value of 5.5GHz. The input/output power sweep is shown in Figure 5-7. We speculate that punch-through or other mechanism may be occurring at an input power higher than 29.6dBm. At an input power range of 29.6dBm to 30.3dBm, the output power is relatively constant, which might be caused by
Figure 5-5. Insertion losses in TX and RX modes.
breakdown of the drain-body-source parasitic NPN BJT. The measured input P1dB is 31.8dBm.
The performance of the T/R switch is summarized and compared with other works in Table 5-1.
5.4 Summary
A CMOS T/R switch based on a series-shunt resonant switch structure has been designed
3 4 5 6 7 8
-50 -40 -30 -20 -10 0
Isolation (dB)
Frequency (GHz)
Figure 5-6. Isolation in TX and RX modes.
27 28 29 30 31 32 33 34 35 36 37 26
27 28 29 30 31 32 33 34
Output Power (dBm)
Input Power (dBm)
Figure 5-7. Power sweep test result at 5.6GHz.
and tested at 4.9–6.0GHz. Techniques including stacked transistor, body isolation, parallel inductor resonance, and transistors inside inductor coils have been presented. Body isolation was carefully analyzed with an EM simulator and characterized to obtain the optimal design parameters. Parallel inductor resonance improves isolation and insertion loss. Transistors inside inductor coils are executed to save area without introducing additional losses. 0.9dB insertion loss and 30dBm power handling capability are achieved from 4.9–6.0GHz in a 90nm CMOS process. Measurement results verify the performance and demonstrate the feasibility of integrating a 4.9–6.0GHz T/R switch in a CMOS transceiver chip.
TABLE5-1 PERFORMANCE COMPARISON OF T/RSWITCHES
T/R Switches This Work Xu [41] Talwalkar [44]
Freq. (GHz) 4.9~6.0 0.9 2.4
Operation Mode TX RX TX RX TX RX
Insertion Loss (dB) 0.86 0.82 0.5 1.0 1.5 1.6 Isolation (dB) > 27 > 17 37 29 32 17
Reflection (dB) > 20 > 20 > 12
IP1dB for TX (dBm) 31.8 31.3 28.5
Chip Area (mm2) 0.2 0.11 0.56
CMOS Technology 90nm 0.13µm 0.18µm
Chapter 6
Conclusion & Future Works
In this thesis we successfully developed BSNIM solution for LNA design. As shown in Chapter 3 and 4, the good input matching and noise performances are obtained within low DC power consumption. The device parasitic effects are also well utilized as part of design.
Switching techniques for reconfigurable LNA were developed and verified of very consistent performance among different configurations. The CMOS RF T/R switch project demonstrates the feasibility of high performance RF switch in CMOS process.
The trend of transceiver front-end is to integrate the RF T/R switch with LNA and PA of receiver and transmitter, respectively. As shown [46], we have obtained very promising results of such integration. In the future we expect more and more integration at transceiver front-end with the optimized performance. Low-cost, low-power, and small form factor of transceiver are always the clear and meaningful targets to pursue.
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Vita
Chang-Tsung Fu received the B.S. in communication engineering and M.S. degrees in electrical engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1996 and 2001, respectively. He is currently working toward the Ph.D. degree in National Chiao-Tung University, Hsinchu, Taiwan, with research topic focused on broadband matching theory and techniques for RF front-end circuitry.
In 2006 he worked in Intel Corporation as an intern. His research interests include research and design of integrated circuitry for wireless communication systems.
Publication List
(A) Journal Papers:
(1) Chang-Tsung Fu, Chiun-Lin Ko, Chien-Nan Kuo, and Ying-Zong Juang, “A 2.4–5.4-GHz Wide Tuning-Range CMOS Reconfigurable Low-Noise Amplifier,” IEEE Trans. Microw. Theory Tech., vol.56, no.12, pp.2754-2763, Dec. 2008.
(2) Adil A. Kidwai, Chang-Tsung Fu, Jonathan J. Jenson, and Stewart S. Taylor, “A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11 b/g/n Application in 90nm CMOS Process,” to be published in IEEE J. Solid-State Circuits, May 2009.
(3) Chang-Tsung Fu and Chien-Nan Kuo, “Low Noise Amplifier Design with Dual Reactive Feedback for Broadband Simultaneous Noise and Impedance Matching,” submitted to IEEE Trans. Microw. Theory Tech.
(B) Conference Papers:
(1) Chang-Tsung Fu, Stewart S. Taylor, and Chien-Nan Kuo, “A 5-GHz, 30-dBm, 0.9-dB Insertion Loss Single-Pole Double-Throw T/R Switch in 90nm CMOS,”
IEEE RFIC Symp. Dig., 2008, pp. 317-320.
(2) Adil A. Kidwai, Chang-Tsung Fu, Ram Sadhwani, Chi Chu, Jonathan C. Jensen, and Stewart S. Taylor, “An ultra-low insertion loss T/R switch integrated with 802.11b/g/n receiver in 90nm CMOS,” IEEE RFIC Symp. Dig. 2008, pp.
313-316.
(3) Chang-Tsung Fu, Chiun-Lin Ko, and Chien-Nan Kuo, “A 2.4 to 5.4 GHz low power CMOS reconfigurable LNA for multistandard wireless receiver,” IEEE RFIC Symp. Dig., 2007, pp. 65-68.
(4) Chun-Hsing Li, Chang-Tsung Fu, Tzu-Yuan Chao, Chien-Nan Kuo, Y.-T. Cheng, and D.-C. Chang, “Broadband Flip-Chip Interconnects for Millimeter-Wave Si-Carrier System-on-Package,” IEEE MTT-S Int. Microwave Symp. Dig. 2007, pp. 1645-1648.
(5) Chang-Tsung Fu and Chien-Nan Kuo, “3~11-GHz CMOS UWB LNA using dual feedback for broadband matching,” IEEE RFIC Symp. Dig., 2006, pp.67–70.
(C) Issued Patents:
(1) US 7,339,436
“Ultra broad-band low noise amplifier utilizing dual feedback technique”
Inventors: Chang-Tsung Fu and Chien-Nan Kuo.
(D) Pre‐granted Patents:
(1) US 20080272824
“CMOS RF switch for high-performance radio systems”
Inventors: Chang-Tsung Fu and Stewart S. Taylor.
(2) US 20090021295
“Dual reactive shunt low noise amplifier”
Inventors: Chang-Tsung Fu and Stewart S. Taylor.
(3) US 20090029654
“Using radio frequency transmit/receive switches in radio frequency communications,”
Inventors: Chang-Tsung Fu, Adil A. Kidwai, Stewart S. Taylor, and Jonathan J.
Jenson.