Chip Implementation

In chip implementation non-ideal factors must be taken into account. Simplified simulation models of inductive devices are built with the EM simulation results. We utilized the optimization utility of Agilent ADS to find the optimal structure, dimension, and parameters for real devices. The practical parameters of the transformer, including Lg, Ld and M, are 1.4nH, 2.6nH and 0.35nH respectively. The circuit floor plan is well arranged to minimize lengths of extra interconnect lines. For those transistors not connected to ground at the source node, a bias resistor of large value is placed in between the source and the body nodes to minimize body effect. Fabricated in 0.18um CMOS process this prototype chip consumes 9mW from a 1.5V power supply. The power consumption of the output buffer stage is not taken into account.

The chip micrograph is shown in Figure 3-4. The parasitic shunt capacitance of the coupling capacitor CC in Figure 3-1 is utilized as the C1 of the matching network. Figures 3-5 to 3-7 show the measurement results. Also included are the post-layout simulation results with the transistor

Figure 3-4. Chip micrograph of the fabricated UWB LNA.

1 2 3 4 5 6 7 8 9 10 11 12 13 Figure 3-6. Measured and simulated S21.

3 4 5 6 7 8 9 10 11 12

Figure 3-7. Measured and simulated noise figure and NFmin.

parameters were measured with ATN NP-5 noise parameter analysis system. Figure 3-5 shows the measured S11 and Sopt. Both of them have good in-band matching to 50Ω. Figure 3-6 shows the power gain S21. The measured S21 meets the simulated result with the model in the SS corner, but is about 5-dB lower than that in the typical-typical (TT) corner. The noise figure (NF) and the circuit minimum noise figure (NFmin) are shown in Figure 3-7, in which NF is very close to the NFmin in the pass band. The measured in-band noise figure is less than 5dB. The measured NFmin higher than the simulated one is due to the degraded power gain. If a 1.8V instead of 1.5V is applied as supply voltage, it achieves < 4dB NF with less than 20mW DC power consumption.

The measured IIP3 is about -12dBm. The linearity performance is degraded by the voltage gain of the first stage driving the gate of M2 (Figure 3-1), such that the nonlinear effect of M2 is magnified. The performance is summarized and compared with other UWB LNAs in Table 3-2.

The simulation and the measurement results successfully validated the proposed BSNIM solution.

3.4 Summary

A LNA architecture using capacitive feedback and series-series transformer feedback simultaneously for broadband purpose is reported. In experimental results the function of broadband simultaneous noise and impedance matching is proven. This design not only lowers the noise figure but also provides flat high gain throughout the UWB band. With the utilization of weakly coupled transformer the chip size is slimmed down dramatically. This design well utilized those device parasitic effects such as transistor gate-to-drain capacitance (Cgd) and the shunt capacitance of coupling capacitor (C1) as part of design.

Chapter 4   

Reconfigurable LNA for   Multi­Standard Receiver 

4.1 Introduction

As more and more wireless applications have come into people’s life for better convenience, many communication standards are widely used currently. For roaming among different access technologies including cellular network, personal area network (PAN), wireless local area network (WLAN) and the upcoming wireless metropolitan area network (WiMAX), there rises strong motivation on using a single radio system to support multi-bands and multi-standards to lower the hardware cost and enable wireless access anywhere and anytime.

As such, it is highly expected that a transceiver is reconfigurable in specification accommodating different standards. Such specifications for a receiver RF front-end include carrier frequency, bandwidth, voltage gain, noise figure, and linearity. Moreover, the power consumption shall be controllable accordingly.

In such a multistandard RF system, one of the most critical issues is a large dynamic range to cover various needs of different standards. Among sub-blocks of a reconfigurable receiver front-end, the low-noise amplifier (LNA) is the most difficult part to design as it is expected to provide good input impedance matching, high voltage gain and low noise figure in dynamically specified frequency bands. Figure 4-1 shows the spectra of Bluetooth, Wireless LAN (802.11a/b/g), multiband ultra-wideband (MB-UWB), and WiMAX (802.16e), which are the standards of interest in this project. To accommodate such diversified frequency specifications, the frequency operation of a reconfigurable LNA can be in either concurrent multiband or tunable single band. To date there are several approaches for concurrent multiband operation.

First proposed in 2002, an LNA utilizes dual-band LC-networks to provide concurrent dual-band input matching and output gain response [26]. This approach becomes cumbersome when handling multiple bands. The more adequate solution is a broadband design with comprehensive band coverage. Numerous broadband LNA design techniques have been developed by applying the input LC band-pass filtering [7], [23], the dual reactive feedback [8], the resistive/ source-follower feedback [19]–[22], and the common-gate topologies [27]. In compare with the tunable single band approach, the broadband input matching avoids the use of tunable devices in input network that easily degrades noise performance. The broadband gain response, however, is unfavorable because it allows undesired interferers to pass through such that stringent linearity is required in the succeeding stages (e.g., mixer). As such, a tunable

Figure 4-1. Spectra of Bluetooth, WLAN, MB-UWB mode-1 and WiMAX.

single band gain response is preferred for out-of-band interferer suppression [28], [29].

Besides the frequency issues, the trade-off between LNA performances can be outlined by the performance matrix as shown in Figure 4-2, giving insight for performance reconfiguration.

Typically the higher gain provides the lower noise figure, whereas the lower gain brings the better linearity. Power consumption further affects the circuit dynamic range⁴. If higher performance of a larger dynamic range is in need, the LNA shall be configured to consume more power to meet the requirement. For example, a large dynamic range demanding both low noise figure and high linearity is required in the ultra-wideband (UWB) system, whereas the low power consumption is of the primary concern in Bluetooth connection. Techniques including bias control, current steering, feedback switching, and attenuation switching can be used for gain control [30], [31].

This chapter proposes a wide-tuning-range, performance-reconfigurable LNA. It consists of two stages featuring broadband input matching and low noise amplification at the first stage,

Figure 4-2. The performance matrix for reconfiguration of LNA. In this work the three corner states of low power and middle power are pursued.

and a wide-tuning-range band-limited gain response with adjustable performance at the second stage. The 0.13um technology CMOS LNA is designed to operate from 2.4- to 5.4-GHz. A new inductor switching configuration provides wide-range frequency tuning while gain and noise figure are maintained at the same level. With bias control and transistor size switching, performance is reconfigurable to approach the lower left three corner states as shown in Figure 4-2.

4.2 General Considerations on the Proposed Reconfigurable LNA

Figure 4-3 shows a possible receiver front-end architecture for multistandard radio. The LNA, local oscillator and low-pass filter are controlled digitally for different specifications by the digital control unit referring to a parameter look-up table. The receiver allows the signal of interest to pass through the receiving path, while the others turn into spurious noise to be

Figure 4-3. Reconfigurable receiver front-end architecture.

excluded. To alleviate the issue of broadband noise, the LNA is reconfigurable to meet the required circuit performance at the tuned operating frequency over the specified 3GHz frequency range. The dashed box in Figure 4-3 shows a two-stage LNA solution pursued in this work. Circuit property is fixed at the first stage, which provides broadband responses of input impedance matching, high voltage gain and low noise figure. This stage is set to have high voltage gain so as to achieve better system noise performance with low power consumption.

Frequency tuning function is implemented at the second stage, which also provides variable gain/ linearity control to enhance the dynamic range.

In general coarse tuning functions are realized using switching components controlled by open-loop digital control signals, while fine and continuous tuning using analog control signals available in current mode generated by simple low-speed digital-to-analog converters (DACs).

All the digital control signals and DAC inputs refer to a look-up table which is obtained from calibration process

While the two-stage LNA as shown in Figure 4-3 is employed, the non-linearity of the broadband stage actually introduces more inter-modulation distortions (IMDs) than a regular narrowband LNA – it generates IMDs from all the passed signals. And in addition to the odd-order IMDs, the even-order IMDs emerges when the fractional bandwidth is larger than 2.

Signal at frequency f0 will be interfered by the second- or third-order inter-modulation of strong signals at frequency f1 and f2 if f0 = |f1 ± f2|, (2f1–f2) or (2f2–f1). Examples of such frequency

2.4 2.6 3.432 3.960 4.488 5.15 5.35

Freq.

(GHz)

WLAN (802.11a) WiMAX signals

@2.6GHz

IM2

Figure 4-4. An exemplary case of IM2 interference.

combinations include {f0, f1, f2}={2.48, 2.68, 5.16} for the 2nd-order IMD (IM2), and {2.42, 2.54, 2.66} and {5.16, 3.79, 2.42} for the 3rd-order IMD (IM3), all in the unit of GHz. Figure 4-4 shows the IM2 from the two blockers around 2.6GHz landing at 5.2GHz as an example.

When operating at 5.2GHz, the band selective second stage of the LNA cannot filter out the IM2

from 2.6GHz blockers at all. And in most design case, the power level of IM2 is larger than IM3

with the same blocker power level.

The even-order IMD in general can be minimized with a fully differential circuit structure.

However when a single-in differential-out receiver frontend is considered with the inclusion of a broadband active BALUN after the single-end LNA, the even-order IMD is not ignorable and should be taken into account in the design.

4.3 A 2.4 – 5.4GHz Wide Tuning range Performance Reconfigurable LNA

The schematic of the proposed reconfigurable LNA is as shown in Figure 4-5. The first stage is a broadband amplifier with dual-reactive feedback, based on the BSNIM amplifier described in chapter 2. The second stage is a cascode amplifier providing gain, linearity, and wide-range frequency tuning. The output buffer stage is for measurement purpose. The parameters of key devices are listed in Table 4-1 and the design concepts of the first and the second stages are detailed as follows.

4.3.1 Broadband Amplifier with Controllable Output DC Level

The first stage employs the BSNIM amplifier described in Chapter 2. In this project this stage is designed for the entire 2–6 GHz frequency band. The input impedance matching is designed having less thn -15dB input reflection and the noise figure is very close to NFmin in this wide frequency range. The voltage gain is about 15dB. As the design result, the simulated frequency responses of voltage gain and noise figure of the first stage are shown in Figure 4-6.

Figure 4-5. The proposed reconfigurable LNA.

TABLE4-1

D^EVICE VALUES OF THE D^ESIGNED RECONFIGURABLE LNA

Transistor M1N M1P M2a M2b M2c M3 M4

Width (µm)

(Length:0.13µm) 120 120 10 20 40 60 30

Device Cp1 Lp1 Cc1&Cc2 Lg Ld k CX

Value 460fF 4.9nH 2.7pF 3.2nH 4.9nH 0.17 240–510fF Note: The inductance of the switching inductor LX is as shown in Figure 4-16.

The biasing of M1N and M1P is separated to provide a controllable output DC level to bias transistor M2, conducting the performance reconfiguration at the second stage. The DC level, Vba, is clamped equal to a reference voltage Vba_ref by a DC feedback loop, including M1P and an OP-Amp. The M1P itself provides a 24dB DC voltage gain and the OPAmp, consuming less than 80μW power, has 37dB voltage gain. Thus the gate voltage of M1P, Vbp, varies within 12.5mV for the demanded 200mV DC dynamic range of Vba, introducing just marginal impact on input matching and noise performance of the first stage. Meanwhile the error between Vba and Vba_ref is less than 0.2mV. In a fully integrated receiver, the Vba_ref and the M1N bias voltage Vbn can be configured by a current-mode DAC and a constant-gm bias circuit, respectively. In this prototype both of them are driven externally for laboratory test purpose.

4.3.2 Performance Reconfiguration by Switching Transistor

Performance reconfiguration is realized by the common-source amplifier (M2) at the second stage, including gain and linearity control. The noise figure is generally correlated to the gain level; that is, higher gain brings a lower noise figure. The design target is implementation of three operation modes, one in high-gain (HG) and two in low-gain (LG1 and LG2). Gain difference of at least 10-dB is expected between the high-gain and the low-gain modes. Besides,

Figure 4-6. Voltage gain and noise figure of the first stage in simulation result.

this LNA exhibits an improved linearity in LG1 mode while the even lower power consumption is achieved with degraded linearity in LG2 mode.

Being the transconductor of the cascode amplifier at the second stage, M2 is found to be the linearity bottleneck of this LNA. Its transconductance gm is the primary nonlinearity source as M2 is loaded by a common-gate stage of low input impedance [32]. Hence linearity control mainly relies on M2 gate biasing. Linearity performance can be inspected by the 2nd and the 3rd input interception point voltages, VIIP2 and VIIP3, as

2

Where the gm' and the gm″ are the first and the second derivative of gm, respectively.

Because M2 receives very wideband input, the second-order distortion is found as critical as the third-order in some application cases. Transistor linearity is characterized by the simulated results of gm, gm'/gm, and g " g vs. V_m / _{m gs}, as plotted in Figure 4-7. As can be seen, larger Vgs

gives higher gain gm, better VIIP2, and larger drain current, while VIIP3 varies insignificantly. The second-order distortion is chosen as the primary linearity index to be improved in this LNA.

The actual design is according to Figure 4-7. Gate bias is first chosen corresponding to different linearity performances in each operation mode. Then the transistor size is set regarding to gain requirement. The design result is summarized in Table 4-2. The 12dB stepping difference is produced on gm and gm'/gm between the HG and the LG1 modes. In practice the drain current IDS, instead of Vgs, is controlled to alleviate the impact of process

As shown in Figure 4-5, the M2 transistor actually consists of three transistors, M2a, M2b

and M2c, with the size ratio of 1:2:4. Transistors M2b and M2c are switched on and off by the switches at their source nodes. This allows larger switch size for smaller on-resistance. The input capacitance of M2 should not be changed significantly by size switching as it is an important parameter for LNA input matching, which is expected to be similar among all considered configurations. For the sake of this, the source nodes of M2b and M2c are AC

Figure 4-7. Simulated gm'/gm and gm of transistor M2 in response to Vgs under different gain modes.

TABLE4-2

DESIGN PARAMETERS AND PERFORMANCE IN EACH OPERATION MODE

Mode VGS SIZE IDS *GM *GM′/GM

HG 0.56V 7x 2.0mA 0dB 0dB

LG1 0.71V 1x 1.0mA -12dB -12dB

LG2 0.51V 3x 0.5mA -12dB +4dB

* The gm and gm′/gm are normalized to their values in HG mode.

bypassed to ground to alleviate the impact of switching to the input capacitance.

Switching transistor M2 controls the voltage gain and linearity, as well as the power consumption. Compared to the conventional current steering variable-gain schemes in which gain is adjusted by the common-gate transistor M3, our approach is more power-efficient because at lower gain the LNA requires smaller drain current.

4.3.3 Frequency Tuning by Switching Inductor and Varactor

Band-selective filtering is provided by an LC resonance tank at the second stage as shown in Figure 4-5. The resonator consists of a multi-tapped switching inductor and two on-chip varactors. The former provides coarse frequency stepping, while the latter is for fine tuning.

Coarse frequency stepping is realized by switching control of tapping points so as to obtain different inductances, yielding to several sub-bands. This LC tank is demanded to be tunable over the entire frequency range of interest. Meanwhile it shall provide a quite consistent voltage gain for each tuned band. This calls for the quality factor requirement of the switching inductor as described as follows.

The resonator tank can be generally represented by an equivalent circuit as shown in Figure 4-8(a), in which the inductance is switchable and the capacitance is tunable. The resistance RS in series to inductor LS includes the inductor parasitic resistance and the switch on-resistance, and dominates the quality factor of this tank. As the inductance LS is changed by turning on distinct switches, the RS value can actually be changed accordingly. To get the insight to achieve the aforementioned gain consistency requirement, the resonator circuit is transformed to the parallel RLC tank in Figure 4-8(b), with the equivalent parallel inductance and resistance derived respectively as

⎟⎟⎠

is the resonance frequency as

2

The 3-dB bandwidth, BW, of this resonance tank is

S

At resonance the voltage gain of this circuit can be expressed as

(a) (b)

Figure 4-8. Wide continuous frequency tuning by adjusting both the inductor and capacitor: (a) Practical circuitry; (b) Equivalent parallel resonance tank.

v out / in m P

A =V V =G R . (4-7)

The design guideline is revealed from these equations. Given the typical condition of a flat Gm response over the frequency range of interest, the voltage gain consistency fully corresponds to the frequency dependency of RP. In discussion of the fine capacitance tuning, the switching inductor is assumed frozen with a fixed inductance. As CP ∝1/ω02, it leads to the frequency dependency of QL for consistent RP from (4-4) as

1 0−

∝ω

QL . (4-8)

This condition can be partially met by a practical inductor, of which quality factor Q declines in the frequency region higher than the peak-Q frequency. Note that a consistent BW calls for the condition of QL ∝ ω0 by (4-6), opposite to (4-8). For LNA the consistency on voltage gain is more important than bandwidth so the design generally follows (4-8).

Nevertheless the bandwidth variation is still acceptable if the frequency range of each sub-band remains small enough.

The condition for consistent RP among coarse inductance stepping can also be obtained from (4-4), by freezing the tuning of CP, as

Figure 4-9. Quality factor profile of switching inductor as required for good voltage gain consistency.

0

.

S L

S

L

Q const

ω ⁼ R ^≈ (4-9)

That is, when inductance LS is switched smaller for a higher resonance frequency, the corresponding quality factor of switching inductor should be proportionally higher, which necessitates a smaller Rs. In general this can be fulfilled by design of the switch on-resistance for each inductance.

Combination of the conditions in (4-8) and (4-9) gives the quality factor requirement of the switching inductor as the profile shown in Figure 4-9. In practical implementation of the on-chip switching inductor, the rule of (4-9) is actually difficult to realize because it demands an unacceptable large switch transistor for the smallest inductance. To overcome this difficulty, an alternative switching configuration for the inductor is proposed, as discussed in the next section.

4.4 Multi-Tapped Switching Inductor

4.4.1 Inductor Switching Configuration

The basic idea of inductor switching is to enable or disable sections of inductor coils to obtain different inductance values. The conventional switching configuration for a multi-tapped inductor is shown in Figure 4-10(a) [33], [34]. Both ends of the coil are directly connected to the application circuit at the nodes a and b. Switches are attached to the tapping nodes, of which one can be turned on to bypass the remaining coils. The switch on-resistance is known to degrade the inductor quality factor. The degradation becomes worse in a spiral configuration that all the coil sections are winded together with magnetic mutual coupling. This coupling magnifies the degrading effect of switch on-resistance. An alternative switching configuration

is proposed as shown in Figure 4-10(b), in which an additional switch is attached at the end

is proposed as shown in Figure 4-10(b), in which an additional switch is attached at the end