Thesis Organization

In Chapter 2 the complete theory of broadband simultaneous noise and impedance matching is developed. In the beginning the channel thermal noise of a MOS transistor in deep sub-micron is reviewed. Then the key factors affecting the noise performance of a common-source amplifier is discussed. According to the derived theory, the optimal condition of broadband simultaneous noise and impedance matching (BSNIM) for LNA is developed.

A dual reactive feedback composing of a shunt capacitive feedback and a series inductive feedback was invented. Three inductors in the topology were further refined into a transformer feedback form, which occupies only one transformer area and reduce the form factor.

In Chapter 3, a 3–11-GHz UWB LNA utilizing the BSNIM technique of LC-ladder matching and dual reactive feedback was developed and silicon verified in TSMC 0.18um CMOS process. It demonstrates a good broadband noise performance (< 5dB NF) over the entire pass band, while only 9mW DC power is consumed.

A 2.4–5.4-GHz reconfigurable LNA for multi-standard purpose was developed in TSMC 0.13um CMOS process, detailed in Chapter 4. The switching of transistor and inductor provide reconfigurable performance and operation frequency, respectively. New inductor switching technique was proposed utilizing switch parasitic capacitance to boost inductor quality factor at high frequency. The tuning range limitation is analyzed and the design guideline is developed.

The noise figure is less than 3.1dB (high gain mode) for all the frequency options, while a less than 5mW DC power is consumed.

A 4.9–6.0-GHz T/R switch was developed as shown in Chapter 5. By utilizing body isolation technique the CMOS switch can handle RF power over +30dBm. Inductor in parallel improves switch isolation in OFF state. The ON-state insertion loss is 0.9dB, of the same order

as GaAs switch. Switch transistors are placed inside inductor coil to save area.

Chapter 2   

Theory of Broadband Simultaneous   Noise and Impedance Matching  

for Low Noise Amplifier Design 

2.1 Introduction

A low noise amplifier (LNA) is an essential component at receiver input for wireless communication. It is expected having a high gain with a low noise figure to provide a sufficient signal-to-noise ratio for signal demodulation. Among various MOSFET LNA circuit topologies, the common-source (CS) based amplifier is generally preferred as it performs better noise performance within limited power consumption. It is especially popular for extreme applications in which ultra low power or very high frequency is demanded.

To exploit the best noise performance from a CS amplifier, the optimal design condition of simultaneous noise and impedance matching (SNIM) should be achieved to reach the minimum noise factor (Fmin) a transistor can provide, while keeping a low voltage standing wave ratio (VSWR) at the input [3], [4]. It’s a condition that the input impedance (Zin) and the conjugate of the noise optimized source impedance (Zopt*) of a CS amplifier are simultaneously conjugate matched to an impedance ZS, and then matched to the source impedance Z0 by a lossless matching network, as shown in Figure 2-1. As such, the amplifier noise figure approaches to the minimum level. Typically the SNIM condition can occur with a feedback technique. A widely used one for narrowband LNA design is a CS amplifier with inductive source degeneration, which has been well analyzed [1], [5], [6]. In those papers the induced gate noise of a MOS transistor was emphasized as the root cause of mismatch between Zin and Zopt*. Because the frequency dependency of the derived Zopt is different from that of Zin, broadband SNIM (BSNIM) is not feasible using that technique. This is observed in the broadband amplifier

Noise Figure (dB)

Figure 2-1. SNIM approaching for a common-source LNA.

realized by employing a multi-order LC matching network [7], of which noise performance is still band-limited. In 2006, two UWB LNAs utilizing distinct transformer feedback structures were reported [8], [9], both showing broadband noise performance. In [8] we demonstrated the first BSNIM LNA by employing dual reactive feedback topology. We infer the work in [9]

might also achieve BSNIM as two reactive feedback paths are employed in the first stage, although this was not discussed by the authors.

In this chapter the theory for BSNIM realization is discussed in details. Before the derivation it’s meaningful to understand the noise model of a MOS transistor in deep submicron CMOS technology, and keep in mind under what condition the derived equations for BSNIM are valid and accurate. This will be discussed in the next section. Then we will analyze the practical mechanisms jeopardizing the ideal SNIM condition inside a CMOS transistor, including the effects of the gate resistance, gate-to-drain capacitance, and induced gate noise.

Based on the derived four noise parameters, the strategies to achieve SNIM are proposed for both narrowband and broadband applications as design guidelines. In the following section a dual reactive feedback amplifier with LC ladder matching network is proposed to achieve BSNIM. The feedback circuit converges to a transformer for area compactness. This circuit topology is applied to realize a 3-11GHz ultra-wideband LNA and a 2-6GHz reconfigurable LNA [10], which will be detailed in the following chapters.

2

ind 2

ing 2

vn,Rg

Figure 2-2. The conventional noise model for common-source based LNA design.

2.2 Noise Model of a MOS Transistor in Deep Submicron MOS Technology

The noise model of a long channel MOS transistor, as shown in Figure 2-2, has been widely used in the common-source based LNA design [1], [2]. Three major noise sources are indicated in this model: the channel thermal noise i_nd² , the induced gate noise i , and the gate _ng² resistance (Rg) associated noise v , of which values are formulated as _Rg²

i_nd² =4kTγg_do⋅Δf , (2-1)

Here gdo is the drain-to-source channel conductance in strong inversion with zero VDS. The Cgsi

is the intrinsic gate-to-source capacitance via channel. The γ and δ are derived as 2/3 and 4/3 respectively for long channel MOS transistor. Because i_nd² and i are introduced by the same _ng² channel resistance, they are partially correlated to each other with the correlation factor defined as

in which the ci is derived as 5 32for long channel devices and the imaginary unit j comes from

the capacitive coupling via Cgsi. The directions of i_nd² and i in Figure 2-2 decide the sign of the _ng² correlation factor.

For deep submicron MOS transistors, short channel effects such as channel length modulation (CLM), carrier velocity saturation, and drain induced barrier lowering (DIBL) should be considered in noise model. These effects are manifest in a significant rise of the γ in (2-1). In the beginning such rise of γ was inferred attributed to the hot carrier effect [11]. In 2002 Chen and Deen showed that the increase of γ can be modeled in charge sheet model with CLM and is irrelevant to the hot carrier [12]. To include short channel effects in a simplified equation for circuit designers, Cui et al. tried to replace the γ·gdo with γgm·gm in (2-1) [13].

However, with an increased Vgs, the channel thermal noise was found keeping increasing while the gm has been saturated. This makes the γgm dependent to Vgs as well as transistor spice model hence not able to be predicted by hand calculation. In this section, we qualitatively interpret short channel effects in noise model to gain some insight.

Figure 2-3 is a cross-sectional view of a deep submicron MOS transistor in saturation mode with channel in moderate to strong inversion. The channel can be divided into two regions: a gradual charged region of length Lelec = Leff – ΔL (the region I in Figure 2-3) and the velocity saturated region of length ΔL (the region II), which emerges when VDS is larger than VDSsat. It is found, while the region I follows Ohm’s law with associated thermal noise, the region II doesn’t introduce noise [12]. The noise level of a MOS transistor is determined by the charge in region I only.

If the saturation is simply caused by pinch-off, i.e., VDG > -Vth, such that no charge resides in region II, the charge distribution is as the curve a in Figure 2-3. In such case, if ΔL ~ 0, the γ,

δ, and ci of 2/3¹, 4/3, and 5 32, respectively, can be obtained for (2-1), (2-2) and (2-4). In presence of carrier velocity saturation, the drain current saturates before the pinch-off occurs, i.e., VDG < Vth. There are charges resident in region II in such case but those charges are confined to the speed limit hence contribute no noise, either. The charge distribution in region I is relatively plane, like the curve b in Figure 2-3, such that the γ is close to 1 if ΔL ~ 0.

The more significant increase in γ is caused by DIBL: the electric field by the drain voltage actually increase the charge in region I, like the curve c in Figure 2-3. The effect of drain voltage on the charge, as well as the corresponding γ, also saturates when VDS > VDSAT because

1 The γ of 2/3, derived by integrating the inverted charge, is the same 2/3 in the expression of Cgsi = (2/3)·WLCox in saturation mode.

Figure 2-3. Short channel effects on FET thermal noise.

the region II absorbs the excessive voltage drop. Therefore the γ value by DIBL depends on the CMOS process and channel length. For circuit designers the γ value can be obtained via simulation at VDS=VDSAT, if the spice model provides an accurate noise model.

The last effect to be considered is CLM. When ΔL > 0 by CLM, the channel noise is also increased as

With the relationship [14]

The induced gate noise, in contrast to the channel thermal noise, is decreased by short channel effects as the effective channel resistance in region I is decreased by the increased charge. The decrease of δ in (2-2) can be inferred in proportional to the increase of γ. Hence the induced gate noise has been argued ignorable in deep submicron process [15], [16]. However in this thesis we still preserve the effect of induced gate noise for the possible case of very high frequency applications.

In SPICE model the induced gate noise is the associated noise of the non-quasi-static (NQS) effect of a MOS transistor in high frequency operation [14]. Figure 2-4 shows the simplified noise model in non-quasi-static (NQS) form. The Rgsi is equal to the inverse of gg in (2-2) with associated voltage noise

f

In addition to the associated noise sources, the metal overlap parasitic capacitances such as the gate-to-drain (Cgd) and the extrinsic gate-to-source (Cgse) capacitances are also included in this model as they are very significant in advanced CMOS technologies. The model in Figure 2-4 is useful for noise analysis in circuit simulator. However for hand calculation the approximated version with the term of induced gate noise in Figure 2-5 is more convenient. The difference between Figure 2-4 and Figure 2-5 is ignorable at frequency much smaller than 5·fT.

)

Figure 2-4. Simplified non-quasi-static transistor model of a MOS transistor;

2

Figure 2-5. The approximated model for hand calculation.

The model in Figure 2-5 will be used for noise derivation in the succeeding sections.

One should keep in mind that the equations (2-1) and (2-2) are only valid for a MOS transistor biased in strong inversion. When it is biased in moderate inversion or weak inversion, the gdo is no longer adequate to evaluate the channel noise. This is because the drain voltage affects channel charge (DIBL) so significantly, sometimes even overwhelms the effect by gate voltage. In consequence, the γ associated with gdo becomes a function of drain voltage. In such case, the γgm·gm instead of the conventional γ·gdo could be a better representation of channel noise [13].

2.3 Noise Analysis Technique for Noise Parameters

Noise parameter analysis is the most critical step to explore the solution for BSNIM. Noise parameters are those parameters indicating the effect of source impedance to noise factor. The widely used Y-parameter representation of noise parameters is derived by analyzing the output

2

Figure 2-6. The two different representations of noise parameters: (a) Y-parameter representation; (b) Z-parameter representation.

noise current, as shown in Figure 2-6(a). The noise factor (F) equation in noise parameters is [3] Z-parameter by analyzing the output voltage noise, as shown in Figure 2-6(b), such that

2

Figure 2-7. The proposed derivation technique for noise parameters: (a) The general case for the CS amplifier with lossless feedback network; (b) Equivalent circuit for noise derivation.

To accurately derive the noise parameters of an amplifier, the input-referred noise sources should be obtained first. The general measure is to calculate the corresponding output noise voltages for the short-circuited and open-circuited input individually first, then divide them by signal gain to obtain the input-referred voltage and current noise sources, respectively [17].

This generalized method, however, is not favorable to hand derivation because it makes the equations very complicated hence one is easy to loss the physical insight of components for the Zopt* (or Yopt*).

The proposed noise analysis technique for a CS amplifier with reactive feedback includes the noise model simplification and the equivalent noise source conversion. The former is illustrated in Figure 2-7. In Figure 2-7(a) is the general case of a CS amplifier with reactive feedback networks, in which the v_n²_{, g} is the equivalent gate noise source representing the noise

contribution by the i_nd² and i_n²_,L , which is.

(

²,

)

²

2 2

,g nd nL m

n i i g

v = + . (2-11)

If |YFP| and |ZFS| are much smaller than gm and 1/gm, respectively, the noise model in Figure 2-7(a) can be approximated to the equivalent circuit shown in Figure 2-7(b). The derivation of input referred noise sources therefore can be simplified and starts from the input of the voltage controlled current source, i.e. the vgs. It is obvious that the real parts of YFP and ZFS contribute noise to the input network and deteriorate noise performance directly hence a pure reactive feedback is preferred for LNA design. When this model is projected to the transistor noise model in Figure 2-5, the Cgd plays the role of YFP, and the ZFS is equal to 0. Noted that the equivalent circuit in Figure 2-7(b) is only for noise analysis – it cannot be used for input impedance analysis.

When referring these noise sources in Figure 2-7(b) to the input, the equivalent noise

source conversion, a derivative concept of equivalent noise fourpoles [18], can be applied. As shown in Figure 2-8(a), the shunt current noise source in,y after a series passive device Zp has input-referred noise sources including the original in,y and a series voltage noise source vn,y fully correlated to in,y, whereas the series voltage noise source vn,x remains unchanged at input. Then the total input-referred voltage noise source vn,i can be obtained by combining vn,x and vn,y. Note that the direction of the noise sources in Figure 2-8 carries the correlation information between noise sources.

The combination of v and v should be proceeded by employing vector operation, as

x

Figure 2-8. Two fundamental cases of equivalent noise sources conversion over passive devices:

(a) series device; (b) shunt device.

shown in Figure 2-9, whether the vn,x and in,y are correlated to each other or not. Assume any vector along the direction of unit vector aˆ_y is fully correlated to in,y, then the vn,x can be seen as combination of two orthogonal vectors along directions aˆ_y and aˆ_z, in which vectors along aˆ_z

have no correlation to in,y. The correlation factor cxy between vn,x and in,y is equal to cosθ0. After vector addition with vG_n,y, as shown in Figure 2-9, the total voltage noise source vn,i can be obtained with the correlation to in,y of factor ciy equal to cosθ1.

The equivalent noise sources conversion over a shunt passive device can be derived in the

x

Figure 2-9. Vector operation to combine two partially correlated noise sources.

⎥⎦

Figure 2-10. General case of equivalent noise sources conversion.

same manner, as shown in Figure 2-8(b). Noise contribution from Zs and Yp in Figure 2-8 can be included in the vn,x and in,y, respectively. The general form of this conversion is shown in Figure 2-10, in which

In (2-13) the dot in the numerator is the symbol of vector inner product. To reduce the unnecessary calculation complexity, it is better to keep those independent noise sources apart during derivation of the total input referred noise sources, i.e., retain noise sources in either fully correlated or uncorrelated types. Only combine those sources when necessary in the derivation. After the input referred noise sources obtained, Zopt* (or Yopt*) and other noise parameters can be accurately derived with the two-port noise theory introduced in [3].

2.4 SNIM for a CS Amplifier – The Problem and the Solution

In the microwave theory, a CS amplifier is designed either gain-optimized by impedance matching or noise-optimized by noise matching [3]. In LNA design the latter is more important since a low noise figure is demanded. The impedance matching of an LNA is simply for a minimized input reflection for a low VSWR such that the random length of a transmission line

noise optimized – it is to optimize the noise performance first, then design for a small input reflection with a feedback technique, by which the gain is slightly suppressed.

The exploration toward the BSNIM design necessitates derivation of input-referred noise sources for the noise parameters. All the noise parameters in this section are derived based on the analysis technique described in the previous section. Some reasonable simplification can be applied with the numerical approximation in the noise parameter equations. Then by analyzing Zin and Zopt* the strategies for BSNIM can be mapped out.

2.4.1 Mismatch between Z

in

and Z

opt*

of a CS MOS Amplifier

The mismatch between Zin and Zopt* of a CS amplifier is well known but was not well analyzed. To identify the factors causing such mismatch we start our discussion from a special case that always meets the SNIM condition, i.e., Zin = Zopt*. Consider the ideal hybrid-π model of a MOS transistor, shown in Figure 2-11, which includes i , _nd² i_n²_,L , and a noiseless gate resistor Rg. By applying the noise analysis technique in the previous section, Zopt* of this ideal transistor can be derived to be

gs g

opt R j C

Z^* = +1/ ω , (2-14)

and Zin is

2 L

in, 2

ind

Figure 2-11. Special case of a common-source amplifier satisfying SNIM condition at all frequency.

Z_in =R_g +1/ jωC_gs. (2-15)

Obviously Zopt* equals to Zin at all frequency. Therefore Zopt* and Zin can be both tuned and matched to Z0 (typically 50Ω) simultaneously with a lossless matching network to meet the SNIM condition.

In the practical case, as shown in Figure 2-5, Zopt* and Zin are found apart from each other by three major factors, referred to as Zin-to-Zopt* discrepancy factors: 1) independent noise sources at the gate, 2) gate-to-drain capacitance, and 3) induced gate noise. Effects of these three factors can be observed individually by the three test cases as shown in Figure 2-12.

The first one is the independent noise sources at the gate port. The typical one is the gate resistance noise v²_n,Rg. Using the noise model as shown in Figure 2-12(a), the analysis shows that Z ^* is significantly changed and derived as

2

Figure 2-12. Simplified MOS transistor noise models testing effects of: (a) gate resistance; (b) Cgd; (c) gate induced current noise.

gs frequency-dependent term and thus makes Zopt* larger than Zin. This factor is found to be the primary factor to Zin-to-Zopt* discrepancy in most CMOS LNA design. The noise from a non-ideal input matching network also contributes the same effect.

The second factor is the parasitic feedback via gate-to-drain capacitance Cgd. The feedback loop gain changes Yin (the inverse of Zin) without affecting Yopt* (the inverse of Zopt*). Consider the simplified transistor noise model with Rg= 0 as in Figure 2-12(b). It can be found that

)

The third factor is the induced gate noise. Consider the noise model with Rg= 0 as in Figure 2-12(c). Cgse, Cgd, and i_n²_,L are ignored. The derived Yopt* is approximately as

( )

By comparing this Yopt* with the corresponding Yin, equal to jωCgs, the induced gate noise is found reducing the effective capacitance of Yopt* and introduces a frequency dependent real part on Yopt*.

Now consider the equivalent circuit in Figure 2-5 with Rg and ZL both equal to zero. Define ρ as the noise contribution ratio,

(

2 ²,

)

(

_{gs gd}

)

² 2 ² _{i gsi}

(

_{gs gd}

)

^{2 2} _gsi²

With the typical device values in 0.18um CMOS technology, CN and c1 are about 0.94·(Cgd+Cgd) and 0.98, respectively. More than 99.5% of Re{Zopt*} comes from its second term in (2-24). Hence Zopt* can be approximated as

If i_n²_,L is assumed frequency-independent, Zopt* has a frequency-independent quality factor.

Hence in Smith Chart the Sopt* curve follows the constant-Q contour, completely different to the behavior of a normal RC network.

Hence in Smith Chart the Sopt* curve follows the constant-Q contour, completely different to the behavior of a normal RC network.

在文檔中 應用於超寬頻及多通訊標準無線接收機之互補式金氧半低雜訊前端電路 (頁 19-0)