Chapter 2 Section II
II. 2.6 Comparison
Section I and Section II are proposed two mixers. Section II utilizes Section I low voltage mixer to improve its flicker noise. From the measured results, the conversion gain enhances 4.5 dB and noise figure reduces 4 dB. The goal is implemented in this design. Table 2.3 shows this two mixer performance at 5.2 GHz.
Table 2.3 Measured results with and without inductor Reference
Specification
Low Power Mixer Low Power Mixer with Inductor
Process CMOS 0.18um CMOS 0.18um
Operating Frequency (GHz) 5.2 5.2
Supply Voltage(V) 1.0 1.0
RF Return Loss (dB) <-10 <-10
IF Return Loss (dB) <-10 <-10
LO Power (dBm) -6 -6
Conversion Power Gain (dB) 1.2 5.8
LO to RF Isolation -45 -61
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Chapter 3
Ultra Low power mixer
3.1 Introduction
As the progressing of the times, the MOS scaling is reduction speedy. With the down scaling of the transistors, it is severe with supply voltage. In the RF receiver, low cost and low consumption is first consideration. The demands for low power wireless transceivers operating GHz band are more critical. In order to achieve low power consumption, circuit topologies combine LNA with mixer for current reuse [1] or combine oscillator with mixer [2]. Transformer-based mixer [3] is presented for low power consumption. By subthreshold biasing of MOS transistor, subthreshold mixer is proposed for Ultra low power [4].
Fig. 3.1 shows a single balance mixer. It is often used in RF receivers and frontends. The transistor M1 as a transconductance converts RF signal into current and commutates at M2 and M3 for frequency translating. The signal current converts to voltage through load resistor at IF. With this topology, it is not suitable for low supply voltage and power application. Folded mixer is presented for solving the problem [5].
Although folded mixer can reduce the supply voltage, it does not reuse DC current and may increase power consumption. Fig. 3.2 shows a complementary current reused mixer [6]. This topology comprises DC current reused and low supply voltage at the same time. In order to enhance conversion gain, current bleeding technology is adopted [7]. Fig. 3.3 is presented complementary current reused mixer with current bleeding technique.
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Fig. 3.1 Single balance mixer
Fig. 3.2 Complementary current reused mixer
Fig. 3.3 Complementary current reused mixer with current bleeding technology [2]
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3.2 Ultra low power mixer
Fig. 3.4 The proposed Ultra low power mixer
Fig. 3.4 shows the proposed circuit. The complementary current reused topology technique is adopted for this single balance mixer. The RF voltage signal converts to current through transistor M1 and M2 (transconductance stage), and then the current coupled to the sources of M3 and M4 (switch stage) through capacitor C2. The resistors R2 and R3 are used to load resistors. The load resistors are as large as possible to achieve high conversion gain. After translating frequency to IF band, the common drain output buffer is connected to switch stage and load resistors. In DC analysis, the complementary current reused topology provides low power consumption and low supply voltage. Transconductance stage utilizes PMOS stacked on the top of the NMOS just like an inverter. The inverter can not only provide current bleeding technique and enhance the transconductor of the transconductance stage. Therefore in the AC analysis,
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the RF signal is converted through M1 and coupled to M2 and then commutating at M3 and M4 through capacitor C2. RF input network employs source degeneration with inductors L1 and L2 to reach input matching network and signal amplification.
Transconductance of the switch stage transistors M3 and M4 is influenced with conversion gain [6]. If gm3 is large enough, the conversion gain is independent of switch stage. On the contrary, gm3 is not sufficient and conversion gain will be decreased. The bleeding current affects transconductance of the switch stage and gain. The choice of the ratio is important for current bleeding technology. Fig. 3.5 shows conversion gain versus ratio of current bleeding. The gain can be achieved maximum at the vicinity of 60 to 70 percent of the ratio. Fig. 3.6 shows noise figure versus ratio of current bleeding.
Noise figure can be achieved minimum at the vicinity of 65 to 70 percent. Hence, the moderate selection of the ratio of current bleeding can achieve ideal performance in conversion gain and noise figure.
0.5 0.55 0.6 0.65 0.7 0.75 0.8
Ratio of current bleeding (%) 0
0.5 1 1.5 2 2.5
Cinversion gain (dB)
Fig. 3.5 Conversion gain versus Ratio of current bleeding
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0.55 0.6 0.65 0.7 0.75 0.8
Ratio of current bleeding (%) 12.15
Fig. 3.6 Noise figure versus Ratio of current bleeding
Linearity in the RF receivers and front ends is influenced by the mixer. Linearity dominated with transconductance of the mixer for ideal switches. In the transconductance stage, the nonlinearity elements are generated from gm
(transconductance), gds (output conductance), and Cgs (gate-source capacitance).
Linearity of overall mixer is dominant from gm [8], [9]. Transconductance g can be m expressed by Taylor series as follows
1 2
1 2 3 ...
m m m gs m gs
g =g +g v +g v + . (11)
And the drain current can be expressed by Taylor series as follows
( )
1( )
2 2( )
3 3( )
...d m gs m gs m gs
i t =g v t +g v t +g v t + (12)
The harmonic elements should be decreased or canceled out. In addition to nonlinearity elements, the gate bias of transistors M1 and M2 are strongly influenced for linearity. The choice of appropriate gate bias can reduce harmonic effects [6], especially the “sweet spot” [10]. The moderate bias at the vicinity of sweet spot enhances the linearity. Therefore, the trade-off between conversion gain, noise figure, and linearity should be considered.
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3.3 Chip implementation and measured consideration
Fig. 3.7 shows layout of the proposed mixer. The proposed circuit is designed for on-wafer measurement. It follows the rules of CIC’s (Chip Implementation Center’s) probe station testing rules.
Fig. 3.7 Layout of the proposed mixer
The Ultra low power mixer is designed for on wafer circuit measurement. So the layout must follow the rule of CIC’s (Chip Implementation Center’s) probe station testing rules. Fig. 3.8 shows the Ultra low power mixer for on wafer circuit measurement with four probes.
Fig. 3.8 On wafer measurement for ultra low power Mixer
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The simple measurement setups are shown in Fig. 3.9 (a-d). We use the RF IC measurement system powered by LabView to measure the linearity and conversion power gain of the Ultra low power mixer.
(a) (b)
(c)
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(d)
Fig. 3.9 Measurement setup of the proposed UWB low power mixer for (a) input return loss (b) conversion gain and P1dB (c) IIP3 (d) noise figure
3.4 Simulation result and discussion
In this section, the simulated results are shown below. We set operating frequency at 5.2 GHz. Fig. 3.10 shows RF return loss. RF return loss is below -20 dB at 5.2 GHz.
Fig. 3.11 shows LO power versus conversion gain. When LO power is -9 dBm, the conversion gain can obtain the maximum gain. Fig. 3.12 shows P1dB and Fig. 3.13 shows the input third order intercept point (IIP3). The two illustrations reveal linearity of this mixer. This mixer has simulation P1dB of -19 dBm, and IIP3 of -8 dBm. The double sideband noise figure is close to 11.25 dB at 5.2 GHz as shown in Fig. 3.14.
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Fig. 3.10 The simulated RF return loss
-16 -14 -12 -10 -8 -6 -4 -2
Fig. 3.11 The simulated LO Power versus conversion gain
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Fig. 3.12 The simulated P1dB
-40 -35 -30 -25 -20 -15 -10 -5 0
Fig. 3.13 The simulated input third order intercept point (IIP3)
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Fig. 3.14 The simulated noise figure versus Frequency
Fig. 3.15 shows two different current bleeding techniques with Ultra low power mixer. From Fig. 3.15 (a), the resistor R is used to current injection to enhance conversion gain. Then the transistor M1 as transconductance stage should be biased at saturation region to operate normally. In order to bias in the saturation region, the transistor M1 drain-source voltage should be larger than the overdrive voltage. At the same time, the transistors M3 and M4 should have enough voltage to bias at switching.
Therefore, the complementary MOS technique can improve the restriction in Fig. 3.15 (b). Because of the transistor M2, the transistor M1 can bias vicinity between saturation region and linear region. In this biasing saturation, the transistor M1 has a little amplifying effect. However, it should not be worried due to the transistor M2. The amplifying purpose can be achieved by the transistor M2 biasing in the saturation region. This type amplifies not merely signal, it can use larger loaded resistor to get larger conversion gain. The larger conversion gain can reach by this type. The degenerated inductor is modified to small inductor to enhance the gain.
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(a)
(b)
Fig. 3.15 (a) Ultra low power mixer with current bleeding R (b) Ultra low power mixer with current bleeding M2
After moderate adjusting, the better performance is presented as follow. Fig. 3.16 shows the conversion gain versus LO power. The maximum conversion gain is
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presented at -9 dBm. Fig. 3.17 shows the RF and IF return loss. The return loss is lower than -10 dB respectively. Fig. 3.18 is presented P1dB. The input compression gain is -20 dBm in this design. The IIP3 is shown at Fig. 3.19. The IIP3 is -8 dBm at 10 MHz separated of RF two tones. Fig. 3.20 shows the noise figure. The double side band noise figure is 13.6 dB at 5.2 GHz.
Fig. 3.21 shows three types isolation (LO_IF (a), LO_RF (b), and RF_IF (c)).
Roughly analyzing, because that the single balance mixer is the based type of this design, the differential signal of LO switch stage could not cancel out at output.
Therefore, the output appear strong LO signal from Fig. 3.21 (a). The isolation of LO to RF is good and will not result in reflecting from antenna and DC offset from Fig. 3.21 (b). The RF signal will degrade at output in conventional single balance mixer, and this design will cause feedthrough from load resistor. Although RF signal is weak, the signal will cause loss at load stage and feedthrough to IF stage from Fig. 3.21 (c). Fig. 3.22 shows the layout of the proposed mixer.
-25 -20 -15 -10 -5 0 5
Fig. 3.16 The simulated conversion gain versus LO power
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Fig. 3.18 The simulated P1dB at 5.2 GHz
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Fig. 3.19 The simulated IIP3 at 5.2 GHz
1 3 5 7 9 11 13
Fig. 3.20 The simulated noise figure
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Fig. 3.21 The simulated isolation (a) LO to IF isolation (b) LO to RF isolation (c) RF to IF isolation
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Fig. 3.22 layout of the proposed mixer
The difference of two data above is moderate biasing, size choosing, and output buffer. The original mixer is used common drain with bias T, and it has almost 4 dB loss. Therefore, the output to buffer would have 1dB loss from simulation. The modify mixer is used common drain and common source to combine differential signal. And the output to buffer has gain more than 1 dB. Therefore, we can get better performance.
Fig. 3.23 shows the schematic output buffer.
Fig. 3.23 Differential in single out output buffer
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The simulated results including modified simulation are in Table 3.1. The comparisons between the two mixers are significant as Table 3.1.
Reference
Specification
This Work . Sim.
This Work Modified. Sim.
Process CMOS 0.18um CMOS 0.18um
Operating frequency (GHz) 5.2 5.2
Supply Voltage (V) 0.6 0.6
RF Return Loss (dB) <-20 <-15
LO Power (dBm) -9 -9
Conversion Power Gain (dB) 1.7 5.2
DSB NF (dB) 11.25 9.5
P1db (dBm) -19 -20
IIP3 (dBm) -8 -8
Core Circuit (mW) 0.57 0.42
Buffer (mW) 3.4 2.4
Table 3.1 Simulated performance of the Ultra low power mixer
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3.5 Comparisons
Table 3.2 shows the comparison of this work and other recently low power mixer paper. This work reveals lower power consumption comparing with other work. The simulation results reveal the power is lower than the other reference and the conversion gain is moderate.
Table 3.2 Comparison of low power mixers Ref. Process Frequency
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Chapter 4
Future Work
4.1 Future work
In this thesis, low power mixer and research of flicker noise in mixer is introduced. Fig. 4.1 shows the conventional Gilbert cell mixer which is popular in receiver and transmitter. However, this type is influenced by flicker noise in DCR systems. The dynamic current injection technique is proposed in Fig. 2.25. It can reduce the noise pulse trains and inject current to the core when turning on and off in the switch. The PMOS switch circuit influences strongly on flicker noise. The large size can inject more current into core to apply to reduce the noise pulse. The large size of PMOS switch circuits may cause parasitic capacitance effect and generate leakage paths in the core. It generates nonlinearity harmonics and degrades linearity.
Therefore, the parasitic capacitance effect should be diminished. Utilizing resonant inductor to minimize the effect is proposed [1]. The resonant inductor in parallel type tunes out the capacitance at 2fo. Fig. 4.2 shows the dynamic current injection with resonant inductor.
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Fig. 4.1 Conventional Gilbert cell mixer
Fig. 4.2 Dynamic current bleeding with resonant inductor
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Utilizing resonant inductor can enhance the linearity and reduce flicker noise [1]. In practice, the resonant inductor can be expressed as inductor Ls series resistor Rs in general and be expressed as resistor Rp at resonance, which is shown in Fig. 4.3.
Fig. 4.3 Equivalent circuit of resonant inductor
Although the parallel inductor can tune out parasitic capacitance and prevent the nonlinearity effect, it still has shunted path. Rp is the shunted resistor of one resonant inductor L. Therefore, some RF signal current flows into Rp. Utilizing different resonating technique to tune out the capacitance is necessary. Fig. 4.4 is proposed the new topology mixer to improve this problem.
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Fig. 4.4 The proposed mixer to reduce flicker noise
This design utilizes two different techniques to reduce flicker noise in different concepts.
From the understanding of the mechanism in flicker noise, the dynamic current bleeding only injects current into core at the switch PMOS turning on and off (see Chapter 2). Current bleeding with two resonant inductors is changed from conventional current bleeding [2]. From Fig. 4.4, the flicker noise reduction can be divided into two parts. One is dynamic current bleeding and the other is current bleeding with two resonant inductors. Because dynamic current bleeding technique
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only happens in the switching moment, this design can be analyzed as equivalent circuit. Fig. 4.5 is the equivalent circuit. Since the RF signal is differential, the node between L1 and L2 is virtual ground. Therefore, the analysis is only needed the half of the whole circuit. The equivalent half circuit is shown in Fig. 4.6. The input impedance is real impedance at resonant frequency [2]. The RF signal will be avoided flowing into current bleeding and tuned out the parasitic capacitance. The two resonant inductors are more efficient than one resonant inductor. This is the future work which can improve the flicker noise and linearity.
Fig. 4.5 The equivalent model of double balance mixer with current bleeding circuit and two resonating inductors
Fig. 4.6 The equivalent half circuit
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Reference
Chapter 1
[1] IEEE 802.15 WPAN High Rate Alternative PHY Task Group 3a (TG3a).
http//www.ieee802.org/15/pub/TG3a.html.
[2] http://hraunfoss.fcc.gov/edocs_public/attachmatch/FCC-02-48A1.pdf Chapter 2
Section I
[1] A. Bevilacqua, and A. M. Niknejad, “An Ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receiver,” IEEE J. Solid-State Circuits, vol.
39, no. 12, pp. 2259–2268, Dec. 2004.
[2] Barrie Gilbert, “A precise four-quadrant multiplier with subnanosecond response,”
IEEE J. Solid State Circuits, vol. sc-3, NO. 4, PP. 365-373, Dec. 1968.
[3] M. Wurzer, T. F. Meister, S. Hackl, H. Knapp, and L. Treitinger,“30 GHz active mixer in Si/SiGe bipolar technology,” in Proc. IEEE APMC, Dec. 2000, pp.
780–782.
[4] S. Hackl, J. Bock, M. Wurzer, and A. L. Scholtz, “40 GHz monolithic integrated mixer in SiGe bipolar technology,” in IEEE MTT-S Int. Dig., Seattle, WA, 2002, vol. 2, pp. 1241–1244.
[5] C.-S. Lin, P.-S.Wu, H.-Y. Chang, and H.Wang, “A 9-50-GHz Gilbertcell down-conversion mixer in 0.13-=mum CMOS technology,” IEEE Microw.
Wireless Compon. Lett., vol. 16, no. 5, pp. 293–295, May 2006.
[6] M.-D. Tsai and H. Wang, “A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-_m CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 14, no.
11, pp. 522–524, Nov. 2004.
- 69 -
[7] A. Q. Safarian, A. Yazdi, and P. Heydari, “Design and analysis of an ultrawide-band distributed CMOS mixer,” IEEE Trans. VLSI Syst., vol. 13, no. 5, pp. 1470–1478, May 2005.
[8] V. Vidojkovic et al., “A low-voltage folded-switching mixer in 0.18-_m CMOS,”
IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1259–1264, Jun. 2005.
Section II
[1] M. D. Jamal and A. F. Tor, CMOS RF Modeling, Characterization and Applications. Singapore: World Sci., 2002.
[2] A. A. Abidi, “Direct-conversion radio transceivers for digital communications,”
IEEE J. Solid-State Circuits, vol. 30, pp. 1399–1410, Dec. 1995.
[3] B. Gilbert, “A precise four quadrant multiplier with subnanosecond response,”
IEEE J. Solid-State Circuits, vol. SC-3, no. 12, pp. 365–373, Dec. 1968.
[4] J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Trans.
Electron Devices, vol. 41, no. 11, pp. 1965–1971, Nov. 1994.
[5] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: A simple physical model,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15–25, Jan. 2000.
[6] H. Darabi and J. Chiu, “A noise cancellation technique in active-RF CMOS mixers,” in Int. Solid-State Circuits Conf., 2005, pp. 544–545, Session 29.
[7] J. Park, C.-H Lee, B.-H Kim, and B. Kim, “Design and analysis of low flicker-noise CMOS mixers for direct-conversion receiver,” IEEE Trans. Microw.
Theory Tech., vol. 54, no. 12, pp. 4372–4380, Dec. 2006.
Chapter 3
[1] A. Zolfaghari and B. Razavi, “A Low-Power 2.4-GHz Transmitter/Receiver CMOS IC,” IEEE J. Solid-State Circuits, vol. 38, pp. 176-183, Feb. 2003.
[2] T. Wang, et al., “A low-power oscillator mixer in 0.18-um CMOS technology,”
- 70 -
IEEE Trans. Microwave Theory Tech., vol. 54, no. 1, pp. 88-95, Jan. 2006.
[3] C. Hermann, M. Tiebout and H. Klar, “A 0.6-V 1.6-mW Transformer-Based 2.5-GHz Downconversion Mixer With +5.4-dB Gain and -2.8-dBm IIP3 in 0.13-um CMOS,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 2, pp.
488-495, Feb. 2005.
[4] H. Lee and S. Mohammadi, “A 500µW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications,” in Proc. RFIC symposium, pp. 325-
328, June 2007.
[5] P. Choi et al., “An experimental coin-sized radio for extremely low power WPAN (IEEE 802.15.4) application at 2.4 GHz,” IEEE J. Solid-State Circuits, vol. 38, no.
12, pp. 2258–2268, Dec. 2003.
[6] H.-H. Hsieh and L.-H. Lu, “Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 7, pp. 1445–1458, Jul. 2007.
[7] S.-G. Lee and J.-K. Choi, “Current-reuse bleeding mixer,” Electron. Lett., vol. 36, no. 8, pp. 696–697, Apr. 2000.
[8] S. Kang, B. Choi, and B. Kim, “Linearity analysis of CMOS for RF application,”
IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 972–977, Mar. 2003.
[9] J. Kang, J. Yoon, K. Min, D. Yu, J. Nam, Y. Yang, and B. Kim, “A highly linear and efficient differential CMOS power amplifier with harmonic control,” IEEE J.
Solid-State Circuits, vol. 41, no. 6, pp. 1314–1322, Jun. 2006.
[10] B. Toole et al., “RF circuit implications of moderate inversion enhanced linear region in MOSFETs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp.
319–328, Feb. 2004.
[11] V. Vidojkovic et al., “A low-voltage folded-switching mixer in 0.18-um CMOS,”
IEEE J. Solid-State Circuits, vol. 40, no. 6, pp.1259–1264, Jun. 2005.
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Chapter 4
[1] J. Yoon, H. Kim, C Park, J. Yang, H. Song, S. Lee, and B. Kim, “A new RF CMOS Gilbert Mixer with improved noise figure and linearity,” IEEE Trans.
Microw. Theory Tech., vol. 56, no. 3, pp. 626–631, Mar. 2008.
[2] J. Park, C.-H Lee, B.-H Kim, and B. Kim, “Design and analysis of low flicker-noise CMOS mixers for direct-conversion receiver,” IEEE Trans. Microw.
Theory Tech., vol. 54, no. 12, pp. 4372–4380, Dec. 2006.
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Vita and Publication
姓 名: 陳志豪 學 歷:
國立台東高級中學 ( 87 年 9 月 ~ 90 年 6 月)
國立中山大學電機工程學系 ( 90 年 9 月 ~ 95 年 1 月) 國立交通大學電信工程所碩士班 ( 95 年 9 月 ~ 97 年 6 月)
Publication Remarks:
1. Chih-Hao Chen and Christina.F. Jou “A 3~8 GHz broadband low power mixer”, PIERS 24-28 March, 2008 in Hangchow, China.