Chapter 2 Section I
I. 2.4 Measurement results and discussion
This chip size is 1.109*0.83 mm2. By the measured setups illustrated above, the measured results are listed below. The folded low power mixer consumes 2.9mA and the buffer consumes 9mA dc current with 1V supply voltage. Therefore this design dissipates only 2.9mW in core. As shown in Fig. 2.10, the measured RF port input return loss are lower than -10 dB through 3.1-10.6 GHz. As shown in Fig. 2.11, the measured IF port input return loss are lower than -10 dB through 100-528 MHz. Fig.
2.12 (a) ~ (e) shows the conversion power gain with LO power sweeping. It reveals that it only needs -6 dBm in this design to get the maximum gain. In simulation, the conversion power gain has maximum value when LO power is -10 dBm, but in measurement, the power gain has maximum value when LO power is -6 dBm. Fig. 2.13 (a) ~ (h) shows the input P1dB from 3.1 ~ 10.6 GHz with measured -11 dBm and simulated -16 ~ -18 dBm. Fig. 2.14 shows the conversion gain versus frequency from 3.1 ~ 10.6 GHz with LO power -6 dBm (measurement) and LO power -10 dBm (simulation). In measurement, the conversion gain variation in 1 dB from 3.1 ~ 9.5 GHz, and variation in 2 dB from 3.1 ~10.6 GHz. Fig. 2.15 (a) ~ (d) shows the input third order intercept point (IIP3) from 3.1 ~ 10.6 GHz with RF frequency 2 MHz separated in measurement. Because the measured setups are considered the noise of the measurement instrument, the reference level is selected lower and influenced the measured results. Fig. 2.16 shows the isolation from LO port to IF port. The LO_IF isolation is better than -30 dB from 3.1 ~ 10.6 GHz. Fig. 2.17 shows the isolation from LO port to RF port. The LO_RF isolation is better than -40 dB in UWB bandwidth. Fig.
2.18 shows the RF port to IF port isolation. The measured results are unexpected and strongly influenced by improper layout which RF port and IF port are closed.
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Fig. 2.10 The measured and simulated RF return loss
0 2 4 6 8 10 12 14 16
Fig. 2.11 The measured and simulated IF return loss
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Fig.2.12 The measured and simulated conversion gain versus LO power (a) RF frequency at 3.1 GHz (b) RF frequency at 5.1 GHz (c) RF frequency at 7.1 GHz
(d) RF frequency at 9.1 GHz (e) RF frequency at 10.6 GHz
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- 16 - Fig. 2.13 The measured and simulated P1dB
(a) RF frequency at 3.1 GHz (b) RF frequency at 4.1 GHz (c) RF frequency at 5.1 GHz (d) RF frequency at 6.1 GHz (e) RF frequency at 7.1 GHz (f) RF frequency at 8.1
GHz (g) RF frequency at 9.1 GHz (h) RF frequency at 10.6 GHz
3 4 5 6 7 8 9 10 11
Fig. 2.14 The measured and simulated conversion gain versus frequency
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(b) RF frequency at 6.101 and 6.099 GHz
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(c) RF frequency at 9.101 and 9.099 GHz (change chip)
-30 -25 -20 -15 -10 -5 0 5 10
(d) RF frequency at 10.601 and 10.599 GHz (change chip)
Fig. 2.15 The measured and simulated input third order intercept point (IIP3)
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Fig. 2.16 The measured isolation LO_IF versus frequency
3 4 5 6 7 8 9 10 11
Fig. 2.17 The measured isolation LO_RF versus frequency
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Fig. 2.18 The measured isolation RF_IF versus frequency
3 4 5 6 7 8 9 10 11 12 13
Fig. 2.19 The measured and simulated noise figure versus frequency
The measured results shown above reveal the good flatness from 3.1 ~ 10.6 GHz.
The RF and IF port has good matching network and matches to 50 Ω. The measured conversion gain is lower than simulation 2 dB, because the post-simulation is not taking
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all circuit into EM simulation. The measured linearity performances are better than simulation, and it is related to lower conversion gain. Linearity in mixer is dominant by the transconductance of the transconductance stage. CMOS topology as transconductance stage should be biased in moderate region to achieve maximum swing.
In this design, gate bias is 0.68V in NMOS and 0.3 in PMOS. However, the linearity is bad in this bias. In mixers, transconductance dominate the linearity. Transconductance can be expressed as followed
1 2
1 2 3 ...
m m m gs m gs
g =g +g v +g v + (5), which gm1 is the differential of the ID, gm2 is the differential of the gm1, and gm3 is the differential of the gm2. In (5), gm1 dominates the conversion gain and gm3 dominates the linearity. Therefore, the maximum in gm1 and minimum in gm3 can get perfect performance. Fig. 2.20 shows gm1, gm2, and gm3 characteristic versus gate bias with NMOS and PMOS. In Fig. 2.20 (a), the gate bias in this design (0.68V) with fixed PMOS bias at 0.3V is almost the maximum gm3 and not maximum gm1. In Fig. 2.20 (b), the gate bias is 0.7V (1V-0.3V) with fixed NMOS bias at 0.68V, the situation is similar to Fig. 2.20 (a). Linearity and conversion gain is not the optimum value in this bias.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
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Fig. 2.20 Simulated gm1, gm2, and gm3 characteristic versus gate-to-source voltage (a) NMOS (M1) (b) PMOS (M3)
The most significant influences is isolation which is worst than simulation.
Because the improper layout resulted in RF to IF isolation feed-through. The RF signal can easily appear at IF port and the layout should be moderate modified. The measured noise figure is higher than simulation, and some problems happened in here. When measuring the noise figure, the measured results in conversion gain are mismatched to the other measured results which are measured in different ways. Therefore, this data should be measured again to make sure what happened. In mixer stability, this topology should be considered. Assuming the variation of Vpdc and Vndc are small, the variation in V1 which is the drain voltage of the M1 and M3 can be expressed as following equation [8] of NMOS and PMOS, and gms is the transconductance of the switch stage transistor.
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The gms dominates the equation if its value is large enough. And CMOS topology is no need for common mode feedback. However, in practice measurement, the mixer is sensitive in variation of Vpdc and Vndc. Because CMOS transconductance stage input versus output characteristic is as following if Vdd is 1V without capacitor.
0 0.2 0.4 0.6 0.8 1
Fig. 2.21 CMOS input voltage versus output voltage
The moderate operation is only at 0.48V for two transistors. In the abnormal operating region in CMOS, the performance will be limited. In this design, Fig. 2.22 is shown with fixed Vpdc at 0.3V. In measured biasing voltage, the 10% variation of Vndc let CMOS operating out of saturation region. The moderate bias is important in mixer design.
0 0.2 0.4 0.6 0.8 1
Gate bias of NMOS (V) 0
Fig. 2.22 CMOS input voltage versus output voltage with capacitor C
The comparisons of the simulated and measured results are in Table 2.1.
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Table 2.1 Simulated and measured performance of the folded low power mixer Reference
Specification
This Work Sim.
This Work . Meas.
Process CMOS 0.18um CMOS 0.18um
Band width (GHz) 3.1-10.6 3.1-10.6
Supply Voltage(V) 1.0 1.0
RF Return Loss (dB) <-10 <-10
IF Return Loss (dB) <-10 <-10
LO Power (dBm) -10 -6
Conversion Power Gain (dB) 2.3~3.4 0-1.8
LO to RF Isolation -85 -40
LO to IF Isolation -75 -30
RF to IF Isolation -60 -10
DSB NF 10.4~13 16.8~18.2
P1db at 6.1 GHz -16 -11
IIP3 at 3.1 GHz -6 -3
Core Circuit (mW) 2.74 2.9
Buffer (mW) 8.88 9
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Section II
Low Power Mixer with Flicker Noise Improved Technique
II. 2.1 Introduction
Rapid development of wireless communication, the target is low power and low cost system. For receivers of communication system, direct conversion receiver (DCR) is most popular type. In the direct conversion system, flicker noise is strong influenced on noise figure and sensitivity. Some problems are presented for DCR with CMOS technology. The critical problem is the noise influence [1]. And there are important repercussions in DCRs [2]. The flicker noise (1/f) of the mixer degrades SNR (signal-to-noise ratio) at the output baseband.
Because of good isolation, Gilbert cell is the most popular topology for using.
Gilbert cell has good isolation for LO-IF and LO-RF and symmetric balance [3]. For application in Gilbert cell mixer of DCR, the noise is influence in flicker noise. The flicker noise in active mixer is discussed as followed.
II. 2.2 Flicker Noise in Mixers
CMOS transistors suffer from high flicker noise which is inversely proportional to the device area [4]. This is produced from CMOS process and unable avoided. So the size of CMOS transistor is influenced in flicker noise.
Double balanced mixer in DCRs comprises transconductance stage, switch stage with local oscillator, and IF loaded stage. Because flicker noise in RF stage is low frequency noise, it will be up-converted to vicinity of LO frequency. And it will not contribute any flicker noise in DCR systems. Load stage is used of polysilicon resistors which are free of flicker noise. Mismatches in the switch pairs will also
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generate a small amount of flicker noise at the output. Therefore, switch stage is significant contributed flicker noise at baseband [5].
Flicker noise in DCRs is determined in switch pair devices. There are two different mechanisms that generate flicker noise. The first one is direct mechanism, which is generated in the switching transitions. When LO stage commutating motion, it will generate noise pulse trains. Because noise transfer function is linear from each device, the superposition theory holds. The low frequency in switching pairs should be calculated as the voltage source Vn(t). Fig. 2.23 shows the noise pulses resulting in flicker noise at mixer output [6]. Because mixer needs sine wave of local oscillator to drive switching quad, the large sine-wave LO signal accompanies noise. The noise advances or retards the time of zero crossing by ∆t=Vn(t)/S. So the noise pulse trains of random widths ∆t and amplitude of 2I at a frequency of 2ωLO represent at the output.
Fig. 2.23 Noise pulses resulting in flicker noise at mixer output [6]
( )
V tn
t S
∆ = (7)
Over one period, the average of output current is [5]
,
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where I is the bias current of RF transconductance stage, T is the LO period, Vn is the flicker noise of switch pairs, and S is the slope of the LO signal. Weff and Leff are the effective width and length, Cox is the oxide capacitance, f is frequency, and Kf is a process parameter [5]. In the indirect mechanism, capacitance Cp is main determined flicker noise. It can describe as following equation
( )
where Cp is the tail capacitance between LO switch stage and RF transconductance stage with all parasitic capacitance. T is the LO period, gms is the transconductance of LO switches, ωLO is the frequency of local oscillator, and Vn is equivalent flicker noise of LO switches [5].
So, there are some topologies to reduce flicker noise from above equation. From (8), increasing the slope of the LO signal and reducing the equivalent flicker noise of switching transistors can alleviate the influence. It needs to increase sizes of the switch transistors. However, it has some drawbacks. The large sizes of switching transistors increase the parasitic capacitance at common source of switch stage and increase the flicker noise indirectly.
Reduction of bias current of the switch stage can lower the noise pulses and improve flicker noise. Conventional Gilbert cell with current bleeding is proposed in Fig. 2.24. However, this technique has some important drawbacks. When reducing the biasing current of the switch pairs, the impendence as seen from RF transconductance stage into switch stage (1/gms) will be increased. It allows more RF leakage current flowing into the bleeding circuit. The leakage current will also be shunt by the parasitic capacitance at the node between RF stage and switch stage.
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This decreases the gain and reduces the mixer linearity. The dynamic current bleeding circuit is proposed to solve the problems [6]. Fig. 2.25 is presented the conventional Gilbert cell mixer with dynamic current bleeding.
Fig. 2.24 Conventional Gilbert cell with current bleeding
Fig. 2.25 Conventional Gilbert cell with dynamic current bleeding
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Since the noise pulse trains is only present at the switching instant of LO switch quads. A dynamic current bleeding is injected to the core through a switch control circuit at the switching instant of switch pairs. Fig. 2.26 shows the theory and idea for dynamic current bleeding [6]. The switching event controls by the nodes at common source of switch pairs (Fig. 2.26 nodes A and B). The waveform of nodes A and B is shown in Fig. 2.26 (b). Because the LO provides large signal, the voltage waveforms at nodes A and B are just like full wave rectifiers. The injection of dynamic current ID
occurs when voltage is small. This way reduces the height of noise pulse directly, and noise pulse at the output is close to zero as shown in Fig. 2.26 (b). On the other time, the switch is close and generates no current to circuit.
Fig. 2.26 (a) Dynamic current injection (b) Nodes waveform [6]
There are a few drawbacks in this topology. It needs high power of LO to drive switch stage and its conversion gain is low. It is just like a passive mixer. In spite of the imperfect of switching, this technique is still improved significant.
To improve flicker noise in the mixer, reducing the bias current of the switch
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stage and tuning out the tail capacitance from (8) and (10). Current bleeding technique is decreased the bias current of the switch stage, and has a few drawbacks described above. Fig. 2.27 shows the conventional Gilbert cell mixer with current bleeding and one resonating inductor. Even though the current bleeding can reduce to LO bias current to improve flicker noise, it is generated the flicker noise from tail capacitance in indirectly mechanism. In order to diminish the tail capacitance, the choice of small size device in RF and LO stage is an idea. Nevertheless, CMOS transistors suffer from high flicker noise which is inversely proportional to the device area [4]. So the other way is using one inductor to tune out the tail capacitance instead of changing the size of MOS. The inductor is connected from one path at the nodes between RF and LO stage to the other path as shown in Fig. 2.27. The equivalent model of double-balanced mixer with current bleeding circuit and one resonating inductor is shown in Fig. 2.28 [7].
Fig. 2.27 Current bleeding technique with inductor
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Fig. 2.28 Equivalent model of double-balanced mixer with current bleeding circuit and one resonating inductor [7]
The gm1 is the transconductance of the switch transistor M1, and gm2, gm3, gm4 are the same as gm1. Cp is the parasitic capacitance at the node of transconductance stage and switch stage. RB is the load of the transistor as current bleeding. Lp is the resonating inductor. As shown in Fig. 2.28, the resonating inductor tunes out the tail capacitance and protects RF signal current from flowing into shunt path. This technique improves conversion gain and flicker noise simultaneously. So this technique is adopted in our design. The significant improvement is presented.
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II. 2.3 Low Power Mixer with Flicker Noise Improved Technique
Fig. 2.29 the proposed low power mixer with low flicker noise
Fig. 2.29 shows the proposed mixer with improved flicker noise. Low power mixer is described in Section I. Improving flicker noise, understanding the physic mechanism in active mixer is first important. From equation (8) and (10), reducing the bias current of LO switch stage and reducing the influence from tail capacitance is the direction. In this request, we use one resonating inductor technique in low power mixer, which is proposed in Section I. As shown in Fig. 2.29, the current reusing in
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RF transconductance stage can reduce the LO bias current and enhance the transconductance of RF stage simultaneously. We would not repeat this part of low power mixer here. In this topology, the low DC current in LO switch stage by current reused in RF stage is achievable. First, lowering the bias current of LO stage is natural by this topology. However, the tail capacitance effect is still existence and generated flicker noise indirectly. Therefore second, tuning out the parasitic capacitance is the best way to improve flicker noise. The parasitic capacitances at the nodes between LO switch stage and RF transconductance stage can be tuned out by resonant inductor at 2fo. We choose small size of LO switch transistors to switch quickly, though the LO switching device suffers from intrinsic flicker noise which inversely to proportional device area. The load is used polysilicon resistor which is free of flicker noise. RF transconductance stage is contributed no flicker noise at output as described before.
The improvement of flicker noise in active low power mixer is significant. This design achieves low power, low cost, moderate gain, linearity, and improving flicker noise in DCR systems. Fig. 2.30 and Fig. 2.31 show the improvement with and without the inductor. Fig. 2.30 is presented the conversion gain is improved by 4 dB.
Fig. 2.31 is shown the flicker noise is reduced and noise figure is decreased 3 dB at 10 MHz.
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Fig. 2.30 The simulated conversion gain with and without resonant inductor L
1000 10000 100000 1E+006 1E+007
Frequency (Hz)
Fig. 2.31 The simulated noise figure with and without resonant inductor L
The important index in flicker noise improvement is the flicker noise corner frequency.
The 1/f flicker noise corner frequency is defined as the frequency where the flicker noise and thermal noise components intersect. The corner is reduced as shown in Fig.
2.31.
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II. 2.4 Chip implementation and measured consideration
Fig. 2.32 shows the layout of the proposed low power mixer with flicker noise improved technique. In order to decrease the degree of mismatches, the layout is as symmetrical as possible. Fig. 2.33 is the die photograph of the proposed low power mixer with improving flicker noise.
Fig. 2.32 Layout of the proposed low power mixer with improving flicker noise
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Fig. 2.33 Die photograph of the proposed UWB low power mixer
The low power mixer is designed for on wafer circuit measurement. So the layout must follow the rule of CIC’s (Chip Implementation Center’s) probe station testing rules. Fig. 2.34 shows the low power mixer for on wafer circuit measurement with four probes.
Fig. 2.34 On wafer circuit measurement
The simple measurement setups are shown in Fig. 2.35 (a-d). We use the RF IC measurement system powered by LabView to measure the linearity and conversion
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power gain of the low power mixer with improving flicker noise.
(a) (b)
(c)
(d)
Fig. 2.35 Measurement setup of the proposed folded mixer with improving flicker noise for (a) input return loss (b) conversion gain and P1dB (c) IIP3 (d) noise figure
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II. 2.5 Measurement results and discussion
This chip size is 1.042*1.102 mm2. In this section, the simulated and measured results are shown below. The low flicker noise and low power mixer consumes 3.8mA and buffer consumes 8.8 mA dc current with 1V supply voltage. Therefore this design dissipates only 3.8 mW in core. This design operating frequency is at 5.2 GHz. Fig.
2.36 shows RF port return loss. RF return loss is below -15 dB at 5.2 GHz. Fig. 2.37 shows LO power versus conversion gain. When LO power is -10 dBm in simulation and -6 dBm in measurement, the conversion gain can obtain the maximum gain. Fig.
2.38 shows P1dB at 5.2 GHz and Fig. 2.39 shows the input third order intercept point (IIP3) with RF frequency 2 MHz separated in measurement. The P1dB is -16 dBm in measurement and -18 in simulation. The IIP3 is -6 dBm in measurement and -8 in simulation. The two illustrations reveal linearity of this mixer. The double sideband (DSB) noise figure is close to 10 dB at 100 MHz in simulation, and in practice, the DSB noise figure is close to 13 dB at 100 MHz. The DSB NF at 10 MHz is 17 dB in measurement and 11.4 dB in simulation as shown in Fig. 2.40. Isolation including LO-to-IF, LO-to-RF, and RF-to-IF are also measured. In LO power is -6 dBm, LO-to-IF isolation is -57 dB, LO-to-RF isolation is -61 dB, and RF-to-IF isolation is -39 dB.
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Fig. 2.36 The simulated and measured RF return loss
-15 -10 -5 0 5
Fig. 2.37 The simulated and measured LO Power versus conversion gain
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Fig. 2.38 The simulated and measured P1dB
-40 -35 -30 -25 -20 -15 -10 -5 0
Fig. 2.39 The simulated and measured input third order intercept point (IIP3)
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0 2 4 6 8 10 12
IF Frequency (10 MHz) 10
11 12 13 14 15 16 17 18
DSB Noise Figure (dB)
Measurement Simulation
Fig. 2.40 The simulated and measured noise figure versus IF Frequency
Because of the moderate layout, the isolation is improved by a wide margin, especially in RF-to-IF. The technique variation is influence in this design. The measured dc in mixer core is higher than simulation, and the measured dc in buffer is lower than simulation. The incomplete EM post-simulation is the reason why the conversion gain is lower than simulation. The target improving flicker noise is achieved in this design.
The simulated and measured results are in Table 2.2. Because the flicker noise is not
The simulated and measured results are in Table 2.2. Because the flicker noise is not