Chapter 1 Introduction
1.2 Thesis organization
In this thesis, the chips are implemented by TSMC 0.18um CMOS technology.
There are four chips designed in this thesis, which included UWB low power low voltage folded mixer, research of flicker noise in low power mixer, and Ultra low voltage mixer. In chapter 2, we discuss UWB low power and low voltage folded mixer, measured result, and design conception from 3.1 GHz to 10.6 GHz. This mixer is used folded topology to reduce supply voltage and achieves wide bandwidth by proper input matching network. Then we introduce flicker noise in mixer first. As follow, many different ways to decrease the influence of the mixer is explained. At last, improving flicker noise technique in low power mixer is proposed. In chapter 3, we discuss Ultra low voltage mixer at 5.2 GHz (802.11a). It utilizes source degeneration to match at 5.2 GHz, and complementary current reusing to lower the supply voltage to 0.6V. In chapter 4, we propose the future work which includes new flicker noise improved techniques.
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Chapter 2
Section I
Low Power and Low Voltage UWB Mixer
I. 2.1 Introduction
In 2002, the FCC opened 3.1 GHz – 10.6 GHz available for UWB applications.
UWB system designs are focused on providing low power, low consumption, low cost, and wideband performance. Compared to UWB mixer, traditional narrow band system and high power mixer should be modified.
One of the important elements in UWB receiver is the down conversion mixer. Fig.
2.1 [1] shows the receiver skeleton. It provides frequency translation from RF to IF.
Many kinds of mixers had proposed in past years in different topologies and technologies. The most popular topology of mixer is the Gilbert cell mixer which had been proposed in 1968 [2]. There are many different technologies with impressive performance for broadband. For example, SiGe-based HBT Gilbert-cell mixers were proposed from dc to 30.5 GHz [3] and from 10 to 42 GHz [4]. Gilbert cell mixers also demonstrated good performances from 9–50 GHz in [5], and 0.3–25 GHz in [6].
Distributed mixer is also proposed for UWB system from 3.1 to 10.6 GHz in [7].
In this section, the low power dissipation, low voltage and broadband mixer is presented. The mixer is based on Gilbert cell mixer and changes the transconductance stage for low power application. And the mixer achieves moderate conversion gain, linearity, noise, and operation at low supply voltage.
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Fig. 2.1 Down conversion receiver [1]
I. 2.2 Low power and low voltage folded mixer
Fig. 2.2 The proposed UWB low power low voltage mixer
Fig. 2.2 shows the schematic of the proposed UWB low power and low supply voltage folded mixer circuit. The mixer is composed of five parts, matching network,
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RF transconductance stage, LO switch stage, loaded resistor, and IF buffer.
Fig. 2.3 shows RF matching network. It composes of C1, L1, R1, L2, and C2 to achieve wide band matching. The LC ladder network can be equivalent to filter to reach broad band frequency response from 3.1 GHz to 10.6 GHz.
Fig. 2.3 RF matching network
In the conventional Gilbert cell mixer, the transistors in the switch stage are stacked on the top of the transistors in the transconductance stage and the load resistor is stacked on the top of the switch stage. In order to achieve low power and low supply voltage, folded type mixer is a good choice. Fig. 2.4 shows the two different transconductors for the folded mixer. Fig. 2.4 (a) is used R stacked on the top of the NMOS to be the transconductance. This type shows some drawbacks. In DC analysis, the current of the NMOS is the sum of flowing through the resistor R and flowing through the switch stage. Then the current through the switch stage can be reduced and the current flowing through the transconductance stage keeps appropriate amount. The folded mixer releases the headroom of the supply voltage. In AC analysis, the current of the NMOS (In) splits to the currents flowing through resistor (Ir) and flowing through the switch (Is). Because that the current flowing through the resistor R is as small as possible to keep sufficient current flowing through loaded stage. In order to reduce the current Ir, the resistor R should be as large as possible. As a result the headroom will be
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limit and the operation region of the transistor M1 should be considered. Fig. 2.4(b) represents the solution of solving the headroom and keeping transistor M1 in the saturation region. The situation that ac current flows into ground through the resistor can be avoided. In DC analysis, it is the same as Fig. 2.4 (a), but the capacitor C can make NMOS and PMOS biasing by oneself, and then reduce the stress of the headroom.
In AC analysis, the currents flowing through the NMOS (In) and flowing through PMOS (Ip) combine to flow through the switch stage (Is). It is a kind of current reuse topologies [8]. The circuit analysis is presented as followed.
(a) (b)
Fig. 2.4 Transconductance stage (a) with resistor stacked on the top of the NMOS (b) with PMOS stacked on the top of the NMOS and bias by oneself
In the biasing of transconductance stage, the supply voltage Vdd must be higher than 1V without capacitor C. The capacitor C can let the NMOS and PMOS biasing in different voltage and reduce the supply voltage Vdd. The supply voltage Vddmin can be expressed as
min ov1 ov3 2 t pdc ndc
Vdd =V +V + V +V −V (1) Vov1 is the overdrive voltage of the transistor M1, Vov3 is the overdrive voltage of the transistor M3, Vt is the threshold voltage of the MOS, Vpdc is the bias voltage of the
Ir
In
Is Is
In Ip
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PMOS, and Vndc is the bias voltage of the NMOS. The threshold voltage of 0.18µm CMOS technology is approximately 500mV. The cautious choice of the Vpdc and Vndc
can obtain the Vddmin. The key is the capacitor C.
In transconductance stage, the advantage of using PMOS instead of resistor can be amplified RF signal. The PMOS is used as current reuse. It can not only supply high gain but also provide a low power. The capacitor C affords ac-coupled in RF signal and to be isolated of PMOS and NMOS in DC. In RF signal, the total gm is equal to gmn + gmp (gmn is the transconductor of NMOS M1 and M2, and gmp is the transconductor of PMOS M3 and M4). Because assuming the switch stage turning on and off is ideal, switch stage can be expressed as Taylor as follows
4 1
Therefore, the conversion gain shown at IF port can be expressed as follows
4 1
The voltage conversion gain of the mixer is shown in [8]
( )
If the LO voltage assumes an ideal square wave. The R is the loaded resistor. Because of the folded type mixer, the DC current flowing through the load R can be reduced.
And the resistor can be as large as possible to achieve higher conversion gain. Hence, the conversion gain will be increased.
Linearity in the mixers is very important. The transistors in switching stage will be cutting off by the large voltage swing at the drain of the M1 and M2 in Fig. 2.2.
Linearity almost completely decides by the input signal dynamic range. In the folded switching mixer with current reuse, the linearity can be improved by decreasing the DC
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drain voltages of the M1 and M3 as Fig. 2.2 [8].
I. 2.3 Chip implementation and measured consideration
Fig. 2.5 shows the layout of the proposed UWB low power mixer. In order to decrease the degree of mismatches, the layout is as symmetrical as possible. Fig. 2.6 is the die photograph of the proposed UWB low power mixer.
Fig. 2.5 Layout of the proposed UWB low power mixer
Fig. 2.6 Die photograph of the proposed UWB low power mixer
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The UWB low power mixer is designed for on wafer circuit measurement with PCB bias network. So the layout must follow the rule of CIC’s (Chip Implementation Center’s) probe station testing rules. Fig. 2.7 shows the UWB low power mixer for on wafer circuit measurement with PCB bias network with four probes.
Fig. 2.7 On wafer circuit measurement with PCB bias network
The simple measurement setups are shown in Fig. 2.8 (a-d). We use the RF IC measurement system powered by LabView to measure the linearity and conversion power gain of the UWB low power mixer. The whole measurement environment in CIC is shown in Fig. 2.9.
(a) (b)
Bond wire Bond wire
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(c)
(d)
Fig. 2.8 Measurement setup of the proposed UWB low power mixer for (a) input return loss (b) conversion gain and P1dB (c) IIP3 (d) noise figure
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(a)
(b)
Fig. 2.9 (a) (b) The whole measurement environment in CIC
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I. 2.4 Measurement results and discussion
This chip size is 1.109*0.83 mm2. By the measured setups illustrated above, the measured results are listed below. The folded low power mixer consumes 2.9mA and the buffer consumes 9mA dc current with 1V supply voltage. Therefore this design dissipates only 2.9mW in core. As shown in Fig. 2.10, the measured RF port input return loss are lower than -10 dB through 3.1-10.6 GHz. As shown in Fig. 2.11, the measured IF port input return loss are lower than -10 dB through 100-528 MHz. Fig.
2.12 (a) ~ (e) shows the conversion power gain with LO power sweeping. It reveals that it only needs -6 dBm in this design to get the maximum gain. In simulation, the conversion power gain has maximum value when LO power is -10 dBm, but in measurement, the power gain has maximum value when LO power is -6 dBm. Fig. 2.13 (a) ~ (h) shows the input P1dB from 3.1 ~ 10.6 GHz with measured -11 dBm and simulated -16 ~ -18 dBm. Fig. 2.14 shows the conversion gain versus frequency from 3.1 ~ 10.6 GHz with LO power -6 dBm (measurement) and LO power -10 dBm (simulation). In measurement, the conversion gain variation in 1 dB from 3.1 ~ 9.5 GHz, and variation in 2 dB from 3.1 ~10.6 GHz. Fig. 2.15 (a) ~ (d) shows the input third order intercept point (IIP3) from 3.1 ~ 10.6 GHz with RF frequency 2 MHz separated in measurement. Because the measured setups are considered the noise of the measurement instrument, the reference level is selected lower and influenced the measured results. Fig. 2.16 shows the isolation from LO port to IF port. The LO_IF isolation is better than -30 dB from 3.1 ~ 10.6 GHz. Fig. 2.17 shows the isolation from LO port to RF port. The LO_RF isolation is better than -40 dB in UWB bandwidth. Fig.
2.18 shows the RF port to IF port isolation. The measured results are unexpected and strongly influenced by improper layout which RF port and IF port are closed.
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Fig. 2.10 The measured and simulated RF return loss
0 2 4 6 8 10 12 14 16
Fig. 2.11 The measured and simulated IF return loss
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Fig.2.12 The measured and simulated conversion gain versus LO power (a) RF frequency at 3.1 GHz (b) RF frequency at 5.1 GHz (c) RF frequency at 7.1 GHz
(d) RF frequency at 9.1 GHz (e) RF frequency at 10.6 GHz
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- 16 - Fig. 2.13 The measured and simulated P1dB
(a) RF frequency at 3.1 GHz (b) RF frequency at 4.1 GHz (c) RF frequency at 5.1 GHz (d) RF frequency at 6.1 GHz (e) RF frequency at 7.1 GHz (f) RF frequency at 8.1
GHz (g) RF frequency at 9.1 GHz (h) RF frequency at 10.6 GHz
3 4 5 6 7 8 9 10 11
Fig. 2.14 The measured and simulated conversion gain versus frequency
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(b) RF frequency at 6.101 and 6.099 GHz
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(c) RF frequency at 9.101 and 9.099 GHz (change chip)
-30 -25 -20 -15 -10 -5 0 5 10
(d) RF frequency at 10.601 and 10.599 GHz (change chip)
Fig. 2.15 The measured and simulated input third order intercept point (IIP3)
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Fig. 2.16 The measured isolation LO_IF versus frequency
3 4 5 6 7 8 9 10 11
Fig. 2.17 The measured isolation LO_RF versus frequency
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Fig. 2.18 The measured isolation RF_IF versus frequency
3 4 5 6 7 8 9 10 11 12 13
Fig. 2.19 The measured and simulated noise figure versus frequency
The measured results shown above reveal the good flatness from 3.1 ~ 10.6 GHz.
The RF and IF port has good matching network and matches to 50 Ω. The measured conversion gain is lower than simulation 2 dB, because the post-simulation is not taking
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all circuit into EM simulation. The measured linearity performances are better than simulation, and it is related to lower conversion gain. Linearity in mixer is dominant by the transconductance of the transconductance stage. CMOS topology as transconductance stage should be biased in moderate region to achieve maximum swing.
In this design, gate bias is 0.68V in NMOS and 0.3 in PMOS. However, the linearity is bad in this bias. In mixers, transconductance dominate the linearity. Transconductance can be expressed as followed
1 2
1 2 3 ...
m m m gs m gs
g =g +g v +g v + (5), which gm1 is the differential of the ID, gm2 is the differential of the gm1, and gm3 is the differential of the gm2. In (5), gm1 dominates the conversion gain and gm3 dominates the linearity. Therefore, the maximum in gm1 and minimum in gm3 can get perfect performance. Fig. 2.20 shows gm1, gm2, and gm3 characteristic versus gate bias with NMOS and PMOS. In Fig. 2.20 (a), the gate bias in this design (0.68V) with fixed PMOS bias at 0.3V is almost the maximum gm3 and not maximum gm1. In Fig. 2.20 (b), the gate bias is 0.7V (1V-0.3V) with fixed NMOS bias at 0.68V, the situation is similar to Fig. 2.20 (a). Linearity and conversion gain is not the optimum value in this bias.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
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Fig. 2.20 Simulated gm1, gm2, and gm3 characteristic versus gate-to-source voltage (a) NMOS (M1) (b) PMOS (M3)
The most significant influences is isolation which is worst than simulation.
Because the improper layout resulted in RF to IF isolation feed-through. The RF signal can easily appear at IF port and the layout should be moderate modified. The measured noise figure is higher than simulation, and some problems happened in here. When measuring the noise figure, the measured results in conversion gain are mismatched to the other measured results which are measured in different ways. Therefore, this data should be measured again to make sure what happened. In mixer stability, this topology should be considered. Assuming the variation of Vpdc and Vndc are small, the variation in V1 which is the drain voltage of the M1 and M3 can be expressed as following equation [8] of NMOS and PMOS, and gms is the transconductance of the switch stage transistor.
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The gms dominates the equation if its value is large enough. And CMOS topology is no need for common mode feedback. However, in practice measurement, the mixer is sensitive in variation of Vpdc and Vndc. Because CMOS transconductance stage input versus output characteristic is as following if Vdd is 1V without capacitor.
0 0.2 0.4 0.6 0.8 1
Fig. 2.21 CMOS input voltage versus output voltage
The moderate operation is only at 0.48V for two transistors. In the abnormal operating region in CMOS, the performance will be limited. In this design, Fig. 2.22 is shown with fixed Vpdc at 0.3V. In measured biasing voltage, the 10% variation of Vndc let CMOS operating out of saturation region. The moderate bias is important in mixer design.
0 0.2 0.4 0.6 0.8 1
Gate bias of NMOS (V) 0
Fig. 2.22 CMOS input voltage versus output voltage with capacitor C
The comparisons of the simulated and measured results are in Table 2.1.
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Table 2.1 Simulated and measured performance of the folded low power mixer Reference
Specification
This Work Sim.
This Work . Meas.
Process CMOS 0.18um CMOS 0.18um
Band width (GHz) 3.1-10.6 3.1-10.6
Supply Voltage(V) 1.0 1.0
RF Return Loss (dB) <-10 <-10
IF Return Loss (dB) <-10 <-10
LO Power (dBm) -10 -6
Conversion Power Gain (dB) 2.3~3.4 0-1.8
LO to RF Isolation -85 -40
LO to IF Isolation -75 -30
RF to IF Isolation -60 -10
DSB NF 10.4~13 16.8~18.2
P1db at 6.1 GHz -16 -11
IIP3 at 3.1 GHz -6 -3
Core Circuit (mW) 2.74 2.9
Buffer (mW) 8.88 9
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Section II
Low Power Mixer with Flicker Noise Improved Technique
II. 2.1 Introduction
Rapid development of wireless communication, the target is low power and low cost system. For receivers of communication system, direct conversion receiver (DCR) is most popular type. In the direct conversion system, flicker noise is strong influenced on noise figure and sensitivity. Some problems are presented for DCR with CMOS technology. The critical problem is the noise influence [1]. And there are important repercussions in DCRs [2]. The flicker noise (1/f) of the mixer degrades SNR (signal-to-noise ratio) at the output baseband.
Because of good isolation, Gilbert cell is the most popular topology for using.
Gilbert cell has good isolation for LO-IF and LO-RF and symmetric balance [3]. For application in Gilbert cell mixer of DCR, the noise is influence in flicker noise. The flicker noise in active mixer is discussed as followed.
II. 2.2 Flicker Noise in Mixers
CMOS transistors suffer from high flicker noise which is inversely proportional to the device area [4]. This is produced from CMOS process and unable avoided. So the size of CMOS transistor is influenced in flicker noise.
Double balanced mixer in DCRs comprises transconductance stage, switch stage with local oscillator, and IF loaded stage. Because flicker noise in RF stage is low frequency noise, it will be up-converted to vicinity of LO frequency. And it will not contribute any flicker noise in DCR systems. Load stage is used of polysilicon resistors which are free of flicker noise. Mismatches in the switch pairs will also
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generate a small amount of flicker noise at the output. Therefore, switch stage is significant contributed flicker noise at baseband [5].
Flicker noise in DCRs is determined in switch pair devices. There are two different mechanisms that generate flicker noise. The first one is direct mechanism, which is generated in the switching transitions. When LO stage commutating motion, it will generate noise pulse trains. Because noise transfer function is linear from each device, the superposition theory holds. The low frequency in switching pairs should be calculated as the voltage source Vn(t). Fig. 2.23 shows the noise pulses resulting in flicker noise at mixer output [6]. Because mixer needs sine wave of local oscillator to drive switching quad, the large sine-wave LO signal accompanies noise. The noise advances or retards the time of zero crossing by ∆t=Vn(t)/S. So the noise pulse trains of random widths ∆t and amplitude of 2I at a frequency of 2ωLO represent at the output.
Fig. 2.23 Noise pulses resulting in flicker noise at mixer output [6]
( )
V tn
t S
∆ = (7)
Over one period, the average of output current is [5]
,
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where I is the bias current of RF transconductance stage, T is the LO period, Vn is the flicker noise of switch pairs, and S is the slope of the LO signal. Weff and Leff are the effective width and length, Cox is the oxide capacitance, f is frequency, and Kf is a process parameter [5]. In the indirect mechanism, capacitance Cp is main determined flicker noise. It can describe as following equation
( )
where Cp is the tail capacitance between LO switch stage and RF transconductance stage with all parasitic capacitance. T is the LO period, gms is the transconductance of LO switches, ωLO is the frequency of local oscillator, and Vn is equivalent flicker noise of LO switches [5].
So, there are some topologies to reduce flicker noise from above equation. From (8), increasing the slope of the LO signal and reducing the equivalent flicker noise of switching transistors can alleviate the influence. It needs to increase sizes of the switch transistors. However, it has some drawbacks. The large sizes of switching transistors increase the parasitic capacitance at common source of switch stage and increase the flicker noise indirectly.
Reduction of bias current of the switch stage can lower the noise pulses and improve flicker noise. Conventional Gilbert cell with current bleeding is proposed in Fig. 2.24. However, this technique has some important drawbacks. When reducing the biasing current of the switch pairs, the impendence as seen from RF transconductance stage into switch stage (1/gms) will be increased. It allows more RF leakage current flowing into the bleeding circuit. The leakage current will also be shunt by the parasitic capacitance at the node between RF stage and switch stage.
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This decreases the gain and reduces the mixer linearity. The dynamic current bleeding circuit is proposed to solve the problems [6]. Fig. 2.25 is presented the conventional Gilbert cell mixer with dynamic current bleeding.
Fig. 2.24 Conventional Gilbert cell with current bleeding
Fig. 2.25 Conventional Gilbert cell with dynamic current bleeding
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Since the noise pulse trains is only present at the switching instant of LO switch quads. A dynamic current bleeding is injected to the core through a switch control circuit at the switching instant of switch pairs. Fig. 2.26 shows the theory and idea for dynamic current bleeding [6]. The switching event controls by the nodes at common
Since the noise pulse trains is only present at the switching instant of LO switch quads. A dynamic current bleeding is injected to the core through a switch control circuit at the switching instant of switch pairs. Fig. 2.26 shows the theory and idea for dynamic current bleeding [6]. The switching event controls by the nodes at common