The circuit performance of the two proposed on-chip transient detection circuits has been investigated by the simulation tool HSPICE. The device size of transient detection circuits can be optimized by using HSPICE. From the simulation results, the output voltage level of both new proposed on-chip transient detection circuits can changed from logic 0 to logic 1 after system-level ESD and EFT events. Therefore, these two circuits can detect the positive and negative fast electronic transients disturbed on the VDD or VSS lines. Furthermore, two proposed on-chip transient detection circuits can memorize the occurrence of system-level ESD and EFT events.
Chapter 2
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Fig. 2.1 The previous on-chip transient detection circuit realized with (a) sensor units and
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Fig. 2.2 Measured VDD waveforms under system-level ESD tests with ESD voltage of (a) +1000V and (b) -1000V.
Fig. 2.3 The specific time-dependent underdamped sinusoidal waveforms applied on the power and ground lines to simulate the disturbance under system-level ESD zapping.
Chapter 2
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Fig. 2.4 Measured voltage waveforms of a single pulse on 50Ω under EFT tests with EFT voltage of (a) +200V and (b) -200V.
Fig. 2.5 The specific time-dependent exponential pulse waveform applied on the power lines to simulate the disturbance under EFT zapping.
Fig. 2.6 Schematic diagram of the proposed new transient detection circuit I.
Chapter 2
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Fig. 2.7 Simulated VDD, VSS, VRESET and VOUT waveforms of the transient detection circuit I
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Fig. 2.8 Simulated VDD, VSS, VRESET and VOUT waveforms of the transient detection circuit I with negative-going underdamped sinusoidal voltage on both VDD and VSS. (a) The undershooting amplitude on VDD is larger than that on VSS (b) The undershooting amplitude
Chapter 2
Fig. 2.9 Different coupling path from the ESD zapping source to VDD and VSS pins of CMOS IC on the PCB.
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Fig. 2.11 Simulated VDD, VSS, VRESET and VOUT waveforms of the transient detection circuit I under (a) positive-going underdamped sinusoidal voltage on both VDD and VSS with 5ns delay time and under (b) negative-going underdamped sinusoidal voltage on both VDD and VSS with
Chapter 2
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Fig. 2.12 Simulated VDD, VRESET and VOUT waveforms of the transient detection circuit I
Fig. 2.13 Schematic diagram of the new transient detection circuit II realized with a feedback loop.
Chapter 2
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Fig. 2.14 Simulated VDD, VSS, VRESET and VOUT waveforms of the transient detection circuit II with (a) positive-going underdamped sinusoidal voltage and with (b) negative-going
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Fig. 2.15 Simulated VDD, VSS, VRESET and VOUT waveforms of the transient detection circuit II under (a) positive-going underdamped sinusoidal voltage on both VDD and VSS with 5ns delay time and under (b) negative-going underdamped sinusoidal voltage on both VDD and VSS with 5ns delay time.
Chapter 2
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Fig. 2.16 Simulated VDD, VRESET and VOUT waveforms of the transient detection circuit II
Chapter 3
Measurement Setup and Measurement Results of Transient Detection Circuits
3.1. Background
During system-level ESD tests, the high-energy ESD-induced noise on the power (VDD) and ground (VSS) lines often leads to frozen states or malfunction of the EUT. In the standard of IEC 61000-4-2, there are two kinds of test modes have been specified: contact-discharge test mode and air-discharge test mode. It is difficult to evaluate the immunity of “single”
CMOS IC inside the EUT by using ESD gun under the system-level ESD tests, even though the IEC 61000-4-2 standard has been adopted as reliability test method of microelectronic products by most international companies. The quantity of energy induced by system-level ESD zapping is hard to evaluate in the experiments because of different box shielding and PCB layout designs applied on the microelectronic products. To solve this problem, a component-level transient induced latchup (TLU) test for system-level ESD consideration has been investigated [13]-[16]. In the measurement setup of TLU tests, the ESD trigger source can only apply the ESD-induced energy on the VDD power line. Nevertheless, the measurement setup still can be used as an efficient method to investigate the system-level ESD immunity of CMOS IC. In this chapter, the new proposed on-chip transient detection circuits are fabricated in a 0.18-μm CMOS process with 3.3-V devices. The die photos of two proposed on-chip transient detection circuits are shown in Fig. 3.1 (a) and (b), respectively.
The circuit performance of the circuits has been evaluated by TLU tests, system-level ESD tests, and EFT tests, respectively.
Chapter 3
3.2. Transient Induced Latchup (TLU) Test
There are several advantages of the TLU tests. First, it can easily evaluate the immunity of “single” CMOS IC by the measured voltage/current waveforms through oscilloscope.
Secondly, it can provide accurate simulation and high accuracy without over estimation for ESD-generated voltage disturbed on the CMOS ICs under system-level ESD tests. Through the TLU measurement setup, positive-going or negative-going underdamped sinusoidal voltages similar with the waveforms generated from ESD gun under system-level ESD tests can be provide by setting positive or negative charged voltage levels.
3.2.1. Measurement Setup
The measurement setup of TLU test is shown in Fig. 3.2 and 3.3. An electrostatic discharge simulator is used as a trigger source and it can generate the ESD-like energy to apply the underdamped sinusoidal voltage which is similar to the waveforms generated by ESD gun. A capacitor of 200pF is employed as the charging capacitor, as the same value used in machine model (MM) ESD test. This capacitor can store the energy (Vcharge) generated from the electrostatic discharge simulator and then the stored charge can be discharged to the DUT through the relay. Therefore, by setting positive (negative) Vcharge value, a positive-going (negative-going) underdamped sinusoidal voltage can be generated to simulate the transient disturbance on the power pins of CMOS ICs under system-level ESD test. Finally, the transient VDD or IDD waveforms can be measured through the digital oscilloscope with voltage and current probes. Noteworthiness, a 5Ω resistor is located between the DUT and power supply to avoid electrical-over-stress (EOS) damage on the DUT under a high current latchup state. In previous studies, the usage of a small current-limiting resistance, instead of a
3.2.2. Measurement Results of Transient Detection Circuit I
Fig. 3.4 (a) and (b) show the measured VDD and VOUT waveforms of the on-chip transient detection circuit I under TLU tests, respectively. The VDD power line of the on-chip transient detection circuit I is disturbed with ESD-induced noise under TLU test. Therefore, the VDD
power line would not maintain its normal voltage level of 3.3V, but rapidly increase (decrease) from 3.3V under TLU test with positive (negative) Vcharge. The VOUT voltage level is simultaneously affected by the ESD-generated transient noise. Under TLU test with Vcharge of +9V, a positive-going underdamped sinusoidal waveform can be generated on VDD power line, as shown in Fig. 3.4 (a) Under TLU test with Vcharge of -1V, a negative-going waveform can be generated on VDD power line likewise, as shown in Fig 3.4 (b). After TLU tests with positive and negative Vcharge, the output voltage level of on-chip transient detection circuit I can be changed from 0V to 3.3V.
3.2.3. Measurement Results of Transient Detection Circuit II
The measured VDD and VOUT waveforms of the on-chip transient detection circuit II under TLU tests with positive and negative Vcharge are shown in Fig. 3.5 (a) and (b), respectively. Under TLU tests, the power line would not maintain its normal voltage, but an underdamped sinusoidal voltage instead. As shown in Fig. 3.5 (a), under positive ESD stress with Vchage of +11V, VDD rapidly increases from 3.3V to a high peak voltage and the output is disturbed with the positive-going underdamped sinusoidal voltage waveform at the same time.
After TLU test with positive Vcharge, the output voltage level is changed from 0V to 3.3V. As shown in Fig. 3.5 (b), under negative ESD stress with Vchage of -3V, VDD rapidly reduces from 3.3V to a low peak voltage and the output is disturbed with the negative-going underdamped sinusoidal voltage waveform simultaneously. After TLU tests with negative Vcharge, the output voltage level is changed from 0V to 3.3V.
Chapter 3