ESD is an increasingly important reliability issue on CMOS IC products, especially in the advanced technology. Many international associations, such as ESDA (Electrostatic Discharge Association), AEC (Automotive Electronics Council), EIA (Electronic Industries Alliance), JEDEC (Joint Electron Device Engineering Council), MIL-STD (US Military Standard), etc, draw up the different ESD standards for all kinds of ESD conditions. All of the international standards which have been described above are component-level ESD standards.
The component-level ESD standards defined the test environment, test methods, and the corresponding ESD test level. In order to verify the robustness of CMOS ICs under system-level ESD events, many international companies adopt other specifications, such as IEC 61000-4-2 (ESD events) and IEC 61000-4-4 (EFT events). IEC 61000-4 is a part of the IEC 61000 series, and the mainly contents of part4 is about testing and measurement techniques. In this section, the international standards are described below.
1.2.1. IEC 61000-4-2 Specification
The object of the standard, IEC 61000-4-2 is to establish a common and reproducible basis for evaluating the performance of CMOS ICs inside the electrical/electronic microelectronic products. This standard specifies typical waveform of the discharge current, test levels, test equipment, test set-up, and test procedure. In order to verity the disturbance of
to the discharge electrode, which is shown in Fig. 1.2. Otherwise, the equivalent circuit of human body model is shown in Fig. 1.1(b). To compare two equivalent circuits, the storage capacitor in Fig. 1.1 (a) is 150pF, and that in Fig. 1.1 (b) is 100pF. Therefore, the ESD-induced energy stored in the system-level ESD condition is lager than that in the component-level ESD condition. The discharge resistors used in the Fig. 1.1 (a) and (b) are 330Ω and 1.5kΩ, respectively. Therefore, the ESD-induced energy generating from ESD gun in system-level ESD tests has faster rise time than that in component-level ESD tests. Fig. 1.3 shows the typical waveforms of the discharge current under system-level ESD test (IEC 61000-4-2) and component-level ESD test (MIL-STD 883). Under 8-kV ESD zapping condition, the peak current in system-level ESD test is about five times larger than that in component-level ESD test. In order to compare the test results obtained from different ESD generators, the characteristics of the waveform of discharge current is listed in Table I and shown in Fig. 1.3. Table II shows the test level (test voltage) of component-level ESD test, such as HBM, MM, and CDM. The system-level ESD test levels with contact discharge and air discharge test modes are shown in Table III. Contact discharge is the preferred test method, and air discharge shall be used where contact discharge can not be applied. It is not intended to imply that the test severity is equivalent between contact discharge and air discharge test modes. To compare Table III with Table II, the test voltage of system-level ESD is lager than component-level ESD, no matter with contact discharge or air discharge. Noteworthiness, the voltage waveforms are different for each method due to the different test methods of test.
According to those phenomena, system-level ESD tests are more significant to affect the system operation of the microelectronic products than component-level ESD tests. Table IV shows the evaluation of system-level ESD test results, the test results shall be classified in terms of loss function or degradation of performance of the EUT. In the evaluation table, the microelectronic product should reset itself automatically after system-level ESD test to pass
Chapter 1
conditions to avoid unnecessary influence from electromagnetic environment of the laboratory.
The measurement setup of system-level ESD test is shown in Fig. 1.4 and the elaboration of this will follow in chapter 3.
1.2.2. IEC 61000-4-4 Specification
IEC 61000-4-4 is an international standard which gives immunity requirements and test procedures related to electrical fast transients (EFT) [8]. EFT disturbances are common in industrial environment where electromechanical switches are used to connect and disconnect.
The EFT test is intended to demonstrate the immunity of electronic equipments to transient disturbances such as those originating from switching transients (interruption of inductive loads, relay constant bounce, etc.).
The equivalent circuit diagram of the EFT generator is shown in Fig. 1.5 and the major elements of the EFT test generator are listed in Table V. In particular, the impedance matching resistor Rm (50Ω) and the DC blocking capacitor Cd (10nF) are defined in the standard. The charging capacitor Cc is used to store the charging energy and Rc is the charging resistor. The Rs is used to shape the pulse duration. The effective output impedance of the generator shall be 50Ω.
During EFT tests, the power lines of the CMOS ICs inside the microelectronic products no longer maintain their initial voltage levels. A number of fast transients would couple into power, ground, and I/O pins randomly causing the ICs inside the EUT to be upset or frozen after EFT zapping. The characteristics of such a high-voltage-level EFT-induced disturbance are listed in Table VI and shown in Fig.1.6. The test voltage waveforms of these fast transients are defined in the standard with the repetition frequency of 5kHz and 100kHz. A burst is
100kHz, there are seventy-five pulses in each burst and the burst duration time is 0.75ms.
The rise time and duration of a single pulse voltage waveform must accord with the characteristics which are listed in Table VII and shown in Fig. 1.7. A voltage pulse waveform with rise time of 5ns±30% and duration of 50±30% occurs on the pins of EUT under EFT tests. The EFT test levels for testing power supply ports and for testing I/O, data, and control ports of the equipment are listed in Table VIII. The voltage peak for I/O, data, and control ports is half of the voltage peak for testing power supply ports. Level “X” is an open level, and is specified in the dedicated equipment specification.