In Fig. 4.3, decoupling capacitances widely ranging from 1pF to 0.1μF are investigated the system-level ESD detection level of the on-chip transient detection circuit with different board-level noise filters. The definition of system-level ESD detection level is that minimum ESD voltage can cause transition at the output of on-chip transient detection circuit from 0V to 3.3V. Due to TLU test is the adopted measured method in this work, the system-level ESD detection level is expressed as VCharge. Furthermore, the system-level ESD detection level is dependent on the voltage level zapped into the CMOS ICs inside the DUT. For proposed on-chip transient detection circuits, the combined different noise filter networks can provide different abilities to reduce ESD-induced disturbance on VDD/VSS lines and cause the detection function triggered under different ESD zapping voltages. In the following analyses, different types of board-level noise filters combined with the new proposed on-chip transient detection circuit I shown in Fig. 2.6 have been investigated. Fig. 4.3 shows the relations between the decoupling capacitance of the capacitor and system-level ESD detection level of the proposed on-chip transient detection circuit I under TLU tests. As shown in Fig. 4.3, larger capacitance of decoupling capacitor responses to higher system-level ESD detection level. By using larger decoupling capacitor in noise filter networks, the higher ESD-induced energy must be zapped into the DUT to trigger on the detection function of proposed on-chip transient detection circuit. Therefore, for the on-chip transient detection circuit, the system-level ESD detection level can be adjusted by combining different noise filter networks.
Fig. 4.4 shows the measurement results of proposed on-chip transient detection circuit I combined with 3rd-order π-section noise filter network shown in Fig. 4.2 (b) under TLU tests.
There are two different resistances of 5Ω and 100Ω used in the 3rd-order noise filter network,
Chapter 4
measured results shown in Fig. 4.4, larger decoupling capacitance responses to higher system-level ESD detection level (Vcharge). For example, by using π-section noise filter consisting of a 100Ω resistor and two 0.1μF capacitors, the positive system-level ESD detection level (Vcharge) can be enhanced more than +400V. Furthermore, in this work, a 5Ω resistor and a 100Ω resistor are used in the 3rd-order π-section noise filters with the same capacitance of capacitor, respectively. The π-section noise filter with the 100Ω resistance can provide higher system-level ESD detection level than that with 5Ω resistance.
For the proposed on-chip transient detection circuit I combined with the board-level 2nd-order RC noise filter network, Fig. 4.5 shows the measurement results of the system-level ESD detection level. Two kinds of RC noise filters are used to verify the performance of suppressing the ESD-generated voltage under TLU tests. For two RC noise filters, one consists of a 5Ω resistor, and the other consists of a 100Ω resistor. The decoupling capacitances are the same in both RC noise filters. The capacitances widely ranging from 1pF to 0.1μF are used to investigate the system-level ESD detection level of the on-chip transient detection circuit combined with RC noise filters. From the measured results shown in Fig. 4.5, the efficiency of RC noise filter with 100Ω resistor to against the ESD-induced noise is better than that with 5Ω resistor. If the resistance is fixed, the larger capacitance of the capacitor used in the RC noise filter network will response to the higher system-level ESD detection level (Vcharge), as shown in Fig. 4.5.
In order to reduce the capacitance used in the RC noise filter networks, a modified noise filter network shown in Fig.4.2 (d) is proposed. The original RC noise filter shown in Fig.
4.2(c) is named as type-I RC noise filter, and the modified noise filter is named as type-II RC noise filter. For the same RC time constant, the capacitance of the capacitor in the type-II RC
simultaneously under system-level ESD tests. The resistor located between VSS line and ESD trigger source is needed to against the ESD-induced energy coupled on VSS line. Fig. 4.6 shows the system-level ESD detection level characteristics of the on-chip transient detection circuit combined with type-II RC noise filter under TLU tests. Two capacitances (10pF and 100pF) are used in the type-II RC noise filter network, separately. The system-level ESD detection level is strongly dependent on the capacitance of the capacitor used in the type-II RC noise filter while the resistance is fixed. In addition, the larger resistance used in type-II filter can cause higher system-level ESD detection level. Compared with the measured results in Fig. 4.5 and Fig. 4.6, the type-I RC noise filter consisted with 5Ω resistance and 600pF capacitance response to 15-V system-level ESD detection level (Vcharge), but the type-II RC noise filter consisted with 150Ω resistance and only 10pF capacitance can achieve approximate level. Therefore, type-II RC noise filter can reduce the capacitance on the RC noise filters, no matter for positive and negative Vcharge under TLU tests. Such board-level type-II RC noise filter can be further integrated into chip design to effectively enhance the system-level ESD detection level of CMOS ICs.
4.4. Conclusion
By choosing proper noise filter networks, the ESD-induce energy (voltage) zapped into the CMOS ICs inside the EUT can be suppressed effectively. The performance of different type noise filters against the ESD-induced transient noise have been measured and analyzed under TLU tests. The 3rd-order π-section noise filter networks can enhance the system-level ESD detection level of on-chip transient detection circuit better than the 2nd-order type-I RC noise filter under TLU tests. Otherwise, the type-I RC noise filter can enhance the detection level more efficiently than the 1st-order noise filter. The compared measurement results among different type noise filter networks are shown in Fig. 4.7. For different noise filter
Chapter 4
ESD detection range of the on-chip transient detection circuit. The higher order of noise filters can more effectively enhance system-level ESD detection level, no matter for positive or negative ESD events. Therefore, the board-level noise filters can be combined with the proposed on-chip transient detection circuit to adjust the system-level ESD detection range.
Fig. 4.8 (a) and (b) show the measured VDD and VOUT waveforms under positive and negative TLU tests with VCharge of +9V and -1V, respectively. In the TLU tests, the on-chip transient detection circuit I is combined with noise filter network. The measured results shown in Fig.
4.8 (a) and (b) can be compared with transient waveforms shown in Fig. 3.4 (a) and (b).
Because noise filter network can effectively suppress the ESD-generated energy, the output voltage of transient detection circuit still maintains at 0V under TLU tests with the same Vcharge. Therefore, by combining the noise filter network properly, the on-chip transient detection circuit can adjust the system-level ESD detection level.
Fig. 4.1 Modified measurement setup of component-level transient induced latchup (TLU) test.
Fig. 4.2 Four types of noise filter networks investigated for their improvement on system-level ESD detection level: (a) capacitor filter, (b) π-section filter, (c) type-I RC filter,
Chapter 4
Fig. 4.3 Relations between the decoupling capacitance of the capacitor filter and system-level ESD detection level (Vcharge) of the proposed transient detection circuit under both positive and negative TLU test.
Fig. 4.5 Relations between the decoupling capacitance of the type-I RC filter and system-level ESD detection level (Vcharge) of the proposed transient detection circuit under both positive and negative TLU test.
Fig. 4.6 Relations between the resistance of the type-II RC filter and system-level ESD detection level (Vcharge) of the proposed transient detection circuit under both positive and
Chapter 4
Fig. 4.7 Relations between the decoupling capacitance and system-level ESD detection level (Vcharge) of the proposed transient detection circuit under three types of noise filter networks:
capacitor filter, type-IRC filter, π-section filter.
(a)
(b)
Fig. 4.8 Measured VDD and VOUT transient responses on the proposed on-chip transient detection circuit I with noise filter under (a) positive and (b)negative TLU test with Vcharge of +9V and -1V, respectively.
Chapter 5
Chapter 5
Design of On-Chip Transient-to-Digital Converter
5.1. Background
In chapter 2 and chapter 3, the proposed on-chip transient detection circuits have been designed and fabricated in a 0.18-μm technology with 3.3-V devices. From the simulation and measurement results, the proposed transient detection circuits can successfully detect positive/negative fast electrical transients on the power and ground lines under system-level ESD tests. In chapter 4, different types of board-level noise filter networks have been evaluated the ability to suppress the system-level ESD-induced energy on the power and ground lines. The higher order noise filter applied between the power and ground lines can provide better suppressed ability to reduce the ESD-induced energy zapping into the CMOS ICs. By choosing adaptable noise filter networks to combine with the transient detection circuits, the quantity of the ESD-induced energy zapping into the transient detection circuits on the power or ground lines can be further controlled. In this chapter, different noise filters combined with the proposed transient detection circuit has been designed and investigated under system-level ESD tests. Even with the same ESD zapping voltage, the different noise filters between the ESD trigger source and the transient detection circuit would provide different suppression on the ESD-induced energy. Under system-level ESD tests with smaller ESD voltages, the proposed on-chip transient detection circuit combined with higher-order noise filter network would not easily change the stored logic state, but that with lower-order noise filter network can easily change the logic state from logic 0 to logic 1. Therefore, the
microelectronic products under system-level ESD tests can be quantified as digital thermometer codes.