work. The measurement setup for EFT tests combined with attenuation network is shown in Fig. 3.9. The EFT generator is connected to the EUT through the attenuation network. The VDD and VOUT transient responses of the on-chip transient detection circuits can be monitored by the digital oscilloscope. Thus, the influences on power lines and the transient detection function under EFT tests can be directly evaluated with the measurement setup of EFT test with attenuation network.
3.4.2. Measurement Results of Transient Detection Circuit I
Fig. 3.10 (a) and (b) show the measured transient waveforms of VDD and VOUT of transient detection circuit I under positive and negative EFT tests, respectively. Before each EFT voltage zapping, the initial output voltage (VOUT) of the proposed on-chip transient detection circuit I is reset to 0V. During the EFT tests with positive and negative EFT voltage, VDD and VOUT of the transient detection circuit I are disturbed simultaneously with the exponential voltage waveforms. Thus, VDD increases (decreases) rapidly from its initial value of 3.3V under positive (negative) EFT tests. After EFT tests with attenuation network, the output voltage of the transient detection circuit I transits from 0V to 3.3V.
3.4.3. Measurement Results of Transient Detection Circuit II
Fig. 3.11 (a) and (b) show the measured transient waveforms of VDD and VOUT of transient detection circuit II under positive and negative EFT tests, respectively. Before each EFT voltage zapping, the initial output voltage (VOUT) of the proposed on-chip transient detection circuit II is reset to 0V. During the EFT tests with positive and negative EFT voltage, VDD and VOUT of the transient detection circuit II are disturbed simultaneously with the exponential voltage waveforms. Thus, VDD increases (decreases) rapidly from its initial value of 3.3V under positive (negative) EFT tests. After EFT tests combined with attenuation
Chapter 3
3.5. Conclusion
The two new proposed on-chip transient detection circuits have been fabricated in a 0.18-μm CMOS process with 3.3-V devices. These circuits have been investigated and designed with the HSPICE simulator tool. Three test methods including TLU test, system-level ESD test, and EFT test are adopted to verify the circuit performance of proposed on-chip transient detection circuits. From the experimental results, the outputs of two transient detection circuits can transit from 0V to 3.3V after voltage zapping. Therefore, it has been confirmed that the transient detection circuits can detect and memory the occurrence of the positive (negative) fast electrical transients on the power and ground lines of CMOS ICs.
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Fig. 3.1 Die photos of (a) transient detection circuit I and (b) transient detection circuit II.
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Fig. 3.2 Measurement setup of component-level transient induced latchup (TLU) test.
Fig. 3.3 Measurement instruments of component-level transient induced latchup (TLU) test.
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Fig. 3.4 Measured VDD and VOUT transient responses on the proposed on-chip transient detection circuit I under TLU test with (a) Vcharge of +9V and (b) with Vcharge of -1V.
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Fig. 3.6 Measurement setup of system-level ESD test with indirect contact discharge mode.
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Fig. 3.8 Measured VDD and VOUT transient responses on the proposed on-chip transient detection circuit II under system-level ESD test with (a) ESD voltage of +0.2kV and with (b)
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Fig. 3.9 Measurement setup of EFT test combined with attenuation network.
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Fig. 3.10 Measured VDD and VOUT transient responses on the proposed on-chip transient detection circuit I under EFT test with (a) positive EFT voltage and with (b) negative EFT
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Chapter 4
Evaluation on Transient Detection Circuit with Board-Level Noise Filter Networks
4.1. Background
It has been reported that, by choosing proper components in the board-level noise filters, the ESD immunity of CMOS ICs can be significantly enhanced under system-level ESD tests [10]. The usage of board-level noise filters between the noise source and CMOS ICs can decouple, bypass, or absorb noise voltage (energy) such as bi-polar transient waveform.
“Bi-polar” waveform means that the polarity of the voltage waveform can be varied between positive and negative with time repeatedly. The bi-polar transient waveforms are similar with the underdamped sinusoidal waveforms disturbed on the power and ground lines under system-level ESD tests. The domain parameters of the bi-polar transient waveform disturbed on the power and ground lines of CMOS ICs under system-level ESD tests include frequency, damping factor, and transient peak voltage. According to the previous investigations on board-level noise filters, the purpose of this chapter is to develop an effective board-level noise filter network to reduce the ESD energy zapped into the DUT under system-level ESD tests. Different types of board-level noise filters have been evaluated to find their improvement on reducing ESD-induced energy, including capacitor filter, LC-like (2nd-order) filter, π-section (3rd-order) filter, etc. These noise filters can be used to appropriately improve the ESD immunity of DUT under system-level ESD tests. Some board-level noise filters can be even integrated into the chip design to further achieve the system-on-chip (SOC) design and reduce the cost of microelectronic products. Furthermore, the proposed on-chip transient detection circuits have been verified in a 0.18-μm technology with 3.3-V devices successfully.
Chapter 4
memorize the occurrence of the fast electrical transients disturbance on the power and ground lines of CMOS ICs. Therefore, board-level (chip-level) noise filters with proper components can reduce high ESD energy zapped into the proposed on-chip transient detection circuits.
4.2. Different Types of Board-Level Noise Filters to Suppress Bi-Polar