2.5 Conclusions
From SIMS measurement, it exhibits that there are high dopant dosages pilled up at the M/S interface due to the dopant segregation phenomenon even under low thermal budget 2nd RTA control. This factor could limit the implantation damage mainly occurred in the silicide layer and provide a better M/S interface. C-V measurement shows that with higher 2nd RTA temperatures at the range 400 to 650℃, higher activation could be achieved at the M/S interface for both boron and phosphorous doped samples. Ohmic contact property could be found in I-V measurements, with higher 2nd RTA temperatures between 400 to 550 ℃ , lower contact resistances are present. AFM inspections shows that no agglomeration of silicide film is occurred under 700 ℃ 30s. From these results, 2nd RTA 500 to 600℃
30s may be a good process window for IIS method to future integration with high-k dielectric device.
14
References
[1] G..D. Wilk, R. M. Wallace, and J. M. Anthony: J. Appl. Phys., Vol. 89, pp. 5243, (2001).
[2] C.S. Kang, H.J. Cho, R. Choi, Y.H. Kim, C.Y. Kang, S.J. Rhee, C. Choi, M.S. Akbar, and J.C. Lee:
Electron Devices, IEEE Transactions on, Vol. 51, Issue 2, pp. 220, (2004).
[3] B.J. Pawlak, R. Lindsay, R. Surdeanu, P.A. Stolk, K. Maex: Proceedings of the 14th International Conference on Ion Implantation Technology, pages X, (2002).
[4] M.J.P. Hopstakena, Y. Tamminga, M.A. Verheijen, R. Duffy, V.C. Venezia, A. Heringa: Applied Surface Science, Vol. 231–232, pp. 688, (2004).
[5] R. Lindsay, K. Henson, W. Vandervorst, K. Maex, B.J. Pawlak, R. Duffy, R. Surdeanu, P. Stolk, J.A. Kittl, S. Giangrandi, X. Pages and K. van der Jeugd: J. Vac. Sci. Technol. B, Vol. 22, No. 1, pp. 306 (2004).
[6] Dieter K. Schroder: “Semiconductor material and device characterization”, second edition, John Wiley & Sons, Inc. 1998.
[7] J.S. Blakemore: Solid-State Electronics, Vol. 25, pp. 1067, (1982).
[8] A. Lauwer, J.A. Kittl, M.J.H.V. Dal, O. Chamirian, M.A. Pawlak, M. de Potter, R. Lindsay, T.
Raymakers, X. Pages, B. Mebarki, T. Mandrekar, and K. Maex: Materials Science and Engineering B, Vol. 114-115, pp. 29, (2004).
[9] C.C. Wang and M.C Chen: J. J. Appl. Phys. Vol. 45, pp. 1582, (2006).
[10] A. S. Wong, D. Z. Chi, M. Loomans, D. Ma, M.Y. Lai, W. C. Tjiu, S. T. Chua, C. W. Lim, and J.
E. Greene: Appl. Phys. Lett., Vol. 81, pp. 5138, (2002).
Fig. 2.1. SIMS profile of the BF2 doped p-type substrate, with 2nd RTA 400℃ 30s.
The dopant segregation phenomenon can be found at about 23nm from surface. The shadow area from 23nm to about 50nm is about 5x1012 cm-2, which is defined as dopant implanted in Fig. 2.3.
16
Fig. 2.2. Boron concentrations at different 2nd RTA temperatures extracted by C-V method
Fig. 2.3. Dopant (cm-2) as the integral of the concentration over depths from C-V and SIMS profile (dopant activated and dopant implanted) versus different 2nd RTA temperatures.
18
Fig. 2.4. Phos. concentration (cm-3) calculated from C-V measurement, and activated dopant (cm-2) as the integral of the concentration over depths from C-V measurement at different 2nd RTA temperatures.
Fig. 2.5. I-V characteristics of boron doped samples. All samples with 2nd RTA behave more likely to ohmic contacts than schottky contacts.
20
Fig. 2.6. AFM images show NiSi surface morphology with 30 second 2nd RTA at (a) 400 ℃ (b) 500 ℃ (c) 600 ℃ (d) 700 ℃.
Chapter 3 N
+/P J UNCTION
3.1 Brief Introduction and Design Idea
Based on our previous work [1], we could conclude that even at very low dosage (1x1013 cm-2), dopant activated at the silicide/silicon interface could drive the MS junction to become ohmic like. These experiment results showed that even with low temperature thermal treatment, junction formed by IIS [2-4] technique still had high dopant activation ability. But what is most important to us is that why IIS technique could exhibit this unusual property? There are no researches to answer this mechanic before.
To answer this question, first of our assumption is refer to the SPER [5-8]
process. SPER process gives a good explanation of why dopant can be activated at lower temperature than traditional junction formation process. If there any linkage between SPER and IIS techniques? It is known that there will be an amorphous layer formed at silicide/silicon interface during the silicidation process. It is reasonable that what is happened in SPER process will also occur in IIS process. This provides the base of low temperature activation behavior for IIS technique. In addition, IIS usually needs less activation temperature comparing to SPER process. Our second assumption to the IIS technique is that silicide could lower the energy required for the SPER process. This factor is less discussed in CMOS process, but for TFT process, metal induced crystallization or lateral crystallization (MIC/MILC) is often been studied.
At this part, heavily doped phosphorous (5x1015 cm-2) is applied to our test device. Such a high dosage is commonly adapted in the traditional junction
22
fabrication process. The projection range of the implantation was designed to locate in the silicide to let the implantation damage in silicon be minimized. The constraint for thermal treatments is the same as that in the chapter 1. Different to the metal/silicon interface discussed in chapter 1, chapter 2 focus on the silicide/N+/P test structures.
3.2 Device Fabrication
3.2.1 Device fabrication for I-V, C-V, SIMS measurements
Thirty-nanometer silicon dioxide was thermally grown on (100) p-type silicon wafer as the isolation oxide, after defining the active region, a 20nm nickel film was then deposited by E-gun evaporation system. All samples were treated with 1st RTA 350℃ 30s, after un-reacted Ni was removed, all samples were ion implanted with phosphorous (doping density: 5x1015 cm-2), followed different 2nd RTA temperature treatments 60 seconds from 400℃ to 650℃, 50℃ per step. At the final step, Al was thermally coated as back contact. No post metal annealing was treated for thermal budget control consideration.
3.2.2 Device fabrication for FPP measurements
For four points probe test structure, starting material was (100) p-type silicon wafer, too. After thermal oxidation and active regions definition, 20nm nickel was deposited by e-gun system. Following processes were the same as described in section 3.2.1. However, for FPP test structure, after 2nd RTA, NiSi was removed using silicide etch solution (the etch selectivity of NiSi to bare Si is larger than 50). At the final step, Al was thermally coated as back contact. No post metal annealing was treated for thermal budget control consideration.
3. 3 Results and Discussions 3.3.1 C-V measurement
The effective phosphorous concentration (Neff) estimated from C-V measurement [9] is demonstrated in Fig. 3.1. The measured capacitance is composed by of three different capacitances in series, silicide/silicon (M/S) junction capacitance, N+/P junction capacitance, and back contact capacitance. Based on the results in chapter 2 (see also reference 10), it shows that there present a high dopant activation level at the M/S interface formed by IIS method, either it will become an ohmic contact or exits a relative large capacitance compared to the N+/P junction capacitance where the lightly doped substrate dominate the small capacitance value. The M/S capacitance term could be neglect with little influence in the analysis. On the other hand, the area of the back contact is about the full wafer size, which is several orders of magnitude larger than the area of N+/P junction, so the capacitance at the back contact can also not take into consideration. As the result, the measured capacitance was mainly contributed due to p-sub depletion junction at the N+/P junction. From analyzing the C-V data, the p-sub doping density can be obtained from the differential capacitance-voltage profiling technique [9]. Fig. 3.1 shows the relationship between the depletion capacitance and the applied reverse voltage, the building voltage of the N+/P junction can be obtained from the projection of the 1/C2-V curve to where 1/C2 =0. The high linearity of the 1/C2-V curve implies that the abruptness of the N+/P junction is good and is suitable to use the abrupt junction formula to express the experimental results.
The Neff is then calculated from the averaged substrate doping density and the building voltage. The relation of Neff to the 2nd RTA temperature is shown in Fig. 3.2, it seems that the Neff presents at the N+/P interface is negatively related to the 2nd RTA
24
temperature. The lowest Neff extracted at this study is above 1019 cm-3, which is four order larger than the substrate doping density. This supports the assumption that the capacitance measured is mainly due to the depletion in substrate at the N+/P junction.
3.3.2 FPP and SIMS measurements
Some papers appointed that defects might cause dopant deactivated [11,12] at higher RTA temperature. However, from the study about the M/S junction [10], we did not find significant deactivation to take place at the silicide/silicon interface at the same process window in this study. In order to make clear what is the origin of the decreased Neff, a test structure designed for FPP measurement is adapted. By removing nickel silicide using silicide etch solution (the etch selectivity of nickel silicide to bare Si is larger than 50 in our test), the results of measured resistance are displayed in Fig. 3.3. It shows that the resistances become smaller with higher 2nd RTA temperatures, which means that either doping concentration or the junction depth is extended with higher 2nd RTA temperature. Comparing the result to the SIMS profile in Fig. 3.4, suggesting that the lower Neff measured at higher temperature is mainly due to that where the N+/P interface presented are at the deeper position away from the M/S interface. The result implies that the dopant activation behavior is starting from the NiSi/Si interface and then extended to the silicon substrate. If the high activated doping concentration is related to the SRER process as we assumed in the previous chapter, it is recommended that the SPER process is starting from the M/S interface. As a consequence of C-V, FPP, and SIMS measurements, the suggested phosphorous activation behavior of the IIS method is illustrated in Fig. 3.5.
3.3.3 I-V measurement
In addition to analyze the junction forming behavior, I-V measurement are adapted.
The N+/P diode I-V measurement results are summarized as Jon (at VA = -1V) and Joff
(at VA = 2V) exhibited in Fig. 3.6. The sample with 2nd RTA 550℃ 60s treatment has the lowest Joff value among all samples. The high Joff current densities presented at 2nd RTA temperature below 500℃ are explained as that there may exist high defect densities at the P/N junction interface. The defects may originate from the remained amorphous region where is still not recrystallized due to the short activation time or the low activation temperature. As the result, with increasing 2nd RTA temperatures, the SPER process continuous going, and the Joff currents decreased. At 2nd RTA 550
℃ 60s, the SPER process seen to be completed (this can be observed by the relative consistent resistances measured in FPP method, see Fig. 3.3), the sample exhibits the maximum on/off ratio. However, the on/off ratios (Fig. 3.6) and Neff (Fig. 3.2) diminish at 2nd RTA higher than 550℃ 60s. Since the SPER process looks like completed above 2nd RTA 550℃ 60s, the facts described above may originated by defect (dislocations start to form at the temperature range from 500 to 600℃ [13]) itself or by some defect induced dopant deactivation at the P+/N interface. In addition, deactivation from phosphorous super-saturated solubility to thermal equilibrium solubility in silicon [14] might also play an important role when the thermal budget is higher than which required for SPER process completion. (The experiments of thermal stability about dopant super-saturated will be given in future publication.)
26
3.4 Conclusions
With the starting ideas that SPER and metal enhanced crystallization are the main responses to the high activation ability with IIS method in low activation temperature, we combine the SIMS, C-V, FPP, and I-V measurements to construct the doping activation behavior of the IIS method. All experiment results suggested that SPER process is starting from the M/S interface and extend into the silicon substrate. The best N+/P interface is formed when SPER process is complete. After SPER process finished, samples with additional thermal budget treatment above 550℃ cause the defect formation at the bulk silicon and the dopant deactivation phenomenon may occur, both factors will decay the N+/P junction’s performance. Sample treated with 2nd RTA 550 ℃ 60s forms the best N+/P junction among all controls in this study.
References
[1] K.M. Chang, J.H. Lin, and C.Y. Sun: Applied Surface Science, Vol. 154, pp. 6151, (2008).
[2] B.S Chen and M.C. Chen: Electron Devices, IEEE Transactions on, Vol. 43, Issue. 2, pp. 258, (1996).
[3] D.L. Kwong, T.H. Ku, S.K. Lee, E. Louis, N.S. Alvi, and P. Chou: J. Appl. Phys. Vol. 61, pp. 5084, (1987).
[4] J. Kedzierski, D.Boyd, C. Cabral, Jr., P. Ronsheim, S. Zafar, P.M. Kozlowski, J.A. Ott, and M.
Ieong: Electron Devices, IEEE Transactions on, Vol. 52, Issue 1, pp. 220, (2005).
[5] J. Foggiato, W.S. Yoo, M. Ouaknine, T. Murakami, and T. Fukada: Materials Science and Engineering B, Vol. 114–115, pp. 56, (2004).
[6] A. Steegen, and I. De Wolf, K. Maex: J. Appl. Phys., Vo1.86, No. 8, pp. 4290, (1999).
[7] B.J. Pawlak, R. Lindsay, R. Surdeanu, P.A. Stolk, K. Maex: Proceedings of the 14th International Conference on Ion Implantation Technology, pages X, (2002).
[8] R. Lindsay, K. Henson, W. Vandervorst, K. Maex, B.J. Pawlak, R. Duffy, R. Surdeanu, P. Stolk, J.A. Kittl, S. Giangrandi, X. Pages and K. van der Jeugd: J. Vac. Sci. Technol. B, Vol. 22, No. 1, pp. 306 (2004).
[9] Dieter K. Schroder: “Semiconductor material and device characterization”, second edition, John Wiley & Sons, Inc. Chapter 2, 1998.
[10] K.M. Chang, J.H. Lin, and C.Y. Sun: Applied Surface Science, Vol. 154, pp. 6155, (2008).
[11] T.E. Seidel and A.U. MacRae: First Intl. Conf. on Ion Implantation, (1971).
[12] K. Larsen, V. Privitera, S. Coffa, F. Priolo, S. U. Campisano, and A. Carnera: Physical Review Letters, Vol. 76, No.9, pp.1493, (1996).
[13] S. Wolf, and R.N. Tauber: “Silicon processing for the VLSI era”, second edition, Lattice press, Vol. 1, Chapter 10, 2000.
[14] Y. Takamura, S.H. Jain, P.B. Griffin, and J.D. Plummer: J. Appl. Phys., Vo1. 86, No. 1, pp. 230, (2002)
28
Fig. 3.1. An example of the measured1/C2–V curve, the sample was treated with 2nd RTA 650℃ 60s.
Fig. 3.2. Phos. doping density estimated from C-V measurement with different 2nd RTA temperatures.
30
400 450 500 550 600 650 0
5 10 15 20 25
R trend (ohm/ohm) (Normalized with P60 650 o C)
2nd RTA Temperature (oC) 2nd RTA 30s (P30) 2nd RTA 60s (P60)
Fig. 3.3. Relative resistance ratio measured with FPP test structures at different 2nd RTA conditions
Fig. 3.4. SIMS profile of phosphorous doped sample treated with 2nd RTA 650℃ 60s.
32
Lower 2
ndRTA
Fig. 3.5. The behavior of phosphorous activation is shown schematically. The P/N junction interface becomes deeper away from M/S interface with higher 2nd RTA temperature.
Fig. 3.6. Absolute Jon, Joff, current density and on/off ratio measured at different 2nd RTA temperatures.
34
Chapter 4 P
+/N J UNCTION
4.1 Brief Introduction and Design Idea
For the purpose to confirm the ideas made in chapter 2 (SPER and metal assisted metallization construct the low temperature dopant activation ability of IIS technique) and in chapter 3 (The SPER is starting from silicide/silicon interface and then extended into the silicon substrate) are valid, we designed an experiment similar to that in chapter 3 but differs in the implantation projection range design and the junction type. Boron was adapted as the implanted dopant in this study, due to its fast diffusion ability, and as a result the junction now we were treated was changed to silicide/P+/N type. The projection range of this study was changed from in silicide (as in chapter 2 and chapter 3 did) to in the silicon. Since the peak dopant densities was located in the silicon region, we expected to see that with the C-V measurement, we could observe the “moving junction” behavior suggested in chapter 3.
4.2 Experiments
4.2.1 Device fabrication for I-V, C-V, SIMS measurements
Starting material was (100) n-type silicon wafer, after thermal oxidation and active regions definition, backside of the wafer was implanted with phosphorous 5x1015 cm-2 and annealed with furnace at 1000℃ 30 min. TaN 100 nm was sputtered on as the back contact. After dipped dilute HF to remove the native oxide at the active region, 20nm nickel was deposited by e-gun system. All samples were treated with 1st
RTA at 350℃ 30s, after unreacted Ni removed, all samples were ion implanted with BF2 5x1015 cm-2. Then, samples were treated at 2nd RTA 60s with different temperatures from 400℃ to 650℃, 50℃ per step.
4.2.2 Device fabrication for FPP measurements
For four points probe test structure, starting material was (100) n-type silicon wafer, too. After thermal oxidation and active regions definition, 20nm nickel was deposited by e-gun system. Following processes were the same as described in section 4.2.1. However, for FPP test structure, after 2nd RTA, NiSi was removed using silicide etch solution (the etch selectivity of NiSi to bare Si is larger than 50). At the final step, Al was thermally coated as back contact. No post metal annealing was treated for thermal budget control consideration.
4.3. Results and Discussion 4.3.1 SIMS and C-V measurements
In comparison with N+/P junction behavior studied in our previous work (reference 5, where the projected range is in the nickel silicide), a different doping profile is adapted in this study. As shown in Fig. 4.1, there are two peaks presented in SIMS profile (after 2nd RTA 650℃ 60s). Peak 1 is formed due to dopant segregation [6] phenomena (NiSi film is about 23nm thick determined by SEM inspection), and Peak 2 is the projection range of this implantation.
From previous understanding [5], the effective boron concentration (Neff) presented at the P/N interface estimated from C-V measurement in this study would not decrease monochromatically with the increasing 2nd RTA temperatures, instead,
36
Neff measured from increase 2nd RTA temperatures should have the trend such like some part of the SIMS profile. The C-V measurement result is demonstrated in Fig.
4.2, boron has the similar doping profile (but lower density due to not fully activated) to which obtained in SIMS measurement. This result supports our previous observation in chapter 3 that doping activation of the IIS method is starting from silicide/silicon interface toward the silicon substrate. Substrate doping densities extracted from C-V measurements are also shown in the Fig. 4.2 as a reference. It shows that phosphorous have a bit higher concentrations below 500℃ 2nd RTA. This behaviour might be due to samples treated at lower 2nd RTA temperatures have narrower activated region from the edge of NiSi/Si (M/S) interface, and there are some doping segregation phenomena of phosphorous at the M/S interface. As a result, samples with lower 2nd RTA temperatures, the P/N interface are closer to M/S interface than samples with higher 2nd RTA temperatures, and have a higher substrate concentration due to the doping segregation affect. This double confirms our previous observation in chapter 3.
4.3.2 I-V and FPP measurements
Fig. 4.3 shows the I-V measurement results of samples fabricated in section 4.2.1. The forward current (IF) is defined at sample with 1V forward bias voltage, and the reverse (IR) current is defined at sample with 2V reverse voltage. From the IF/IR ratio, it seems that the sample with 2nd RTA 550℃ 60s has the best performance at this measurement. The better performance of 2nd RTA 550℃ 60s than those samples with lower 2nd RTA temperatures can be contributed to two reasons. First, the activation process will also re-crystallize the amorphous layer at silicide/silicon interface caused by silicide formation process. With higher thermal budget, the better
re-crystallization interface can be formed. Secondly, as shown in Fig. 4.1 and Fig. 4.2, the P+/N junction position of 2nd RTA 550℃ 60s sample might be beyond the point 2 appeared in Fig. 4.1, where less doping defects (unactivated dopant and silicon interstitials) are present. However, the I-V behaviour above 550℃is different to those observed about N+/P junction in Fig 3.6, in N+/P case, above 550℃, IF/IR ratios decreased with increasing 2nd RTA temperature.
To explain the I-V behaviour above 550℃, some other information about the junction formation should be measured as the reference. In Fig. 4.4, the relative resistance of these samples (after NiSi removed) measured with FPP test structure is displayed. The resistance reflects the combination interactions of the doping activation level and the junction depth. All resistances are normalized to the lowest measured value (2nd RTA 650 ℃ 60s). It exhibits that the resistance decreases gradually but has an abrupt decrease at 650℃ for N30 samples (treated with 2nd RTA 30s) and at 600℃ for N60 samples (treated with 2nd RTA 60s). In addition, the lowest resistance values measured in N30 and N60 samples are almost the same at the original data. This implies that above 2nd RTA 650℃ 30s or 2nd RTA 600℃ 60s, the bulk activation of boron is higher than the substrate doping density, and the p-type junction extended far into the substrate. As a result, the resistances measured under this bulk activation [7] condition are very similar. Bulk activation behaviour dominates the P+/N junction formation at high thermal budget conditions. This explains the difference of the N+/P and P+/N junction’s I-V behaviours above 550℃.
In N+/P case, the performance of junction formed at high thermal budget condition is dominated by defect formation or dopant deactivation, but for P+/N case, bulk activation behaviour dominates.
38
The low IF/IR ratio of 600℃ 2nd RTA sample (N600) in this study is due to the low forward current density measured at VA = 1V. Fig. 4.5 shows the J-V curve of some samples treated at 2nd RTA 550℃ 60s (N550-1), 600℃ 60 s (N600-1), and 650
℃ 60 s (N650-1). The ideality factors of these three samples are all round 1.02. The low JA of 1 is explained as follows: the law of junction is violated first of N600-1, which implies the voltage drop in the bulk regions occurring at lowest forward voltage in N600-1 sample. This means that the built-in voltage (Vbi) of the N600-1 sample is lowest among these samples. This observation confirmed the measured C-V data in Fig. 4.2, the Neff is lowest at 2nd RTA 600℃ 60s sample.
℃ 60 s (N650-1). The ideality factors of these three samples are all round 1.02. The low JA of 1 is explained as follows: the law of junction is violated first of N600-1, which implies the voltage drop in the bulk regions occurring at lowest forward voltage in N600-1 sample. This means that the built-in voltage (Vbi) of the N600-1 sample is lowest among these samples. This observation confirmed the measured C-V data in Fig. 4.2, the Neff is lowest at 2nd RTA 600℃ 60s sample.