Chapter 6 Thermal Reliability of Junctions Formed by IIS Method
6.3.2 Lightly implanted samples
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The I-V measurement results of lightly doped sample are shown in Fig. 6.4.
For lightly implanted samples, samples with three different kind thermal treatments are discussed. Case A: samples were treated with 2nd RTA 60s at different temperatures. Case B: An extra 3rd RTA 60s were introduced at the same temperature as 2nd RTA. Case C: samples were treated with 2nd RTA 120s at different temperatures.
For M/P+/N diode, shown in Fig. 6.4(a), for Case A, it looks like the activation process is best completed at 450℃, and Joff increases as temperature increases. There is a Joff drop at 600℃ for Case A. With added 3rd RTA, Case B, Joff become worse at 450 ℃ and 500 ℃ , this might cause by the dopant de-activation due to the supersaturation. And for 550 ℃ and 600 ℃ samples, the Joff is improved. These improvement above 550℃ could also be found for the heavily doped case. The improvement might be contributed to the recovery of some defects that already generated in the previous thermal treatment. Although we don’t know what is the defect type recovered in these samples, we can conclude that defects are both generated and recovered above 550℃ and the process widow for the defect recovery mechanism dominate is relative small and hard to control. Finally, for Case C, the Joff differs only a little among all samples and when comparing to Case A and Case B samples, it shows that Case C samples are not in the best conditions. All samples suffer same high defect levels.
Fig. 6.4(b) shows the I-V measurement results for the M/N+/P diode. Samples treated at 500 ℃ demonstrate the best performance in all the cases. Dopant de-activation under 500℃and defect generated above 500℃ are both significant. This observation is similar to the result for the heavily implanted samples. Thermal treatment at 500℃might have the widest time process window for the M/N+/P diode.
Also, samples treated at 650℃ in Case C, the defect recovery behavior is also be observed.
The C-V results of the lightly implanted samples are less reliable than heavily implanted samples. For heavily implanted samples, the abrupt junction assumption vanished only for M/N+/P diodes treated at Case 3 (RTA 60s+30s+30s) above 600℃.
However, the abrupt junction assumptions only hold in Case A for lightly implanted samples. Resembling to the Type I and Type II C-V distortions in heavily implanted samples, as shown in Fig. 6.5, there are also two different kinds of C-V distortions in the lightly implanted samples. First of C-V distortion in lightly implanted samples is linear junction like behavior shown in Fig. 6.5(a) and this distortion are found in all samples in Case C and most samples in Case B (except samples treated at 600℃). The linear junction like behavior could be explained similar to the Type I distortions for heavily implanted case. When an additional thermal treatment processed (most samples in Case B), majority carriers not only diffused from the N+ region into the p-substrate and also activated there. This situation is easy to be found with a long-term thermal treatment (Case C). This distortion could be concluded that junction is deepened from the silicide/silicon interface into the substrate, this supported our previous work in chapter 3 that real junction position of the PN junction is moved when device undergone thermal treatment. And with less defects in the substrate region, the easier C-V distortion behavior to be observed: light implanted case compare to heavily implanted case, and also Case C (deeper junction position, far from the silicide/silicon interface) versus Case A for light implanted case. This might due to the less the dopants, the slower the diffusing and activation speed. Hence, the non-uniform PN interface would easy be observed. The second kind of distortion, hyper junction like, is similar to the Type II C-V distortion in the heavily implanted
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case. Interestingly, this kind of distortion is only found in the M/N+/P samples with additional thermal treated at 600 ℃ (the C-V results for corresponding lightly implanted M/P+/N samples are shown in Fig 6.6 for comparing). This implied that the origin of this kind C-V distortion might due to the dopant itself, for example diffusion coefficient and activation behavior. This observation agrees to our suggested explanation in the previous section. In addition, the different of C-V and I-V results for samples demonstrated in Case B and Case C suggested that even samples are treated at the samples thermal budget, RTA 60s+60s versus RTA 120s at same temperature, the dopant and defect distributions differ one to another. Not only thermal treated at the stable temperature region is important at the junction formation process, the rising and cooling temperature processes also play an important role.
6.4 Conclusion
For junctions formed by IIS method, heavily implanted samples might have better thermal stability than lightly implanted samples. For heavily implanted case, although the C-V measurement result differs only a few, the I-V measurement changes a lot. The I-V measurement is more sensitive to the defect present in the junction area. There are at least two different mechanisms for junction degrading for IIS formed junction. Above 550℃, defect formation due to silicon itself might be the obvious one, and for temperatures lower than 500℃, de-activation caused by the supersaturation of dopant dissolved in the silicon might dominate. When junction is under an additional thermal process, there are two kinds of C-V distortion patterns could be observed. One distortion pattern has the characteristic that the activated doping density at the PN junction interface is more linearly distributed. This pattern
corresponds to the junction extension process. On the other hand, the second C-V distortion pattern has observed that there is higher effective substrate doping density near the PN interface. This might due to the dopant segregation effect, and the observation of this distortion pattern is also related to the substrate and implanted dopant characteristics such like diffusion and de-activation attributes. In addition, the thermal budget is not the only key factor to the junction formation process, the heating and the cooling process also have significant impact to the junction formation.
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Reference:
[1] ITRS Roadmap 2006 update
[2] G.D. Wilk, R. M. Wallace, and J. M. Anthony: J. Appl. Phys., Vol. 89, pp. 5243, (2001)..
[3] C.S. Kang, H.J. Cho, R. Choi, Y.H. Kim, C.Y. Kang, S.J. Rhee, C. Choi, M.S. Akbar, and J.C. Lee:
Electron Devices, IEEE Transactions on, Vol. 51, Issue 2, pp. 220, (2004).
[4] K.M. Chang; J.H. Lin; C.H. Yang: Semiconductor Device Research Symposium, FP6-5, (2007.) [5] K.M. Chang, J.H. Lin, and C.Y. Sun: Applied Surface Science, Vol. 154, pp. 6151, (2008).
[6] C.C. Wang and Mao-Chieh Chen: J. J. Appl. Phys. Vol. 45, pp. 1582, (2006).
[7] Advanced Micro Devices, Inc. US Patent number-7306998
[8] A. Kinoshita, C. Tanaka, K. Uchida and J. Koga: IEEE VLSI, pp. 158, (2005).
[9] S. Wolf, and R.N. Tauber: “Silicon processing for the VLSI era”, second edition, Lattice press, Vol.
1, Chapter 10, 2000.
400 450 500 550 600 650
400 450 500 550 600 650
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Fig. 6.1. (a) Reverse current density (I-V method) and (b) Effective doping density extracted from C-V method versus different process conditions for heavily implanted M/P+/N samples
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400 450 500 550 600 650
400 450 500 550 600 650
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Fig. 6.2. (a) Reverse current density (I-V method) and (b) Effective doping density extracted from C-V method versus different process conditions for heavily implanted M/N+/P samples
0.0 0.5 1.0 1.5 2.0
M/N+/P sample RTA 600 oC 60s+30s+30s Type I : Lower densities near N+/P at Psub
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
M/N+/P sample RTA 600 oC 60s+30s+30s Type II : Higher densities near N+/P at Psub
1/C2
VR (V) Higher density Lower density
Fig. 6.3. (a) Type I C-V distortion and (b) Type II C-V distortion for the heavily implanted M/N+/P samples with 600℃ RTA 60s+30s+30s
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450 500 550 600 10-4
10-3 10-2
M/P+/N Sample 5E13 2nd RTA 60s RTA 60s+60s 2nd RTA 120s
J off (A/cm2 )
RTA Temperature (oC)
450 500 550 600
10-7 10-6 10-5 10-4 10-3 10-2
M/N+/P Sample 5E13 2nd RTA 60s RTA 60s+60s 2nd RTA 120s
J off (A/cm2 )
RTA Temperature (oC)
Fig. 6.4. Reverse current density (I-V method) for lightly implanted (a) M/P+/N and (b) M/N+/P samples verse different process conditions
0.0 0.5 1.0 1.5 2.0
Fig. 6.5. Two different kinds of C-V distortions for lightly implanted M/N+/P sample treated at RTA 600℃ (a) 120s (gradual junction like) and (b) 60s+60s (abrupt junction like)
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0.0 0.5 1.0 1.5 2.0 Abrupt Junction Assumption M/P+/N 5E13 After 3rd RTA 600oC 60s
C-2 ( Abrupt junction Assumption) C-3 ( Linear junction Assumption)
Abrupt Junction Assumption
VR (V) Linear Junction Assuption
M/P+/N 5E13 After 2nd RTA 600oC 120s
Fig. 6.6. Only one kind of C-V distortion for lightly implanted M/P+/N sample treated at RTA 600℃ (a) 120s and (b) 60s+60s (both gradual junction like)
Chapter 7
S UMMARY AND F UTURE W ORK
7.1 Summary
At first part of this thesis, we described and tried to explain the junction formation behaviors of the IIS method how it formed and why dopant could activate at low temperature. The junction formation process of IIS method could be contributed to three mechanisms: first, near the silicon/silicon interface, metal assisted activation is notable, and secondly, at the heavily doped region where SPER caused activation behavior is obvious, and finally, with higher activation temperature, above 600℃ in the case in chapter 4, bulk activation dominates the junction’s position and its behavior. Before bulk activation dominates the junction’s behavior, the junction formation process is starting at the M/S interface and then extending into the silicon substrate. The mechanism, which would be the dominated one of the junction formation process, depends on the implantation energy (projection range), implanted dosage (quantity of the impurity), diffusion coefficient of the dopant, thermal solubility of the dopant, and the thermal treatment condition itself (both temperature and time). For boron and phosphorous studied in this study, boron not only has faster diffusion coefficient than phosphorous but also has higher (bulk) activation ability at low temperature range ( < 650℃). This makes boron doped sample when activated using IIS method easy fall in SPER caused activation or bulk activation dominate region. These factors make boron doped sample hard to form very shallow junction (where heavily doped region is fully depleted during device operation, the region is estimated fall around 1 nm range). On the other hand, phosphorous doped sample
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which junction activation is mostly dominated by metal assisted activation could be used to form very shallow junction.
In second part of this thesis, based on the understanding of the junction’s behavior in the first part, we try to connect the junction’s electrical properties and the junction’s physical properties. However, the physical properties are difficult to be direct measured, most physical parameters used here were just qualitatively described but not quantitatively determined. Experimental results showed that for M/N+/P samples, doping densities extracted from C-V methods could be used to approximate the phosphorous doping activation densities near the M/S interface. It showed that with higher activated doping densities near the M/S interface, the higher the SBH would be obtained from the I-V-T measurement and the lower the reverse biased leakage current. And for M/P+/N samples, the junction behaves with both the characters of M/P+ junction (when VR<0.1V) and M/N (whole behavior). Combined with C-V measurement results, it implied that the M/P+/N junction in this study could be treated as two individual junctions in series but with strong coupling effects between them. And for thermal reliability issue, junctions formed by IIS method, heavily implanted samples might have better thermal stability than lightly implanted samples. In addition, comparing to C-V measurement method, I-V measurement is more sensitive to the defect present in the junction area and more suitable be used to observe the thermal reliability issue of the junction. When junction is under an additional thermal process, there were two kinds of C-V distortion patterns observed in this study. One distortion pattern had the characteristic that the activated doping density at the PN junction interface was more linearly distributed. This pattern corresponded to the junction extension process. On the other hand, the second C-V distortion pattern had observed that there was higher effective substrate doping
density near the PN interface. This might due to the dopant segregation effect, and the observation of this distortion pattern was also related to the substrate and implanted dopant characteristics such like diffusion and de-activation attributes.
7.2 Future Work
We have widely discussed the junction formed by IIS method at many aspects from the low temperature activation ability, junction formation behavior (also provide possible mechanisms), some relationships between the process parameters to the electrical properties and also some notes on the thermal reliability issues. But there are still many works could be studied. We divided the future work into two parts:
7.2.1 junction characteristics modeling, and 7.2.2 applications.
7.2.1 Junction characteristics modeling
Modeling most depends on correct physical parameters for doping densities and junction depth, however, these data are still hard to direct measured for us at this time. Most other researches use SIMS to explain the dopant distribution, but lack of the activation information. In this study we use C-V measurement method but C-V method has its spatial resolution limitation, restricted by Debye length. That is why in this study we only use C-V method as a tool to describe the “average” behavior, but not focus on the exact doping quantity calculation. And the junction depth here we are interested in is about 1nm deep. It is hard to use SRP method to precisely determined the junction’s position, since many factors will effect the experimental result, such like interface roughness and band narrowing effect of the heavily doped region. Some special kinds of TEM might tell the junction position, but TEM could tell only localized information and lack of information about the activation ability. These are topics should be classified but undone, waited for some more studies devote on.
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After physical parameters are determined, the systematical study for large sample size diodes should be measured to model the I-V behavior. Recent studies have some predictions to junction’s behavior by simulation. But the assumptions are hard to be verified in the device fabrication. That originates from lacking information about the device parameters just stated above in 7.2.1. In this study, we used comparing to determine the relative junction depth and doping levels. Only could conclude some relationship between process parameters and final junction’s behavior qualitatively. More accurate model need pay more effort to establish.
7.2.2 Applications
Although the model of the IIS formed junction is not clear, we can also take the advantage of the high activation ability in low temperature to many different kinds of applications: 1. Gate first process integrates with high-k material. 2. S/D contact for the TFT device. 3. Contact for solar cell.
Gate first process for high-k device is limited by the thermal reliability of the high-k dielectric. If using IIS method at S/D region might provide more choices for the high-k dielectric selection. TFT S/D contact activation limited by the substrate property. Traditionally, TFT S/D activation need long time period, for introducing IIS method, the S/D contact formation process might be improved. Also, the contact issue for solar cell is limited by the dopant diffusion (p-i-n) structure, high temperature might thin the intrinsic layer and worse the photo-electric efficiency, but contact resistance will also worse the voltage generated of the solar cell. Introducing IIS method to solar cell might improve the contact resistance and provide better cell performance.
學歷資料
電子工程學系電子研究所博士班學生 林建宏
學號： 9311807
性別： 男
出 生 日 期： 68年 5月 15日
學歷 : 國 立 台 灣 大 學 工 商 管 理 學 系 畢 業 ( 91年畢業) 國 立 交 通 大 學 電 子 研 究 所 碩 士 班 ( 93年畢業) 國 立 交 通 大 學 電 子 研 究 所 博 士 班 ( 93年入學)
博士論文題目：
中文：藉由離子佈植進入矽合金法在低溫活化下形成的接面研究
英 文 ： A Study of Low Temperature Activated Junction Formed by
Implant Into Silicide Method
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