Conclusion

We have studied the thermally oxidized AlAs and Al to use as an alternative gate dielectric. The leakage current from AlAs oxidation is larger than that from Al

oxidation at low voltages. The leakage current of a 53 Å Al2O3 is already lower than SiO2 with an equivalent oxide thickness of 21 Å. These results suggest that scaling equivalent oxide thickness below 13 Å is possible using the Al2O3 films.

Fig. 2-1 SIMS depth profiles of oxidized AlAs at 500^oC.

0 100 200 300 400 500

10¹ 10² 10³ 10⁴ 10⁵ 10⁶

Al₂O₃/Si interface

As Al

O

Secondary Ion Counts

Depth (Angstroms)

Fig. 2-2 SIMS depth profiles of oxidized Al at 500^oC.

0 100 200 300 400 500

10¹ 10² 10³ 10⁴ 10⁵ 10⁶

Al₂O₃/Si interface

Al O

Secondary Ion Counts

Depth (Angstroms)

Fig. 2-3 J-V characteristic of MOS capacitors with deposited AlAs oxidized at a temperature of 500^oC to form Al2O3 dielectric. The capacitor area is 800µm×

800µm.

Fig. 2-4 J-V characteristic of MOS capacitors with deposited Al oxidized at a temperature of 500^oC to form Al2O3 dielectric. The capacitor area is 800µm×

800µm. The J-V characteristic of 21 Å SiO2 is from reference 2.

0.0 0.5 1.0 1.5 2.0 2.5

Chapter 3

Device and Reliability of High-k Al

₂

O

₃

and La

₂

O

₃

Gate Dielectric with Good Mobility and Low D

_it

3.1 Introduction

By continuously scaling down the CMOS technology, ultra-thin high-k gate dielectrics with low leakage current are required to replace the direct-tunneling current dominated thermal SiO2. Recently Si3N4 gate dielectric has been studied extensively to replace thermal SiO2 [3.1]; however, the marginal improvement beyond SiO2 is due to the relatively lower k and slightly higher leakage current. Although stacked high-k materials have been studied to achieve higher k value than that of Si3N4 [3.2], [3.3], it may require complicated process steps and the leakage current is still higher than expected. In this study, we report a very simple process to fabricate Al2O3 as an alternative gate dielectric with a k value (9.0 to 9.8) greater than Si3N4. To avoid any process related damage, Al2O3 gate dielectric is formed by direct oxidation from thermally evaporated Al. In addition to high-k, the 48 Å Al2O3 has ~6 orders lower leakage current than equivalent 13 Å SiO2. Good mobility, interface trap density, and reliability are also achieved using this process.

Although high-k gate dielectrics have attracted much attention recently, further

reduction of EOT may be limited by the interface reaction region between high-k material and Si [3.4], [3.5]. Therefore, the search for thermodynamically stable high-k dielectric directly on Si is important to meet future sub-10 Å requirement. Besides the required good electrical properties such as low interface trap density (Dit), low leakage current, high breakdown field (EBD) and good reliability, high-k material must also be compatible with existing VLSI process. Thus, good stability with H2 and high transition temperature from amorphous to crystal [3.5] are necessary to prevent dielectric degradation by H2 and crystalline structure created defects or dislocations during strain relaxation in process. Previously, we have worked that amorphous Al2O3

directly on Si can meet near all the requirements and stable up to 1000^oC [3.6], except that EOT (21 Å) and Dit (1x10¹¹ eV^-1/cm²) are still high. The high Dit is unacceptable for IC because of the increased noise [3.7]. In this study, we have used amorphous La2O3 (k~27) to achieve 4.8 Å EOT and reduced Al2O3 EOT to 9.6 Å, where La2O3

has similar property as Al2O3 but with even better thermal stability on Si (Table 1-2).

In addition to respective low leakage current of 0.06 and 0.4A/cm² for La2O3 and Al2O3,both dielectrics now have good Dit (3x10¹⁰ eV^-1/cm²), EBD, SILC, and QBD as compared with SiO2.

3.2 Device and Reliability of High-k Al

2

O

3

Gate Dielectric

3.2.1 Experimental

To avoid any possible process-related damage in Al2O3 gate dielectric [3.8], we have used direct thermal oxidation from thermally evaporated Al on Si. Native oxide is suppressed by a HF-vapor passivation and desorbed in-situ inside an ultra-high vacuum MBE environment [3.9], followed by an immediate Al evaporation.

Deposited Al was oxidized at a temperature of 400^oC to form Al2O3. Then the Al2O3

was annealed in nitrogen ambient to reduce defects. Poly-Si gate MOS capacitor and transistor were fabricated to evaluate the electrical characteristics. The suppression of native oxide is important to achieve higher k in Al2O3, and we have used similar idea to achieve atomically smooth ultra-thin oxide with good electrical characteristics and reliability [3.10]. For comparison, MOS capacitor and transistor were also fabricated by thermal SiO2.

3.2.2 Results and Discussion

3.2.2.1 The physical property of Al2O3

We have first measured the SIMS profile in Fig. 3-1 to confirm the formation of Al2O3. Although Al diffusion into Si can be observed, the concentration reduces rapidly as increasing thickness into Si. Fig. 3-2(a) and 3-2(b) illustrates the TEM

observed in Al2O3 bulk oxidized at 500^oC. We have also used C-V measurement to determine the Al diffusion and the concentration is lower than 1x10¹⁶ cm^-3. Furthermore, the field-dependent mobility also suggests the low Al diffusion into Si.

3.2.2.2 Gate capacitor

Fig. 3-3 presents the J-V characteristic of a 48 Å Al2O3 capacitor. The leakage current is ~6 orders of magnitude lower than that of the equivalent 13 Å thermal SiO2. In order to obtain an accurate k value, we have also measured the C-V of a thick 110 Å Al2O3 capacitor. As shown in Fig. 3-4, a k value of 9.0 is measured that is higher than Si3N4. In Fig. 3-5 presents the measured interface trap density with a mid-gap value of 1x10¹¹ eVcm^-2 from this capacitor. This low interface trap density is suitable for MOSFET application.

3.2.2.3 Mobility and transistor performance

To further characterize the Al2O3/Si interface, we have fabricated a wide gate MOSFET to measure the electron mobility. Fig. 3-6 shows the effective mobility of an 80 Å Al2O3 MOSFET. The electron mobility is comparable to published mobility data from thermal SiO2. Fig. 3-7 shows the Id-Vd characteristics of an 80 Å Al2O3

than that of thermal SiO2 also proves the high-k value in Al2O3 MOSFET and a k of 9.8 is obtained.

3.2.2.4 Reliability

Fig. 3-8 and Fig. 3-9 show the 48 Å Al2O3 gate dielectric under a 2.5 V constant stress for 10,000 sec, and good reliability is evidenced from the very small current change and stress-induced leakage current (SILC) respectively. Fig. 3-10 and Fig.

3-11 present the same Al2O3 gate dielectric under a much higher stress of ~5.4 V with a 0.1 mA/cm² constant current density for 1000 sec. The small voltage changes less than 0.04 V and the small SILC also suggest the excellent reliability. Therefore, the Al2O3 gate dielectric is suitable for continuously operation at VLSI generations of 2.5 V and beyond.

3.3 Device and Reliability of High-k La

2

O

3

Gate Dielectric

3.3.1 Experimental

To avoid any k value reduction, interfacial native oxide is suppressed by HF-vapor passivation and in-situ desorption [3.6] followed by an immediate La or Al evaporation. Because La or Al is highly reactive with O2, low oxidation temperatures

≤ 400^oC is used to reduce metal diffusion into Si. The formed oxides were further annealed in N2 at 900^oC. To reduce gate depletion, Al gate is used for MOS capacitor and transistor to evaluate the electrical characteristics. H2 annealing at 450-550^oC is performed to study the stability withH2. Besides achieved higher k, suppression of native oxide is important to obtain a smooth interface, low Dit, and high reliability in our previously achieved atomically smooth ultra-thin oxides.

3.3.2 Results and Discussion 3.3.2.1 Gate capacitor

Fig. 3-12 presents the J-V characteristics of La2O3 and Al2O3 capacitors.

Comparable leakage current for La2O3 on Si or Si0.3Ge0.7 I s obtained that is important for high mobility PMOS [3.11]. The stacked Al2O3/La2O3 is used to reduce leakage current for C-V to obtain Dit. In order to get accurate k and EOT, the oxide thickness is carefully examined by both ellipsometer and TEM in Fig. 3-13. The very uniform oxide and smooth interface are due to native oxide free surface and high thermal stability in Table 1-2 as contact with Si. Therefore, low EOT can be expected. Fig.

3-14 shows the cumulative values for high-k oxides, and leakage current of 0.06 A/cm² for La2O3 and 0.4 A/cm² for Al2O3 are obtained. Fig. 3-15 is the C-V curves and

4.8 Å and 9.6 Å EOT (without QM correction). Small hysterisis of 11 and 22 mV are measured for respective dielectrics that indicates good quality because of applied high annealing temperature without transition to crystal structure [3.5]. Fig. 3-16 shows the measured Dit of 3x10¹⁰ eV^-1/cm² from both capacitors. This low Dit close to thermal SiO2 is extremely important for circuit to lower 1/f noise [3.7].

3.3.2.2 Transistor performance with 4.8 Å EOT

We have further fabricated wide gate MOSFETs with 4.8 Å EOT. Figs. 3-17 shows the device Id-Vd, and important Id-Vg and gm are plotted in Fig. 3-18. The very high current drive and gm are due to high-k that gives a k of ~27 consistent with C-V measurement. Good device pinch-off Ioff < 10^-10A/µm and small sub-threshold swing of 75 mV/decade are observed, and the small swing also suggests the low Dit. The effective mobility is further plotted in Fig. 3-19. The electron mobility is comparable with published universal mobility data for thermal SiO2 because of low Dit.

3.3.2.3 Reliability

Fig. 3-20 shows the gate dielectrics under a -2.5 V constant stress for 1 hour with total Qinj of 1.3x10³ and 1.2x10⁵C/cm² for La2O3 and Al2O3, respectively. No

significant charge trapping is occurred during stress, and small SILC for both dielectrics is observed in Fig. 3-21. Good reliability for 4.8 Å EOT La2O3 is evidenced from the high QBD in Fig. 3-22 and comparable with current SiO2 [3.12].

The good SILC and QBD may be due to the high lattice energy in Table 1-2. From the 50% failure time, an extrapolated max voltage of 2.3 V is obtained for 10 years lifetime that suggests good reliability for VLSI application with 4.8 Å EOT and small leakage of 0.06 A/cm² at 1 V.

3.4 Conclusion

We report a very simple process to fabricate Al2O3 gate dielectric with k (9.0 to 9.8) greater than Si3N4. Al2O3 is formed by direct oxidation from thermally evaporated Al. The 48 Å Al2O3 has ~6 orders lower leakage current than equivalent 13 Å SiO2. Good Al2O3/Si interface was evidenced by the low interface density of 1x10¹¹ eVcm^-2 and compatible electron mobility with thermal SiO2. Good reliability is measured from the small SILC after 2.5 V stress for 10,000 sec.

High quality La2O3 and Al2O3 are fabricated with EOT of 4.8 and 9.6 Å, leakage current of 0.06 and 0.4 A/cm² and Dit of both 3x10¹⁰ eV^-1/cm², respectively. The high-k is further evidenced from high MOSFET’s Id and gm with low Ioff. Good SILC

thermodynamic stability in contact with Si and stable after H2 annealing up to 550^oC.

Fig. 4-1 SIMS depth profile of oxidized Al at 500^oC. The measured thickness is close to that measured by ellipsometer & cross-sectional TEM.

0 100 200 300 400 500

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

Al₂O₃/Si interface

Al O

Secondary Ion Counts

Depth (Angstroms)

(a)

(b)

Fig. 3-2 TEM photos of Al oxidized at (a) 400^oC and (b) 500^oC.

Al ₂ O ₃ Glue

100Å

Al ₂ O ₃ Glue

100Å

Crystal

100Å Crystal

100Å

0 1 2 3 4 5 6 7 8 10^-11

10^-9 10^-7 10^-5 10^-3 10^-1 10¹ 10³ 10⁵

48 A Al

2O

3

13 A SiO

2

Jg (A/cm2 )

Vg (Voltage)

Fig. 4-2 J-V characteristics of the 48 Å Al2O3 MOS capacitor.

Fig. 3-4 C-V characteristics of 110 Å Al2O3 MOS capacitor.

-2 -1 0 1 2

0 100 200 300 400 500 600

Capacitance (pF)

V (Voltage)

Fig. 3-5 Interface trap density of the Al2O3/Si interface.

-0.6 -0.4 -0.2 0.0 0.2 0.4

10¹⁰ 10¹¹ 10¹² 10¹³ 10¹⁴

Dit (ev/cm2 )

Energy (ev)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0

100 200 300 400 500 600 700

Al₂O₃ gate 80A SiO₂ gate

u eff(cm2 /V-sec)

Es,eff (MV/cm)

Fig. 3-6 Electron mobilities of MOSFET’s with 80 Å Al2O3 and conventional SiO2. (M. S. Liang, J. Y. Choi, P. K. Ko, C. Hu, IEEE TED-33, no. 3, pp. 409-413, 1986.).

Fig. 3-7 Id-Vd characteristics of an 80 Å Al2O3 MOSFET. The high current drive in Al2O3 gives a k value of 9.8.

0 1 2 3 4 5

0.000 0.001 0.002 0.003 0.004 0.005

Al₂O₃ VG from 0V~5V SiO₂ VG from 0V~5V

I D (A)

V_D (Voltage)

Fig. 3-8 Current density changes of the 48 Å Al2O3 MOS capacitor under a constant voltage stress at 2.5 V for 10,000 sec.

0.0 2.0x10³ 4.0x10³ 6.0x10³ 8.0x10³ 1.0x10⁴ 10^-9

10^-8 10^-7 10^-6 10^-5

J (A/cm2 )

Time (sec)

Fig. 3-9 SILC effect of the 48 Å Al2O3 MOS capacitor under a constant voltage stress at 2.5 V for 10,000 sec.

0 1 2 3 4 5

10^-11 10^-9 10^-7 10^-5 10^-3

Before 2.5V 10000s stress After 2.5V 10000s stress

J (A/cm2 )

V (Voltage)

Fig. 3-10 Voltage changes of 48 Å Al2O3 MOS capacitor under a 0.1 mA/cm² current density stress for 1000 sec.

0 200 400 600 800 1000

Fig. 3-11 SILC effect of 48 Å Al2O3 MOS capacitor under a 0.1 mA/cm² current density stress for 1000 sec.

0 1 2 3 4 5

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

Before 0.1mA/cm² stress 1000s After 0.1mA/cm² stress 1000s

J (A/cm2 )

V (Voltage)

Fig. 3-12 J-V characteristics for Al2O3 (9.6 & 16.5 Å EOT)and La2O3 (4.8 Å EOT) capacitors. Stacked structure is adopted to reduce leakage current for Dit

measurement.

Fig. 3-13 Cross-section TEM of Al2O3 and La2O3. Very smooth interface is due to the high thermal stability and native oxide free surface. Both dielectrics are amorphous.

La2O3

Glue 10nm Glue

Si Al2O3

Si

Fig. 3-14 Cumulative distribution of leakage current and breakdown field for Al2O3

and La2O3 gate dielectrics.

11 12 13 14 15

0 20 40 60 80 100

Cumulative Failure (%)

Breakdown Field (MV/cm)

0.01 0.1 1

Al₂O₃ 21A

La₂O₃ 33A

Leakage Current Density @ -1V (A/cm²)

Fig. 3-15 Hysteresis curves for Al2O3 and La2O3 gate dielectrics.

-3 -2 -1 0 1 2

0 100 200 300 400 500 600 700 800

Area=1x10^-4 cm² 21A Al₂O₃

△V_FB=22mV

33A La₂O₃

△V_FB=11mV

Gate Voltage (V)

Capacitance (pF)

Fig. 3-16 Interface state density of Al2O3 and La2O3 on Si. Min Dit of 3x10¹⁰ eV^-1/cm² is obtained for both dielectrics and close to SiO2/Si.

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 10¹⁰

10¹¹ 10¹²

EOT=21.8A

EOT=16.5A ^{36A Al2O3 / 33A La2O3 / Si}

36A Al₂O₃/Si

D it (ev-1 /cm2 )

Energy (ev)

Fig. 3-17 Id-Vd characteristics of 30 mm x 1200 mm nMOSFETs with 33 Å La2O3

gate dielectric.

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0

5 10 15 20

25 Vg=0.75V

Vg=0.6V Vg=0.45V Vg=0.3V Vg=0.15V

Drain Current (mA)

Drain Voltage (V)

Fig. 3-18 Subthreshold characteristic and transconductance for 33 Å La2O3

nMOSFETs as a function of gate bias.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Fig. 3-19 Effective electron mobility versus electrical field for 33 Å La2O3

nMOSFET.

0.1 1

10² 10³

E_eff (MV/cm) u eff(cm2 /V-sec)

Fig. 3-20 Time evolution of Ig under -2.5 V for 1 hr with Qinj of 1.3x10³ and 1.5x10⁵ C/cm² for respective La2O3 and Al2O3.

0 400 800 1200 1600 2000 2400 2800 3200 3600 10^-1

10⁰ 10¹ 10²

33A La₂O₃ CVS under -2.5V for 3600sec 21A Al₂O₃ CVS under -2.5V for 3600sec

Current Density (A/cm2 )

Time (second)

Fig. 3-21 Stress induced leakage current and current variation for Al2O3 and La2O3

(I stressed- I Fresh) / I fresh (%)

Fig. 3-22 QBD distribution of La2O3 dielectricwith different Vg. For 50% MTTF and 10 years lifetime, a max operation voltage of 2.3 V is obtained.

0 20 40 60 80 100 120 140 160 180 200 0

10 20 30 40 50 60 70 80 90 100

Vg=-3.3V Vg=-3.4V Vg=-3.5V

Cumulative Failure (%)

Q_BD (C/cm²)

Chapter 4

Bias-Temperature Instability and Charge Trapping on Fully-Silicided-Germanided Gates/High-k Al

₂

O

₃

CMOSFETs

4.1 Introduction

As continuous scaling down the MOSFET devices into sub-100 nm scale, oxynitride or metal-oxide high-k gate dielectric, with ultra-thin equivalent oxide thickness (EOT), is required to replace the conventional SiO2 to reduce gate dielectric leakage current. To further increase the drive current in MOSFET, metal gate will be integrated with these high-k gate dielectrics [4.1]-[4.5]. However, one of the main concerns of such metal-gate/high-k MOSFETs is the poor Bias-Temperature Instability (BTI) [4.1], [4.6]-[4.8]. In particular, the negative BTI (NBTI) of pMOSFETs is becoming an increasingly serious problem of the CMOS reliability. It is known that the NBTI of oxynitride gate dielectric pMOSFETs is mainly related to nitrogen traps [4.9]-[4.12], hydrogen [4.13]-[4.14], moisture (H2O) [4.14], and impurity diffusion [4.6] etc. Both the NBTI and positive BTI (PBTI) are even worse in metal-oxide high-k CMOSFETs than oxynitride devices [4.1], [4.6]-[4.8]. In this work, we have studied the BTI effect on fully silicided-germanided (NiSi-NiGe) dual

gates on high-k Al2O3 CMOSFETs [4.5], [4.15]-[4.19] and compared with a benchmark oxynitride devices. The fully silicided gate has advantage of fully process compatible to current VLSI fabrication technology. The Al2O3 gate dielectric has reasonable high-k and good thermal stability with amorphous type up to 1000^oC [4.5], [4.12], [4.15]-[4.21]. In contrast to the worse NBTI than PBTI in oxynitride devices, close NBTI and PBTI is found in fully NiSi-NiGe gates/Al2O3 CMOSFETs. At 17 Å EOT, the extrapolated maximum operation voltage (Vmax-10years) for 10 years lifetime, with 50 mV threshold voltage (Vt) change at 85^oC, is 1.16 V and -1.12 V from PBTI and NBTI, respectively. These results are comparable or better than the reported HfAlON [4.6] and HfSiON data [4.7]. The high Vmax-10years and close value for both NBTI and PBTI may be due to the process without hydrogen and H2O that were used during high-k HfAlON and HfSiON deposition by Atomic-Layer Deposition (ALD) using NH3 and H2O sources [4.6]. However, the inferior PBTI of NiSi-NiGe/Al2O3

CMOSFETs to oxynitride devices suggests that further improving the high-k dielectric quality is required.

4.2 Experimental

Standard n- and p-type (100) Si wafers with a typical resistivity of ~10 Ω-cm were used in this study. After standard cleaning, the device active region was formed

by thick field oxide and patterning. The source and drain region were implanted by 35 KeV Phosphorus or 25 KeV Boron for nMOSFETs or pMOSFETs respectively, followed by RTA activation. Then the ~39 Å Al2O3 was formed by physical-vapor deposition, 400^oC oxidation for 20 min. and 400^oC annealing for 20 min. From the C-V measurement, a k value of 8.9 and EOT of 17 Å were obtained. The slightly low-k value than bulk Al2O3 (k=10) is due to the oxidation of Si during post deposition annealing. The fully NiSi and NiGe gates were formed by depositing 150 Å amorphous Si or Ge on Al2O3, 150 Å Ni for both n- and p-devices, and followed by silicidation and germanidation at 400^oC RTA for 30 sec [4.5], [4.15]-[4-19]. For comparison, control oxynitride was formed by decoupled plasma nitridation [4.22] on a 18 Å SiO2 that was grown by oxygen at 700^oC for 12 min. The formed oxynitride has peak N concentration of 9% near poly gate interface, followed by post deposition annealing at 1000^oC RTA. The fabricated CMOSFETs were further characterized by C-V I-V, and Bias-Temperature (BT) measurements.

4.3 Results and Discussion

We have first measured the Ids-Vgs characteristics to examine the hysteresis effects in Al2O3. Fig. 4-1 and Fig. 4-2 show the measured hysteresis on NiSi/Al2O3

nMOSFETs and NiGe/Al2O3 pMOSFETs, respectively. For fully silicide/high-k

nMOSFET, the double sweep of gate voltage from 0 to 1.5 V results in Vt shifted to positive by +10 mV. This result suggests generating negative charge traps in nMOSFET. For pMOSFET, the double sweep of gate voltage from 0.5 to -1.5 V results in VT shifted to negative by -10 mV, which also indicates the generating positive charge traps in bulk Al2O3 and Al2O3/Si interface. These amounts of charge trappings may cause NBTI in pMOSFETs and PBTI in nMOSFETs. The poor Ioff in nMOSFETs is due to the insufficient high temperature annealing (only 950^oC RTA) for ion-implanted damage. The limited RTA temperature also gives a relative poor sub-threshold swing because of the insufficient annealing of high-k dielectric defects.

Further improving the leakage current and sub-threshold swing can be done by increasing RTA temperature to typical 1000-1050^oC or using LaAlO3 high-k dielectric [4.24], [4.25].

We have also used the C-V to measure the hysteresis effects. Fig. 4-3 and Fig.

4-4 show the CV hysteresis characteristics, measured at 500 KHz, on NiSi/Al2O3

nMOSFETs and NiGe/Al2O3 pMOSFETs respectively, where conventional bi-directional sweeps from inversion to accumulation were applied to these transistors.

The double sweeping hysteresis of +10 mV and ~0 mV are measured for nMOS and pMOS capacitors, respectively. The smaller flat band voltage shift of pMOS capacitor than the Vt shifts of Ids-Vgs curves in NiGe/Al2O3 pMOSFETs may be due to the

relative slower and deeper traps that were unable to follow the AC signal [4.23].

Similar effect is also observed in other high-k dielectrics from quasi-static to RF frequency range [4.24]-[4.27].

Figs. 4-5 and Fig. 4-6 shows the NBTI characteristics of Ids-Vgs and Vt change (∆Vt) for NiSi/Al2O3 pMOSFETs stressed at 10 MV/cm electric field and 85^oC ambient to 1 hour, respectively. This stress condition was chosen to compare with published data in the literature [4.6], [4.7]. For reference and comparison, the ∆Vt of SiON pMOSFETs and the data of TaN/HfAlO [4.6] are also plotted in Fig. 4-6. After the 1 hour stress at 10 MV/cm and 85^oC, a ∆Vt of -33 mV is measured suggesting that the NBTI is one of the most serious reliability issues for fully NiSi gate/high-k Al2O3

pMOSFETs. The measured ∆Vt changes are comparable or better than the published HfAlON [4.6], HfSiON [4.7] and HfTaO [4.1] where additional Al, N, Si or Ta must be added to HfO2 for BTI reliability improvement. However, the measured ∆Vt is still larger than that of oxynitride devices with plasma generated N at top poly-Si/oxynitride interface. The possible reason of the inferior NBTI is due to the degraded interface of Al2O3/Si and bulk oxide change in Al2O3, where oxygen-riched SiN interface on Al2O3 will be the possible solution for this important reliability issue [4.10]-[4.12].

Fig. 4-7 and Fig. 4-8 show the PBTI characteristics of Ids-Vgs and Vt for

NiGe/Al2O3 nMOSFETs stressed at 10 MV/cm electric field and 85^oC to 1 hour, respectively. The ∆Vt of SiON nMOSFETs are also added in Fig. 4-8 for comparison.

After the 1 hour BT stress, a ∆Vt of 34 mV is measured for PBTI that is close to the

-33 mV value in NBTI. In sharp contrast, the NBTI of only 0.76 mV is measured in poly-Si/oxynitride (9% peak at poly-Si interface) nMOSFETs after the same BT stress that is lower than the 6.6 mV change in oxynitride pMOSFETs. The better PBTI than NBTI is normal for oxynitride MOSFETs where the mechanism is attributed to hole injection to break the H-Si bonds and created interface traps [4.9]-[4.14].

However, the measured NBTI and PBTI value are less than that of HfO2 [4.7], [4.8], which may be due the strong A-O bond and consistent with the results in HfAlO [4.6].

However, the measured NBTI and PBTI value are less than that of HfO2 [4.7], [4.8], which may be due the strong A-O bond and consistent with the results in HfAlO [4.6].

在文檔中 高介電常數閘極介電質熱氧化氧化鋁在金氧半電晶體的電性及應用 (頁 38-0)