We have further fabricated wide gate MOSFETs with 4.8 Å EOT. Figs. 3-17 shows the device Id-Vd, and important Id-Vg and gm are plotted in Fig. 3-18. The very high current drive and gm are due to high-k that gives a k of ~27 consistent with C-V measurement. Good device pinch-off Ioff < 10-10A/µm and small sub-threshold swing of 75 mV/decade are observed, and the small swing also suggests the low Dit. The effective mobility is further plotted in Fig. 3-19. The electron mobility is comparable with published universal mobility data for thermal SiO2 because of low Dit.
3.3.2.3 Reliability
Fig. 3-20 shows the gate dielectrics under a -2.5 V constant stress for 1 hour with total Qinj of 1.3x103 and 1.2x105C/cm2 for La2O3 and Al2O3, respectively. No
significant charge trapping is occurred during stress, and small SILC for both dielectrics is observed in Fig. 3-21. Good reliability for 4.8 Å EOT La2O3 is evidenced from the high QBD in Fig. 3-22 and comparable with current SiO2 [3.12].
The good SILC and QBD may be due to the high lattice energy in Table 1-2. From the 50% failure time, an extrapolated max voltage of 2.3 V is obtained for 10 years lifetime that suggests good reliability for VLSI application with 4.8 Å EOT and small leakage of 0.06 A/cm2 at 1 V.
3.4 Conclusion
We report a very simple process to fabricate Al2O3 gate dielectric with k (9.0 to 9.8) greater than Si3N4. Al2O3 is formed by direct oxidation from thermally evaporated Al. The 48 Å Al2O3 has ~6 orders lower leakage current than equivalent 13 Å SiO2. Good Al2O3/Si interface was evidenced by the low interface density of 1x1011 eVcm-2 and compatible electron mobility with thermal SiO2. Good reliability is measured from the small SILC after 2.5 V stress for 10,000 sec.
High quality La2O3 and Al2O3 are fabricated with EOT of 4.8 and 9.6 Å, leakage current of 0.06 and 0.4 A/cm2 and Dit of both 3x1010 eV-1/cm2, respectively. The high-k is further evidenced from high MOSFET’s Id and gm with low Ioff. Good SILC
thermodynamic stability in contact with Si and stable after H2 annealing up to 550oC.
Fig. 4-1 SIMS depth profile of oxidized Al at 500oC. The measured thickness is close to that measured by ellipsometer & cross-sectional TEM.
0 100 200 300 400 500
10
110
210
310
410
510
6Al2O3/Si interface
Al O
Secondary Ion Counts
Depth (Angstroms)
(a)
(b)
Fig. 3-2 TEM photos of Al oxidized at (a) 400oC and (b) 500oC.
Al 2 O 3 Glue
100Å
Al 2 O 3 Glue
100Å
Crystal
100Å Crystal
100Å
0 1 2 3 4 5 6 7 8 10-11
10-9 10-7 10-5 10-3 10-1 101 103 105
48 A Al
2O
3
13 A SiO
2
Jg (A/cm2 )
Vg (Voltage)
Fig. 4-2 J-V characteristics of the 48 Å Al2O3 MOS capacitor.
Fig. 3-4 C-V characteristics of 110 Å Al2O3 MOS capacitor.
-2 -1 0 1 2
0 100 200 300 400 500 600
Capacitance (pF)
V (Voltage)
Fig. 3-5 Interface trap density of the Al2O3/Si interface.
-0.6 -0.4 -0.2 0.0 0.2 0.4
1010 1011 1012 1013 1014
Dit (ev/cm2 )
Energy (ev)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0
100 200 300 400 500 600 700
Al2O3 gate 80A SiO2 gate
u eff(cm2 /V-sec)
Es,eff (MV/cm)
Fig. 3-6 Electron mobilities of MOSFET’s with 80 Å Al2O3 and conventional SiO2. (M. S. Liang, J. Y. Choi, P. K. Ko, C. Hu, IEEE TED-33, no. 3, pp. 409-413, 1986.).
Fig. 3-7 Id-Vd characteristics of an 80 Å Al2O3 MOSFET. The high current drive in Al2O3 gives a k value of 9.8.
0 1 2 3 4 5
0.000 0.001 0.002 0.003 0.004 0.005
Al2O3 VG from 0V~5V SiO2 VG from 0V~5V
I D (A)
VD (Voltage)
Fig. 3-8 Current density changes of the 48 Å Al2O3 MOS capacitor under a constant voltage stress at 2.5 V for 10,000 sec.
0.0 2.0x103 4.0x103 6.0x103 8.0x103 1.0x104 10-9
10-8 10-7 10-6 10-5
J (A/cm2 )
Time (sec)
Fig. 3-9 SILC effect of the 48 Å Al2O3 MOS capacitor under a constant voltage stress at 2.5 V for 10,000 sec.
0 1 2 3 4 5
10-11 10-9 10-7 10-5 10-3
Before 2.5V 10000s stress After 2.5V 10000s stress
J (A/cm2 )
V (Voltage)
Fig. 3-10 Voltage changes of 48 Å Al2O3 MOS capacitor under a 0.1 mA/cm2 current density stress for 1000 sec.
0 200 400 600 800 1000
Fig. 3-11 SILC effect of 48 Å Al2O3 MOS capacitor under a 0.1 mA/cm2 current density stress for 1000 sec.
0 1 2 3 4 5
10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
Before 0.1mA/cm2 stress 1000s After 0.1mA/cm2 stress 1000s
J (A/cm2 )
V (Voltage)
Fig. 3-12 J-V characteristics for Al2O3 (9.6 & 16.5 Å EOT)and La2O3 (4.8 Å EOT) capacitors. Stacked structure is adopted to reduce leakage current for Dit
measurement.
Fig. 3-13 Cross-section TEM of Al2O3 and La2O3. Very smooth interface is due to the high thermal stability and native oxide free surface. Both dielectrics are amorphous.
La2O3
Glue 10nm Glue
Si Al2O3
Si
Fig. 3-14 Cumulative distribution of leakage current and breakdown field for Al2O3
and La2O3 gate dielectrics.
11 12 13 14 15
0 20 40 60 80 100
Cumulative Failure (%)
Breakdown Field (MV/cm)
0.01 0.1 1
Al2O3 21A
La2O3 33A
Leakage Current Density @ -1V (A/cm2)
Fig. 3-15 Hysteresis curves for Al2O3 and La2O3 gate dielectrics.
-3 -2 -1 0 1 2
0 100 200 300 400 500 600 700 800
Area=1x10-4 cm2 21A Al2O3
△VFB=22mV
33A La2O3
△VFB=11mV
Gate Voltage (V)
Capacitance (pF)
Fig. 3-16 Interface state density of Al2O3 and La2O3 on Si. Min Dit of 3x1010 eV-1/cm2 is obtained for both dielectrics and close to SiO2/Si.
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 1010
1011 1012
EOT=21.8A
EOT=16.5A 36A Al2O3 / 33A La2O3 / Si
36A Al2O3/Si
D it (ev-1 /cm2 )
Energy (ev)
Fig. 3-17 Id-Vd characteristics of 30 mm x 1200 mm nMOSFETs with 33 Å La2O3
gate dielectric.
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0
5 10 15 20
25 Vg=0.75V
Vg=0.6V Vg=0.45V Vg=0.3V Vg=0.15V
Drain Current (mA)
Drain Voltage (V)
Fig. 3-18 Subthreshold characteristic and transconductance for 33 Å La2O3
nMOSFETs as a function of gate bias.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Fig. 3-19 Effective electron mobility versus electrical field for 33 Å La2O3
nMOSFET.
0.1 1
102 103
Eeff (MV/cm) u eff(cm2 /V-sec)
Fig. 3-20 Time evolution of Ig under -2.5 V for 1 hr with Qinj of 1.3x103 and 1.5x105 C/cm2 for respective La2O3 and Al2O3.
0 400 800 1200 1600 2000 2400 2800 3200 3600 10-1
100 101 102
33A La2O3 CVS under -2.5V for 3600sec 21A Al2O3 CVS under -2.5V for 3600sec
Current Density (A/cm2 )
Time (second)
Fig. 3-21 Stress induced leakage current and current variation for Al2O3 and La2O3
(I stressed- I Fresh) / I fresh (%)
Fig. 3-22 QBD distribution of La2O3 dielectricwith different Vg. For 50% MTTF and 10 years lifetime, a max operation voltage of 2.3 V is obtained.
0 20 40 60 80 100 120 140 160 180 200 0
10 20 30 40 50 60 70 80 90 100
Vg=-3.3V Vg=-3.4V Vg=-3.5V
Cumulative Failure (%)
QBD (C/cm2)
Chapter 4
Bias-Temperature Instability and Charge Trapping on Fully-Silicided-Germanided Gates/High-k Al
2O
3CMOSFETs
4.1 Introduction
As continuous scaling down the MOSFET devices into sub-100 nm scale, oxynitride or metal-oxide high-k gate dielectric, with ultra-thin equivalent oxide thickness (EOT), is required to replace the conventional SiO2 to reduce gate dielectric leakage current. To further increase the drive current in MOSFET, metal gate will be integrated with these high-k gate dielectrics [4.1]-[4.5]. However, one of the main concerns of such metal-gate/high-k MOSFETs is the poor Bias-Temperature Instability (BTI) [4.1], [4.6]-[4.8]. In particular, the negative BTI (NBTI) of pMOSFETs is becoming an increasingly serious problem of the CMOS reliability. It is known that the NBTI of oxynitride gate dielectric pMOSFETs is mainly related to nitrogen traps [4.9]-[4.12], hydrogen [4.13]-[4.14], moisture (H2O) [4.14], and impurity diffusion [4.6] etc. Both the NBTI and positive BTI (PBTI) are even worse in metal-oxide high-k CMOSFETs than oxynitride devices [4.1], [4.6]-[4.8]. In this work, we have studied the BTI effect on fully silicided-germanided (NiSi-NiGe) dual
gates on high-k Al2O3 CMOSFETs [4.5], [4.15]-[4.19] and compared with a benchmark oxynitride devices. The fully silicided gate has advantage of fully process compatible to current VLSI fabrication technology. The Al2O3 gate dielectric has reasonable high-k and good thermal stability with amorphous type up to 1000oC [4.5], [4.12], [4.15]-[4.21]. In contrast to the worse NBTI than PBTI in oxynitride devices, close NBTI and PBTI is found in fully NiSi-NiGe gates/Al2O3 CMOSFETs. At 17 Å EOT, the extrapolated maximum operation voltage (Vmax-10years) for 10 years lifetime, with 50 mV threshold voltage (Vt) change at 85oC, is 1.16 V and -1.12 V from PBTI and NBTI, respectively. These results are comparable or better than the reported HfAlON [4.6] and HfSiON data [4.7]. The high Vmax-10years and close value for both NBTI and PBTI may be due to the process without hydrogen and H2O that were used during high-k HfAlON and HfSiON deposition by Atomic-Layer Deposition (ALD) using NH3 and H2O sources [4.6]. However, the inferior PBTI of NiSi-NiGe/Al2O3
CMOSFETs to oxynitride devices suggests that further improving the high-k dielectric quality is required.
4.2 Experimental
Standard n- and p-type (100) Si wafers with a typical resistivity of ~10 Ω-cm were used in this study. After standard cleaning, the device active region was formed
by thick field oxide and patterning. The source and drain region were implanted by 35 KeV Phosphorus or 25 KeV Boron for nMOSFETs or pMOSFETs respectively, followed by RTA activation. Then the ~39 Å Al2O3 was formed by physical-vapor deposition, 400oC oxidation for 20 min. and 400oC annealing for 20 min. From the C-V measurement, a k value of 8.9 and EOT of 17 Å were obtained. The slightly low-k value than bulk Al2O3 (k=10) is due to the oxidation of Si during post deposition annealing. The fully NiSi and NiGe gates were formed by depositing 150 Å amorphous Si or Ge on Al2O3, 150 Å Ni for both n- and p-devices, and followed by silicidation and germanidation at 400oC RTA for 30 sec [4.5], [4.15]-[4-19]. For comparison, control oxynitride was formed by decoupled plasma nitridation [4.22] on a 18 Å SiO2 that was grown by oxygen at 700oC for 12 min. The formed oxynitride has peak N concentration of 9% near poly gate interface, followed by post deposition annealing at 1000oC RTA. The fabricated CMOSFETs were further characterized by C-V I-V, and Bias-Temperature (BT) measurements.
4.3 Results and Discussion
We have first measured the Ids-Vgs characteristics to examine the hysteresis effects in Al2O3. Fig. 4-1 and Fig. 4-2 show the measured hysteresis on NiSi/Al2O3
nMOSFETs and NiGe/Al2O3 pMOSFETs, respectively. For fully silicide/high-k
nMOSFET, the double sweep of gate voltage from 0 to 1.5 V results in Vt shifted to positive by +10 mV. This result suggests generating negative charge traps in nMOSFET. For pMOSFET, the double sweep of gate voltage from 0.5 to -1.5 V results in VT shifted to negative by -10 mV, which also indicates the generating positive charge traps in bulk Al2O3 and Al2O3/Si interface. These amounts of charge trappings may cause NBTI in pMOSFETs and PBTI in nMOSFETs. The poor Ioff in nMOSFETs is due to the insufficient high temperature annealing (only 950oC RTA) for ion-implanted damage. The limited RTA temperature also gives a relative poor sub-threshold swing because of the insufficient annealing of high-k dielectric defects.
Further improving the leakage current and sub-threshold swing can be done by increasing RTA temperature to typical 1000-1050oC or using LaAlO3 high-k dielectric [4.24], [4.25].
We have also used the C-V to measure the hysteresis effects. Fig. 4-3 and Fig.
4-4 show the CV hysteresis characteristics, measured at 500 KHz, on NiSi/Al2O3
nMOSFETs and NiGe/Al2O3 pMOSFETs respectively, where conventional bi-directional sweeps from inversion to accumulation were applied to these transistors.
The double sweeping hysteresis of +10 mV and ~0 mV are measured for nMOS and pMOS capacitors, respectively. The smaller flat band voltage shift of pMOS capacitor than the Vt shifts of Ids-Vgs curves in NiGe/Al2O3 pMOSFETs may be due to the
relative slower and deeper traps that were unable to follow the AC signal [4.23].
Similar effect is also observed in other high-k dielectrics from quasi-static to RF frequency range [4.24]-[4.27].
Figs. 4-5 and Fig. 4-6 shows the NBTI characteristics of Ids-Vgs and Vt change (∆Vt) for NiSi/Al2O3 pMOSFETs stressed at 10 MV/cm electric field and 85oC ambient to 1 hour, respectively. This stress condition was chosen to compare with published data in the literature [4.6], [4.7]. For reference and comparison, the ∆Vt of SiON pMOSFETs and the data of TaN/HfAlO [4.6] are also plotted in Fig. 4-6. After the 1 hour stress at 10 MV/cm and 85oC, a ∆Vt of -33 mV is measured suggesting that the NBTI is one of the most serious reliability issues for fully NiSi gate/high-k Al2O3
pMOSFETs. The measured ∆Vt changes are comparable or better than the published HfAlON [4.6], HfSiON [4.7] and HfTaO [4.1] where additional Al, N, Si or Ta must be added to HfO2 for BTI reliability improvement. However, the measured ∆Vt is still larger than that of oxynitride devices with plasma generated N at top poly-Si/oxynitride interface. The possible reason of the inferior NBTI is due to the degraded interface of Al2O3/Si and bulk oxide change in Al2O3, where oxygen-riched SiN interface on Al2O3 will be the possible solution for this important reliability issue [4.10]-[4.12].
Fig. 4-7 and Fig. 4-8 show the PBTI characteristics of Ids-Vgs and Vt for
NiGe/Al2O3 nMOSFETs stressed at 10 MV/cm electric field and 85oC to 1 hour, respectively. The ∆Vt of SiON nMOSFETs are also added in Fig. 4-8 for comparison.
After the 1 hour BT stress, a ∆Vt of 34 mV is measured for PBTI that is close to the
-33 mV value in NBTI. In sharp contrast, the NBTI of only 0.76 mV is measured in poly-Si/oxynitride (9% peak at poly-Si interface) nMOSFETs after the same BT stress that is lower than the 6.6 mV change in oxynitride pMOSFETs. The better PBTI than NBTI is normal for oxynitride MOSFETs where the mechanism is attributed to hole injection to break the H-Si bonds and created interface traps [4.9]-[4.14].
However, the measured NBTI and PBTI value are less than that of HfO2 [4.7], [4.8], which may be due the strong A-O bond and consistent with the results in HfAlO [4.6].
The close PBTI and NBTI absolute value after BT stress in Al2O3 MOSFETs suggesting the higher number of interface and bulk traps, which are normal for high-k gate dielectric, are the main causes and for larger ∆Vtchange than oxynitride devices.
We have also measured BTI at other gate electric field for 10 years lifetime projection, where the lifetime at each gate voltage was defined by a ∆Vt=50 mV change during stress. Such high gate voltage or electric field is especially required for poly-Si/SiON CMOS due to the excellent reliability. Figs. 4-9 show the time as a function of Vgs of nMOSFETs and pMOSFETs, respectively. The 10 years lifetime
Vmax-10years is from the extrapolation of measured data at high gate voltage. The extrapolated Vmax-10years are 1.16 and -1.12 V for Al2O3 nMOSFETs and pMOSFETs, respectively. Theses values can barely meet the BTI requirement at 1 V operation with additional 10% safety margin to 1.1 V. It is important to notice that the degraded PBTI is also reported in HfAlON gate dielectric MOSFETs [4.6] that is even worse than NBTI and attributed to gate impurity diffusion. The close Vmax-10years for PBTI and NBTI in Al2O3 MOSFETs is simply because no impurity [4.6], nor hydrogen annealing [4.13]-[4.14] or processing water [4.6], [4.14] were added to the fully NiSi-NiGe/Al2O3 CMOSFETs. Unfortunately, these values are lower than the 2.48 and -1.52 V of respective PBTI and NBTI extrapolation for oxynitride MOSFETs at close EOT. The main mechanism for NBTI degradation in poly-Si/SiON pMOS is due to the trap generation by energetic holes in bulk oxide and interface. In contrast, the poorer BTI in high-k MOSFETs may be directly related to the existing high bulk and interface traps. Therefore, further technology development to reduce these traps or using an oxygen-riched SiN interface beneath the high-k [4.10]-[4.12] is the key factor for metal-gate/high-k CMOS BTI reliability.
4.4 Conclusion
We have studied the NBTI and PBTI of 17 Å EOT NiSi-NiGe/Al2O3
CMOSFETs, with baseline characteristics of 10 mV hysteresis. The comparable Vt
change of -34 and 33 mV for respective NBTI and PBTI, after 10 MV/cm and 85oC stress for 1 hour, is probably due to impurity free in NiSi or NiGe gate and no hydrogen or water used in device process. The amount of Vt change and extrapolated Vmax-10years of 1.16 and -1.12 V in NiSi-NiGe/Al2O3 CMOSFETs are comparable with or better than the reported BTI data of HfSiON and HfAlON that suggesting the good high-k device integrity. Although the Vmax-10years of NiSi-NiGe/Al2O3 CMOSFETs can barely meet the 1 V operation requirement, better performance is found in oxynitride CMOSFETs with higher Vmax-10years of 2.48 and -1.52 V of PBTI and NBTI, respectively. In addition to almost the same NBTI and PBTI values in NiSi-NiGe/Al2O3 CMOSFETs, the comparison with oxynitride CMOSFETs suggests the bulk and interface oxide traps in high-k Al2O3 dielectric plays the dominant role for BTI. Therefore, further improving the device performance is required for metal-gate/high-k CMOSFETs including BTI and mobility degradation effects.
Fig. 4-1 The room temperature Ids-Vgs characteristics of NiSi/Al2O3 nMOSFETs under double sweep measurements. The inserted figures are the enlarged view to show the hysteresis.
0.0 0.5 1.0 1.5
10-7 10-6 10-5 10-4
nMOSFET
VDS=0.1V, T=300K 0 to 1.5V (single) 0 to 1.5V (double)
Drain Current (A/µm)
Gate Voltage (V)
0.60 0.65 0.70 0.75 0.80 10-6
10-5
Drain Current (A/µm)
Gate Voltage (A)
Fig. 4-2 The room temperature Ids-Vgs characteristics of NiGe/Al2O3 pMOSFETs under double sweep measurements. The inserted figures are the enlarged view to show the hysteresis.
0.5 0.0 -0.5 -1.0 -1.5
Fig. 4-3 The room temperature C-V characteristics of NiSi/Al2O3 nMOS capacitors under double sweep measurements. The inserted figures are the enlarged view to show the hysteresis.
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Fig. 4-4 The room temperature C-V characteristics of NiGe/Al2O3 pMOS capacitors under double sweep measurements. The inserted figures are the enlarged view to show the hysteresis.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Fig. 4-5 The Ids-Vgs changes of NiGe/Al2O3 pMOSFETs stressed at 85oC and 10 MV/cm for 1 hour.
0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5
10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
pMOSFET
3600 sec stress at 10 MV/cm and 85oC
before stress after stress
Drain Current (A/µm)
Gate Voltage (V)
Fig. 4-6 The ∆Vt changes of NiGe/Al2O3 pMOSFETs stressed at 85oC and 10 MV/cm for 1 hour. For comparison, the data from poly-Si/SiON and TaN/HfAlO (from reference 6) are also added under the same stress condition.
100 101 102 103 104
100 101 102 103
pMOSFET, 10 MV/cm and 85oC
50 mV
TaN/HfAlO [4.6]
NiGe/Al2O3 poly-Si/SiON
−∆ V t (mV)
Time (sec)
Fig. 4-7 The Ids-Vgs change of NiSi/Al2O3 nMOSFETs stressed at 85oC and 10 MV/cm for 1 hour.
-0.5 0.0 0.5 1.0 1.5
10-8 10-7 10-6 10-5
Al2O3 nMOSFET
3600sec stress @ 10MV/cm, 85oC
before stress after stress
Drain Current (A/µm)
Gate Voltage (V)
Fig. 4-8 The ∆Vt changes of NiSi/Al2O3 nMOSFETs stressed at 85oC and 10 MV/cm for 1 hour. For comparison, the data from poly-Si/SiON and TaN/HfAlO (from reference 6) are also added under the same stress condition.
100 101 102 103 104
10-1 100 101 102 103
50 mV
nMOSFET, 10 MV/cm and 85OC TaN/HfAlO [4.6]
NiSi/Al2O3 poly-Si/SiON
∆ V t (mV)
Time (sec)
Fig. 4-9 The extrapolated maximum operation voltage for 10 years lifetime of NiSi/Al2O3 nMOSFETs and NiGe/Al2O3 pMOSFETs under failure condition of 50 mV change in Vt at 85oC. The data from oxynitride is also
Chapter 5
The Copper Contamination Effect on Al
2O
3Gate Dielectric on Si
5.1 Introduction
To reduce the circuit’s RC delay from backend metal lines and parasitic capacitors, Cu and low-k dielectric are required. However, Cu diffusion into low-k and front-end MOSFETs is an important issue [5.1]-[5.12]. The Cu contamination from backend Cu interconnects or the backside wafer surface contaminated by Cu will accumulate at the Si/SiO2 interface [5.6]-[5.8] or reacts with Si to form silicide. The precipitate Cu at oxide interface will increase the sub-threshold swing of MOSFETs [5.7], [5.9], shift the threshold voltage, and degrade the gate leakage current [5.10]-[5.12]. The Cu silicide will also increase the unwanted leakage current in source-drain junction.To reduce Cu diffusion during backend thermal cycle, barrier metal under Cu and thick SiN between each inter-metal layer (IML) dielectric are usually added. However, the added SiN of typical 500 Å has large k value of 7.5 and will degrade the total k of combined IML dielectric and SiN. The increasing effective k is unfavorable since it will increase the circuit’s backend RC delay. In this paper, we have studied the Cu contamination effect in high-k Al2O3 gate dielectric [5.13]-[5.16]
with small equivalent-oxide thickness (EOT) of 19 Å, where the high-k gate dielectric is important for continuously scaling down the nm-scale MOSFET. In contrast to the large degradation of gate oxide integrity in 30 Å thermal SiO2, the smaller 19 Å EOT Al2O3 gate dielectric shows much better resistance to Cu contamination related degradation on gate dielectric leakage current, charge-to-breakdown (QBD) and stress-induced leakage current (SILC). Therefore, the high-k gate dielectric with Al2O3 ternary compound such as HfAlO or LaAlO3 should have this additional advantage besides the high-k value.This is the first study of Cu diffusion in high-k Al2O3.
5.2 Experimental
Standard four-inch, p-type (100) Si wafers with a typical resistivity of ~10 Ω-cm were used in this study. After standard cleaning, the device active region was formed by thick field oxide and patterning. Then the ~42 Å Al2O3 was formed by physical-vapor deposition from an Al2O3 sputter source, oxidation at 400oC under O2
ambient for 5 min and annealed at N2 ambient for 25 min. From the C-V measurement, a k value of 8.5 and EOT of 19 Å were obtained. Then the gate electrode was formed by depositing a 3000 Å thick aluminum by thermal evaporation and patterning, where the fabricated area of MOS capacitors is 100 µm × 100 µm. The Cu contamination to
the Al2O3 MOS devices was introduced by contacting the front side of devices into a Cu(NO3)2 solution with 10 ppb or 10 ppm concentration for 1 minute then followed by driving-in at 400oC N2 annealing. The existence of Cu within gate SiO2 by this contamination process was confirmed by SIMS measurements reported previously [5.11], where strong Cu accumulation is observed in both poly-Si and SiO2. More detailed Cu contamination process and the degradation on gate dielectric integrity of
the Al2O3 MOS devices was introduced by contacting the front side of devices into a Cu(NO3)2 solution with 10 ppb or 10 ppm concentration for 1 minute then followed by driving-in at 400oC N2 annealing. The existence of Cu within gate SiO2 by this contamination process was confirmed by SIMS measurements reported previously [5.11], where strong Cu accumulation is observed in both poly-Si and SiO2. More detailed Cu contamination process and the degradation on gate dielectric integrity of