Conclusion

In this paper, the use of the Pt buried gate technology for the enhancement of the

RF and logic performance of the HEMTs has been demonstrated. The HEMTs exhibit high Ids =1418mA/mm; high gm =1590 mS/mm, and a fT (fmax) of 494 GHz (390 GHz) after gate sinking. This is believed to be the highest value ever achieved for an 80 nm HEMT devices. In evaluating the devices for ultra-low DC power consumption LNA applications, the device exhibits the minimum noise figure at 17 GHz was 0.82 dB with corresponding associated gains 14 dB when biased at a VDS of 0.3 V.

Additionally, the logic performance of such device has also been characterized and a very low intrinsic gate delay (0.78 psec) with an ION/IOFF ratio in the excess of 10³were obtained at VDS = 0.6 V. Overall, the performance improvement after gate sinking was mainly attributed to the increase of gm and the decrease in the corresponding capacitances of the device. The results demonstrate that superior HEMT device performance for high frequency, high-speed and low-power logic applications can be achieved through very simple gate sinking process with optimal epitaxy structure.

Fig. 4-1 The schematic view of the device structure and the insert SEM image is the 80-nm T-shaped gate after recess before silicon nitride passivation.

0.0 0.2 0.4 0.6 0.8 1.0 0

200 400 600 800 1000 1200 1400 1600

Device with gate sinking

Vg = -1 V Vg = -0.75 V Vg = -0.5 V Vg = -0.25 V Vg = 0 V

D rai n curr ent (m A /m m )

Drain-source Voltage, V

_D

(V)

Fig. 4-2 Drain-source current versus drain-source voltage curve for device with gate sinking.

0.0 0.2 0.4 0.6 0.8 1.0 0

300 600 900 1200 1500

Device without gate sinking Vg = 0 ~ -1V, step:-0.25V

D rai n current (m A/ m m )

Drain-source Voltage, V

_D

(V)

Fig. 4-3 Drain-source current versus drain-source voltage curve for device without gate sinking.

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

InAs/In_0.7Ga_0.3As HEMTs

Gate-drain breakdown voltage (V_BR)= 3.6 V Compliant I_DG = 1 mA/mm

Gate-drain current I GD (mA/mm)

Gate-drain voltage V

_GD

(V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

G ate -d ra in c urr en t I

GD

( mA /mm)

Gate-drain voltage V

_GD

(V)

Fig. 4-4 Two terminal gate-to-drain breakdown characteristics of device with/without gate sinking

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

D rai n-source current I

ds

(m A /m m )

Gate-source Voltage, V

_gs

(V)

Transconduct ance g

m

(m S/ m m )

before gate sinking After gate sinking at 250⁰C for 3 min

Fig. 4-5 Transconductance versus gate-source voltage before and after gate sinking at 250^oC for 3 min.

1 10 100 1000 0

10 20 30 40

f

_max

= 390 GHz

f

_T

=494 GHz U

H

₂₁

MAG/MSG

Gai n ( dB)

Frequency (GHz)

L

_g

= 80 nm W

_g

= 2 x 50

µ

m V

_D

= 0.8 V V

_G

= -0.5 V

Fig. 4-6 Frequency dependence of the current gain H21, the power gain MAG/MSG, and the unilateral gain U of the InAs/In0.7Ga0.3As composite channel HEMTs. The frequency range was from 5 to 80 GHz, and the device was biased at Vds = 0.8V and Vgs = -0.5V.

1 10 100 1000 0

10 20 30 40 50

f

_max

=360 GHz f

_T

=390 GHz

InAs HEMTs L_g=80nm W_g=2X50 µm V_D=0.8V V_g=-0.55V

MAG/MSG H

₂₁

U

Gai n ( dB )

Frequency (GHz)

Fig. 4-7 Typical current gain H21, MAG/MSG, and unilateral gain U as a function of frequency of the 0.08 × 100 µm² HEMTs before gate sinking.

Gate Sinking Non Gate Sinking

Gate Sinking Non Gate Sinking

Fig. 4-8 Measured S11 of devices with and without gate sinking under the same bias condition. Note that this bias condition gives the smallest intrinsic gate delay for the devices.

1 10

Fig. 4-9 Measured noise performance of the device at drain voltage VDS = 0.1V (a) device with gate sinking, Ids = 0.25 mA/mm (b) device without gate sinking, Ids = 0.34 mA/mm.

1 10

Fig. 4-10 Measured noise performance of the device at drain voltage VDS = 0.3V (a) device with gate sinking, Ids = 3.80 mA/mm (b) device without gate sinking, Ids = 2.52 mA/mm.

10

¹

10

²

10

³

10

⁴

1

10

¹

10

²

10

³

10

⁴

1

0.7 0.8

G ate d ela y ( pse c) 0.9

I

_ON

/I

_OFF

With gate sinking

2

In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite channel HEMTs V_CC @ 0.6 V

Without gate sinking

Fig. 4-11 The calculated intrinsic gate delay as a function of ION/IOFF ratio with various choices of the threshold voltage for device with/without sink.

Table 4.1 Summary of the HEMT device parameters with and without gate sinking.

InAs/ In0.7Ga0.3As HEMTs Cgs Cgd Cds Gm (RF) fT (GHz) fmax (GHz) Without gate sinking 73.3 fF 16.3 fF 5.3fF 201mS 390 GHz 360 GHz Gate sinking 60.5 fF 16.6 fF 3.7fF 208mS 494 GHz 390 GHz

Chapter 5

InAs-Channel Based Quantum Well Transistors for High-Speed and Low-Voltage Digital Applications

5.1 Introduction

For device scaling in Si technology, the physical gate length of Si transistors used in the current 65 nm generation node is about 30 nm and the size of the transistor will reach 10 nm in 2011. The International Technology Roadmap of Semiconductors Winter Public Conference 2007 (ITRS 2007) also forecasted integration of planar III-V compound semiconductor FETs with Si technology is one of the promising solutions for the CMOS technology to extend Moore’s law well into the next decade [5-1] – [5-5]. Generally, III-V materials have about 50 to 100 times higher electron mobility than Si and the resulting III-V-based transistors are showing very attractive merits over scaled Si MOSFETs. The extremely high transconductance and excellent RF performance have been demonstrated recently by InAlAs/InGaAs MHEMTs on GaAs substrate or InP substrate with ultra short gate length [5-6,5-7].

Low DC power consumption is always a highly desired property for practical system applications. However, maintaining device performance with low drain bias can only be achieved through optimized device technology which also plays a critical role for high-speed low-power digital applications. Having the properties of electron mobility as high as 20,000 cm²/Vs at room temperature, higher electron peak velocity, low electron effective mass and a reasonable energy bandgap (0.36 eV), InAs

materials have attracted numerous attentions as channel layer of Quantum Well FETs (QWFETs) for future high-speed and low-power digital applications [5-8].

In this letter, nano scale In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel QWFETs were fabricated and evaluated for high-speed and low-power digital applications. The devices demonstrated excellent DC, RF, and logic performances, indicating the suitability for ultra-high speed and low power digital applications.

5.2 Experimental

The epitaxial layer structure of the InAs-channel QWFETs was grown by molecular beam epitaxy (MBE) on 2-in InP substrate. Fig. 5-1 shows the detailed epitaxial structure of the 80 nm InAs-channel QWFETs in this study. The In0.7Ga0.3As sub-channels were applied to enhance the electron confinement in the thin InAs layer and improve the electron transport properties [5-8]. An InP layer could provide a good gate etching stop layer as well as a good surface passivation of InAlAs layer to avoid kink effect and reduce the hot-electron surface damage [5-9]. Besides, with the use of the InP etching stop layer, the lateral recess length (Lr) can be easily controlled and RF performance can be improved [5-10,5-11]. The room temperature 2DEG density and electron mobility measured were 4.34×10¹² /cm² and 12,000 cm²/Vs, respectively.

For the device fabrication, mesa isolation was done by a phosphoric based solution first. The device was etched to the buffer layer in order to attain a good isolation. After rapid thermal annealing of ohmic metal (Au/Ge/Ni/Au) in forming gas ambient, low ohmic contact resistance (RC) and sheet resistance were achieved and measured by transmission line method. The values were 0.02 Ω‧mm and 37.4Ω/□, respectively. A conventional tri-layer resist system of ZEP-520/PMGI/ZEP520 was used for the T-shaped gate fabrication by E-Beam lithography with double exposure

and double development. The recess etching was performed carefully using pH-adjusted solution of succinic acid (S.A.) and H2O2 mixture to selectively etch heavily doped cap layer over InP layer. After gate metal deposition, the T-shaped gate was formed by lift-off technique. The gate length of the T-shaped gate was 80nm with 2µm source-to-drain spacing achieved. Finally, a 100-nm thick silicon nitride was deposited as passivation layer by PECVD at 250 ^oC for 10 min. Special attention must be paid during the heat treatment process to avoid the degradation of the contact resistance values since these values are critical for high-speed low-power digital applications.

5.3 Results and Discussion

Fig. 5-2 shows the measured current-voltage characteristics of a 0.08 × 40 µm² device. As observed from the figure, this device can be well pinched off with a threshold voltage (VT) of -0.81 V and the maximum drain-source current of 1015 mA/mm at VDS = 0.5 V and Vgs = 0V. The threshold voltage is defined as the Vgs when Ids reaches 1mA/mm. This very high drain current density was mainly due to the superior electron mobility in the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel and the very low ohmic contact resistance. The transconductance gm and the drain source current versus Vgs with various VDS are shown in Fig. 5-3. The maximum gm peak of the device at a VDS of 0.5 V was 1900 mS/mm. The extremely high transconductance was due to higher carrier concentration and superior electron transport properties in the InAs channel. Compared with InxGa1-xAs QWFETs, the In0.52Ga0.48As QWFETs shows a transconductance of 823 mS/mm at VDS = 1.5 V and is shown in Fig 5-4. On the other hand, the transconductance of In0.7Ga0.3As QWFETs is 1050 mS/mm at VDS

= 1.5 V showing in Fig 5-5. The results clearly indicated that the InAs-channel

QWFETs can be biased at a low supply voltage to reduce overall dc power consumption, while maintaining relatively high current density and transconductance.

The two terminal gate-to-drain breakdown voltage (BVGD) was measured to be -2.5 V, defined at IGD = -1mA/mm.

The S-parameter of the device was measured using Cascade Microtech^TM on-wafer probing system with HP8510XF vector network analyzer from 5 to 80 GHz.

A standard Load-Reflection-Reflection-Match (LRRM) calibration method was used to calibrate the measurement system and the calibrated reference planes were at the tips of the corresponding probes. The parasitic effects (mainly capacitive) from the probing pads have been carefully removed from the measured S-parameters using the same method as in ¹² and the equivalent circuit model in ¹³. Since the geometry of the probing pads are relatively large compared to the device itself, the S-parameters of the open probing pads have also been rigorously characterized through full-wave electromagnetic simulations with measurement. The capacitance at the gate-source end and gate-drain end were extracted to be 13.9 fF and 10.3 fF, respectively. Before RF measurements, we must find the optimum DC bias to obtain the maximum current gain and power gain. Fig. 5-6 shows the Ids and VDS dependence of fT curves. From the figure, InAs device could exhibits exceeding 360 GHz at VDS = 0.5 V at the range of 200 mA/mm to 500 mA/mm. The current gain cutoff frequency (fT) and maximum available (stable) gain (MAG/MSG) as a function of frequency are plotted in Fig. 5-7.

The extracted current gain cut-off frequency fT and maximum oscillation frequency fmax are 393 GHz and 260 GHz at drain bias of 0.5 V, respectively, by extrapolating H21 and MAG/MSG with a -20 dB/decade slope. Apparently, the excellent fT is owing to the extremely high transconductance value. Moreover, the dc power dissipation was 5.8 mW when the device was biased at peak fT and fmax.

Care must be taken while biasing devices with such narrow energy bandgap values

since the occurrence of impact ionization will certainly degrade the performance of devices. Fig. 5-8 (a) shows the measured H21 at 80 GHz as a function of drain voltages for InAs/In0.7Ga0.3As channel HEMTs. It is obvious that H21 has the highest gain at drain voltage 0.8 V and decreases when the bias voltage increases. The main reason is that the impact ionization occurred at VDS = 0.8 V and the generated electrons failed to keep up with the electronic field modulation at RF frequency, causing a drop in RF gain even at higher drain voltages. The gate current plotted as a function of gate voltage at different drain bias is shown in Fig. 5-8 (b). The dramatic increase in gate leakage current further evidenced the occurrence of impact ionization for biases higher than 0.8. This is because some holes produced during gate voltage increase transferred over the barrier to the gate region due to the impact ionization phenomenon.

The procedure as proposed by R. Chau, et. al [5-1] was adopted for the evaluation of digital performance of such non-optimized VT device to avoid possible erroneous and physically meaningless values of logic parameters. The on-state (off-state) current was defined as the Ids corresponding to a Vgs 2/3 (1/3) of the difference between the drain bias and the threshold voltage. Fig. 5-9 shows the sub-threshold characteristics of the device with different drain biases. The Drain Induced Barrier Lowering (DIBL) and sub-threshold slope (SS) were calculated to be 200 mV/V and 115 mV/dec, respectively. The DIBL and SS for device with In0.7Ga0.3As channel were 156 mV/V and 110 mV/dec, shown in Fig. 5-10.

The very important figure of merit for high speed operation of logic transistors, the intrinsic gate delay (CtotalV/ION), has also been investigated. According to the definition, Ctotal is the total gate capacitance including gate-to-source capacitance (Cgs) and gate-to-drain capacitance (Cgd) extracted from high-frequency S-parameter measurement at corresponding bias conditions. V and ION are the applied drain

voltage and on-state current, respectively. As is observed from such definition, the gate delay is strongly dependent on the choice of the gate bias. The Lundstrom at Purdue university proposed this kind of methodology to explore suitability of novel devices with non-optimized VT, as shown in Fig. 5-11. Thus, the extracted gate delay as a function of the gate bias, VT’ as defined by Lundstrom et al.¹⁴, is shown in Fig.

5-12. It is observed that the device yields a very low intrinsic gate delay time of 0.54 psec at 0.5 V drain bias with VT’ = - 0.56 V. This very low intrinsic gate delay value is also attributed to the very high effective channel mobility. Fig. 5-13 shows the ION/IOFF current ratio as function of various VT as defined in reference 14. Peak ION/IOFF ratio in the excess of 10³ has been observed in the Fig. 5-13, indicating the excellent performance of such devices for high speed logic application.

The comparisons of 80 nm InAs QWFETs, 200 nm InSb QWFETs and advanced 40 nm Si MOSFET between gate delay and ION/IOFF ratio were plotted in the Fig. 5-14.

The InAs QWFETs exhibits a far better ION/IOFF ratio than the InSb QWFETs while getting up to subpicosecond intrinsic speed at the same time. Furthermore, the gate delay of InAs or InSb QWFETs are very much dependent on the ION/IOFF as compared to the Si MOSFETs. This is mainly due to the off-state current of QWFETs determined by the gate leakage current. It was limited resulting from band-to-band tunneling (BTBT) in such small energy band gap and lower effective conductivity mass (m*). Therefore, the use of a high-k gate dielectric between the metal gate and the III-V device layers will eliminate such gate leakage and potentially improve the ION/IOFF ratio [15].

Cutoff frequency (fT) versus DC power consumption of the 80 nm device under different drain biases are plotted in Fig. 5-15 with the published data ¹⁶ of 80 nm Si MOSFETs biased at 0.7 V also included for comparison. We can conclude from the plot that InAs channel-based QWFETs can achieve higher fT under the same level of

DC power consumption since the InAs channel can provide better electron transport properties. Fig. 5-16 shows the comparison of delay time as a function of gate length for different device technologies [5-1,5-3]. It is clear that InAs QWFETs exhibit lower gate delay than the state-of-the-art Si n-channel MOSFETs when compared at the same gate length.

Finally, to further improve the ION/IOFF ratio, a suitable high-k material and metal gate stack for QWFETs can reduce the gate leakage current effectively. The I-V characteristics of the Metal-Insulator-Semiconductor QWFETs capacitor were compared with those of the schottky metal gate QWFETs formed on the same epiwafer, as shown in Fig. 5-17. As seen from the plot, the insulated gate structure reduced the leakage current by more than 5 orders of magnitude under a negative bias and 9 orders of magnitude under a positive bias compared to schottky metal gate.

5.4 Conclusion

The 80 nm In0.7Ga0.3As /InAs/In0.7Ga0.3As composite channel QWFETs have been fabricated and evaluated its for high-speed low-power digital applications. The device exhibited high Ids =1015 mA/mm; high gm =1900 mS/mm, and a fT (fmax) of 393 GHz (260 GHz) at low drain bias voltage (VDS = 0.5 V). Additionally, a very low intrinsic gate delay of 0.54 psec was achieved due to the superior transport properties of the InAs channel. The InAs QWFETs exhibit better ION/IOFF performance than InSb QWFETs at an equivalent gate delay. With further combination of high-k dielectric and schottky metal gate, the off-state current could be reduced significantly. These results demonstrated that the InAs channel-based QWFETs have great potential for high-speed and low-power digital applications and are potential candidates for applications in post-Si generations.

Fig. 5-1. Epitaxial layer structure of the InAs/In0.7Ga0.3As HEMTs.

0.0 0.1 0.2 0.3 0.4 0.5 0

200 400 600 800 1000

D rain C urr ent (m A /m m )

Drain-Source Voltage (V)

InAs QWFETs Lg = 80 nm

S-D spacing = 2 µm Vg = 0 ~ -0.8 V Step: -0.2

Fig. 5-2. Drain-source current versus drain-source voltage curve

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

Transconductance (mS/mm)

V_DS = 0.2 ~ 0.5 V

Fig. 5-3. Current-voltage characteristics at different VDS of 0.08 × 40 µm² QWFETs.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0

100 200 300 400 500 600

_In

0.52Ga_0.48As QWFETs V_DS@1.5V

Lg = 80 nm

Vgs (V)

D rai n curr ent (m A /m m )

0 200 400 600 800 Transconduct ance (m S/m m )

Fig. 5-4 Current-voltage characteristics of In0.52Ga0.48As QWFETs.

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

T ransconductance (m S/m m )

Fig. 5-5 Current-voltage characteristics of In0.7Ga0.3As QWFETs.

0 100 200 300 400 500 600 700 800 240

260 280 300 320 340 360 380 400

f

T

(G H z)

Current density (mA/mm)

InAs HEMTs V

_DS

= 0.4 V V

_DS

= 0.5 V

Fig. 5-6. Cutoff frequency vs. Ids and VDS of InAs HEMTs

1 10 100 1000

Fig. 5-7. Frequency dependence of the current gain H21, and the power gain MAG/MSG of the InAs/In0.7Ga0.3As composite channel QWFETs. The frequency range was from 5 to 80 GHz, and the device was biased at VDS = 0.5 V and Vgs = - 0.45 V.

-1.0 -0.8 -0.6 -0.4 -0.2

InAs/In_0.7Ga_0.3As Channel QWFETs V_DS = 0 - 0.9 V

∆V = 0.1 V

Gate Leakage current IG (mA/mm)

Gate Source Voltage, V_GS (V) 0.60 0.65 0.70 0.75 0.80 0.85 0.90

7.6

Drain Source Voltage, V_DS (V) InAs/In_0.7Ga_0.3As Channel QWFETs

Fig. 5-8. InAs/In0.7Ga0.3As Channel HEMTs (a) Plot of H21 measured at 80 GHz versus drain-source voltage of 0.08 × 100 µm² (b) Gate current IG plotted as a function of VG at different VDS from 0 V to 0.9 V.

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 10

^-3

10

^-2

10

^-1

10

⁰

10

¹

10

²

10

³

I

_on

I

_off

V

_T

=-0.81V

Log (Ids) m A /m m

Gate Voltage (V)

InAs QWFETs V_DS = 0.05 V V_DS = 0.5 V

Fig. 5-9. The sub-threshold characteristics of the device with InAs channel at the VDS

of 0.05 and 0.5V.

Fig. 5-10. The sub-threshold characteristics of the device with In0.7Ga0.3As channel at the VDS of 0.05 and 0.5V.

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 10

^-3

10

^-2

10

^-1

10

⁰

10

¹

10

²

10

³

I

_OFF

I

_ON

V

_T

= -0.69 V

Log (Id) (m A/m m )

Vgs (V)

V

_cc

= 0.05 V

V

_cc

= 0.5 V

Fig. 5-11. The methodology for the evaluation of the logic performance of novel devices with non-optimized VT. Different definitions of VT result in a new set of logic parameters of C’V’/I’.

0.05 0.10 0.15 0.20 0.25

0.0 0.2 0.4 0.6 0.8 1.0 1.2

InAs QWFETs V

_DS

= 0.5 V

G ate delay ( ps ec)

V

_T

'-V

_T

Fig. 5-12. Gate delay as a function of the selected threshold voltage.

-0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 10

¹

10

²

10

³

10

⁴

I

ON

/I

OFF

V

_T

'-V

_T

V

_DS

= 0.5 V

Fig. 5-13 ION/IOFF ratio as function of various VT at the drain voltage 0.5 V.

10

¹

10

²

10

³

10

⁴

0.1

1

G at e delay (psec)

I

_ON

/I

_OFF

InAs QWFETs, V_DS = 0.5 V InSb QWFETs, V_DS = 0.5 V Si MOSFET, V_DS = 1.1 V

Fig. 5-14 Comparison between gate delay and ION/IOFF of 80 nm InAs QWFETs, 200 nm InSb QWFETs and 40 nm Si MOSFETs.

10 100 0

50 100 150 200 250 300 350 400 450 500

500

Si NMOS, Lg = 80 nm, V_DS = 0.7 V

C utoff Fr equency, f

T

( GHz)

Power Dissipation (mW/mm)

InAs QWFETs, Lg = 80 nm, V_DS = 0.5 V InAs QWFETs, Lg = 80 nm, V_DS = 0.4 V

Fig. 5-15. Cutoff frequency of InAs QWFETs and 80 nm Si MOSFETs as a function of the power dissipation

1 10 100 1000 0.1

1 10

G ate de lay tim e ( ps ec )

Gate length, Lg (nm)

Si NMOSFETs V_DS = 1.1 ~ 1.3 V InSb QWFETs V_DS = 0.5 V InAs QWFETs V_DS = 0.5 V

Fig. 5-16. Gate delay of InAs, InSb QWFETs and Si NMOSFETs as a function of gate length.

-4 -3 -2 -1 0 1 2 3 4 10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

9 orders of magnitude 5 orders of magnitude

L eakage current density (A /cm

2

)

Gate bias (V)

Schottky Metal gate

Metal Insulator Semiconductor gate

Fig. 5-17. I-V characteristics of MIS QWFETs and Schottky metal gate QWFETs.

Chapter 6

Metamorphic In

0.53

Ga

0.47

As Metal-Oxide-Semiconductor Structure on a GaAs Substrate with ZrO

2

High-k Dielectrics

6.1 Introduction

The downscaling of complementary metal-oxide-semiconductor (CMOS) devices in the past few decades has followed Moore’s law. Si-based MOS device technology has moved into the deep sub-nanometer generation phase. However, in the 21^st century, it has approached its intrinsic mobility limits for Si technology beyond a 22 nm node. In recent years, III-V compound semiconductor devices, such as InxGa1-xAs-based quantum-well field-effect transistors (QWFETs), have attracted considerable attention for high-speed digital applications because of the high electron mobility of the III-V materials [6-1,6-2]. As a result, III-V-based devices are considered very promising alternatives to the current Si-based devices.

To date, silicon dioxide, silicon nitride and alumina have been investigated as gate insulators on III-V materials. However, the high dielectric permittivity of ε～25, large band gap of EG ～ 7.8 eV, good thermal stability, high hardness and high melting point have made zirconium dioxide (ZrO2) an ideal candidate as the gate oxide for III-V materials [6-3,6-4]. However, unlike the stable interface between Si and silicon dioxide in a Si MOS structure, there is no high-quality insulator suitable for compound semiconductors. Consequently, for the deposition of insulator film on

To date, silicon dioxide, silicon nitride and alumina have been investigated as gate insulators on III-V materials. However, the high dielectric permittivity of ε～25, large band gap of EG ～ 7.8 eV, good thermal stability, high hardness and high melting point have made zirconium dioxide (ZrO2) an ideal candidate as the gate oxide for III-V materials [6-3,6-4]. However, unlike the stable interface between Si and silicon dioxide in a Si MOS structure, there is no high-quality insulator suitable for compound semiconductors. Consequently, for the deposition of insulator film on

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