Generally, the Scattering parameters, which referred to as S-parameters, are fundamental to microwave measurement. S-parameters are a way of specifying return loss and insertion loss. The relation of the microwave signals and s-parameters are defined as follows:
Microwave signals going into or coming out of the input port are labeled by a subscript 1. Signals going into or coming out of the input port are labeled by a subscript 2. The electric field of the microwave signal going into the component ports is designated a; that leaving the ports is designated b. Therefore,
a1 is the electric field of the microwave signal entering the component input.
b1 is the electric field of the microwave signal leaving the component input.
a2 is the electric field of the microwave signal entering the component output.
b2 is the electric field of the microwave signal leaving the component output.
By definition, then,
0
Consequently, s11 is the electric field leaving the input divided by the electric field entering the input, under the condition that no signal enters the output. Because b1 and a1 are electric fields, their ratio is a reflection coefficient. Similarly, s21 is the electric field leaving the output divided by the electric field entering the input, when no signal enters the output. Therefore, s21 is a transmission coefficient and is related to the insertion loss or the gain of the device. s22 is similar to s11, but looks in the other direction into the device.
3.5 Current gain cutoff frequency fT and maximum oscillation frequency fmax
The fT of a device is the frequency at which the short circuit current becomes unity. fT is defined as
From this relation, we could see that in order to achieve high fT, large gm and small total gate capacitance must be achieved. Small total gate capacitance is accomplished by short gate length; for millimeter-wave applications the gate length is usually smaller than 0.15µm. In this equation
G
the LG is the is the gate length; therefore, the shorter the gate length the higher the fT
and higher the gm. The intrinsic S parameters are used to determine the unity current-gain cut-off frequency (fT). It can be determined by extrapolation of the short-circuit current gain h21 = 0 dB. h21 can be defined as
Another important parameter is fmax, which is the frequency where the power gain falls to unity. fmax is expressed as
This expression shows that to obtain useful power gain at high frequency, the fT of a device must be large; in addition, the resistances of gate, source and drain must be small.
3.6 Device modelling technique
When defining the high frequency RF performance of the HEMTs, it is essential to de-embed all the conductors on the top surface of the wafer such as the pad, metal, and interconnect. Detailed layout of the device in this study is shown in Fig. 3-3. This helps us to understand what is going on at the active region of the device. A number of different semiconductor device models exist like small-signal, large-signal, and noise models.
In this paper, an approach that combines the conventional way and 3-D full wave electromagnetic analysis is proposed and extracted the intrinsic parameters of devices.
To accurately determine the equivalent circuit model, the overall structure is divided
into several blocks, including gate parasitic, drain parasitic, source parasitic and intrinsic part according to the scalability of the device size as shown in Fig. 3-4, where the parasitic elements should be kept at fixed values and not scalable with device size. The intrinsic block could further be divided into different equivalent circuit elements and shown in Fig. 3-5. Standard gradient optimization routine is used to minimize the error function value, which is defined as the difference between the modelled and measured S-parameters. Standard gradient optimization routine is used to minimize the error function value, which is defined as the difference between the modelled and measured S-parameters. In order to rigorously determine the parasitic elements, CST Microwave Studio which is based on finite integration algorithm in time domain (FIT) is applied to analyse the structure. It is observed from the filed plot that the two source buses are held at a lower potential referenced to the gate and source pads thus the E-filed lines tend to terminate at these buses indicating a strong capacitive parasitic (Fig. 3-6 a). To illustrate the difference, a similar structure without the two source buses is simulated and the electric filed at 10 GHz is plotted in Fig. 3-6 b, where a much coarser electric field distribution between the gate (drain) pad and source region is observed. Based on the EM analysis of the structure, the strong capacitive parasitic behavior between the gate (drain) pad and the source buses suggests two additional capacitors to be included in the equivalent circuit.
3.7 Noise figure
High-frequency noise relates with the device channel and capacitive coupling between the channel and the gate. The gate noise is represented by a gate-current noise generator ing2 and is caused by charge fluctuation in the channel, which in turn induces thefluctuation of compensating charge on the gate electrode. The channel
noise is represented by a drain-current noise generator ind2 and is caused by various physical mechanisms driven by the electric field in the channel. Another noise source is gate leakage. The noise performance of a FET may be quantified by the noise figure, NF, which is a function of frequency, FET bias voltages, and impedance matching.
NF can be well approximated by the semi-empirical equation given by Fukui [3-4] and is shown as the following equation:
NF = 1+ k (f/fT) [gm (Rg+Rs)]1/2,
= 1+ 2πkf (Cgs + Cgd) [gm (Rg+Rs)]1/2 , where k is a fitting parameter.
Generally, the reduction in Lg does not necessarily minimize the NFmin because Rg tends to increase due to a vertical resistance component of gate resistance, and also gm decreases due to a degraded gate drive so-called “short-channel effect”. Therefore, a reduction in Rg and suppression of the short-channel effect are necessary to minimize NFmin.
Fig. 3.1 Band diagrams at three different locations along the channel of a HEMT
Fig. 3.2 Actual characteristics and those predicted by Eq. (3-3) Eq. (3.4)
Fig. 3-3 Detailed layout of the device, the pads connecting the gate and drain are about 50×100um2.
Fig. 3-4 The block diagram with determined parasitic elements for the overall device structure.
GND IN
Intrinsic
Source Parasitic Gate
Parasitic
Drain Parasitic
Gate-Sourc e
Drain-Sourc e
Zo, Zo,
Transmission line to accommodate for possible phase shift caused by probe positioning variation
Fig. 3-5 Functional blocks of the equivalent circuit model, divided according the scalability with device size.
GND
IN OUT
Source Parasitic Gate
Parasitic
Gate-Source P iti
Drain-Source P iti
Zo, Zo,
Drain Parasitic
Fig. 3-6 Analyzed electric field plot of the 2x50um device at 10 GHz. (a) with the source buses of the device (b) without the source buses of the device
(a) (b)
Chapter 4
RF and Logic Performance Improvement of In
0.7Ga
0.3As /InAs/In
0.7Ga
0.3As Composite Channel HEMT Using Gate Sinking Technology
4.1 Introduction
For the advanced wireless communications, InP-based high electron mobility transistors (HEMTs) have attracted many attentions and demonstrated excellent high-frequency performance because of its superior electronic transport properties and high saturation velocity [4-1, 4-2]. Moreover, it is also a potential candidate FETs for low-power logic applications beyond Si CMOS technology in 22 nm node era [4-3,4-4]. InP HEMTs usually use In-rich InGaAs channel or InAs/InGaAs composite channel for good RF performance with large current drivability of the device.
Meanwhile, the gate-recess structure also plays a critical role in the high frequency performance for HEMT devices. In general, the transconductance (gm) of the device is mainly influenced by the gate-channel distance and the reduction of the distance can effectively increase the current gain cutoff frequency (fT) because of the enhancement of average electron velocity underneath the gate electrode.
Additionally, the shape of the recessed region not only affects the source and drain resistance (Rs and Rd) and the capacitances of gate-source and gate-drain (Cgs
and Cgd), but also modulates the electric field in the channel. K. Shinohara et al.
reported fT value of 547 GHz in 30-nm gate pseudomorphic HEMTs by means of
multilayer cap structure to reduce parasitic source and drain resistances [4-5]. H.
Matsuzaki et. al. have employed Tiered-Edge Ohmic structure and low-k benzocyclobutene (BCB) passivation to effectively minimize parasitic gate capacitance and achieve relatively high gm and fT values [4-6]. Although the results seemed rather promising, yet relatively complicated fabrication processes were involved in the reduction of the parasitic elements.
In this study, the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs were fabricated with Pt buried gate technology. The adoption of Pt buried gate is because Pt can diffuse into the barrier layer and the channel can be further recessed [4-7 – 4-9].
The diffused gate has lower parasitic capacitance and resistance as compared to that of the recessed gate. Additionally, the Pt has higher metal work function (5.65eV) than that of Titanium (4.1eV). The measurement results in this study clearly evidenced that superior device performance can be achieved through very simple and straightforward gate sinking fabrication process with optimal epi structure as compared to those proposed in [4-5] and [4-6].
4.2 Experiment
The HEMT structure was grown by molecular beam epitaxy on a 2-in diameter InP substrate. The schematic of the structure is shown in Fig.1 and given as follows, a 50-Å InAs channel layer with 20-Å In0.7Ga0.3As upper subchannel and 30-Å In0.7Ga0.3As lower subchannel were grown on top of the 500-nm-thick InAlAs buffer layer. The In0.7Ga0.3As sub-channels were applied to enhance the electron confinement in the thin InAs layer and improve the electron transport properties [4-10]. A 40-Å-thick InAlAs spacer, a Si-δ-doping with 5×1012 cm-2, a 10-nm-thick InAlAs barrier. A 4-nm-thick InP etching stop, and a 35-nm-thick InGaAs cap layer
with 2×1018 cm-3 Si-doping were grown on top of the composite channel layers.
For the device fabrication, the active area of the device was isolated by wet etch.
The ohmic contacts were formed with 3 µm source-drain spacing by evaporating Au/Ge/Ni/Au on heavily doped n-InGaAs cap layer and then alloyed at 250oC for 25 second to attain low contact resistance (Rc). For the T-shaped gate process, it was performed by the 50kV JEOL electron beam lithography system (JBX 6000 FS) with trilayer e-beam resist. Succinic acid/H2O2/NH4OH solution was used for gate recess and then Pt (12nm)/Ti (60nm)/Pt (80nm)/Au (180nm) were deposited as Schottky gate metal and lift off by ZDMAC to form 80-nm T-shaped gate. The insert SEM image is the unpassivated T-shaped gate formed after recess. A 100-nm thick silicon nitride was deposited as passivation layer by PECVD at 250oC for 10 min. Finally, thermal annealing at 250oC for 3 minutes in forming gas ambient was carried out for gate sinking to further recess the channel. The contact resistance was 0.032 Ω‧mm after gate sinking process, which remained almost unchanged as compared to that of 0.021 Ω‧mm before annealing.
4.3 Result and Discussion
Fig. 2 shows the DC I-V curve of the device with 2×50 µm gate width using gate sinking technology. The device exhibited very good pinch-off characteristic and the saturation current of 1418 mA/mm at VDS = 1V and Vgs = 0V as compared to the drain current of 1267 mA/mm for device before gate sinking showed in Fig. 3. This very high drain current density was mainly due to the superior electron mobility in the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel and the non-degrading performance of the ohmic contact during gate annealing. In addition, the gate sinking occurrence might cause the decrease of the drain current. In this studied, although the gate
sinking occurred, the drain current increased. The extracted values of source resistance Rs was 1.35 Ω for device without gate sinking compared to 1.22Ω for device with gate sinking. As a result, it is conclude that the reduction of parasitic resistance by the suppression of the formation of surface traps is the main reason for the performance enhancement of the device, because the increase in current is as high as 151 mA/mm [4-10]. As for the gate-drain breakdown voltage (VDG,BR), the value decreased from 3.6V for device without sinking (Fig. 4a) to 2.4V for that with sinking (Fig. 4b), which is mainly due to the reduction in the Schottky barrier thickness after gate sinking process.
The transconductance gm and the drain source current plotted as functions of Vgs
for devices without and with gate annealing are included in Fig. 5. As is observed from the figure, the peak gm value has increased from 1470 mS/mm for the device without gate sinking to 1590 mS/mm for that with gate sinking, both measured at VDS
= 0.5 V. This increase is mainly attributed to the sinking of Pt atoms into the InP etching stop layer which in turn shifted the gate metal front closer to the two-dimensional electron gas (2DEG) channel. Meanwhile, the threshold voltage shifted from -0.91 (without gate sinking) to -0.8 V (with gate sinking) when biased at VDS = 0.5V. The threshold voltage is defined as the Vgs when Ids reaches 1mA/mm.
A slight reduction in the gate leakage current from 1.66 × 10-6 A (without gate sinking) to 6.3 × 10-7A (with gate sinking) was also observed when biased at VDS = 0.8V and Vgs = 0V owing to the increase in the thickness of the amorphous layer under gate which diminished the leakage path because of the reduction of the grain boundaries [4-8], [4-11].
The S-parameters of the 2×50 µm device were measured from 5 to 80 GHz using on-wafer probing system with HP8510XF network analyzer. Fig. 6 and Fig. 7 show the frequency dependence of the current gain H21, the power gain MAG/MSG, and the
Mason’s unilateral gain U of the device with/without gate sinking measured at VDS = 0.8V and Vgs = -0.5V. The parasitic effects (mainly capacitive) due to the probing pads have been carefully removed from the measured S-parameters using the same method as in [4-12] and the equivalent circuit model in [4-13]. Since the geometry of the probing pads are relatively large compared to the device itself, the S-parameters of the open probing pads have been carefully characterized through full-wave electromagnetic simulations with measurement. Standard gradient optimization routine with tolerance level of delta S less than 0.01% were set as the convergence criterion during the fitting process. The capacitance at the gate-source end was extracted to be 10.2 fF and the capacitance at the gate-drain end was about 8.6 fF. The extracted gate resistance was about 4Ω. A very high current gain cut-off frequency fT
of 494 GHz and the maximum oscillation frequency fmax of 390 GHz were obtained for device with sinking as compared to that of fT = 390 GHz and fmax = 360 GHz for the device without sinking. This improvement in the RF performance was due to the increase of gm and the decrease of the gate-to-source capacitance (Cgs) in the applied gate bias range resulting from the gate sinking process. This decrease in Cgs was also evidenced from the measured S-parameters (even before the removal of parasitic elements) where a S11 contour with smaller “radius” with respect to the center of Smith Chart was observed as shown in Fig. 8, indicating a small capacitance value seen at the input port. Similar trend of reduction in (Cgs) values due to gate sinking process has also been observed in [4-14]. Table 4.1 summarizes the extracted intrinsic parameters for devices with and without gate sinking at same bias conditions. The increase in fT is mainly caused by the decrease of Cgs and increase of the transcondutance.
The noise performances for devices with/without gate sinking at drain voltage biases VDS = 0.3 V, and VDS = 0.1 V are shown in Fig. 4-9 and 4-10 with frequency
range from 1 GHz to 17 GHz at optimum bias conditions. The measured minimum noise figures (NFmin) at 17 GHz were 0.82 dB and 1.19 dB for devices with gate sinking and without gate sinking at VDS = 0.3 V, respectively. In addition, the corresponding associated gains (Ga) were 14 dB and 10 dB, respectively. The ultra-low dc power dissipation for gate sinking device (without gate sinking) is 1.14 (1.32) mW/mm, respectively. These results show great potential for ultra-low power high frequency LNA applications.
The effect of gate sinking on the gate delay performance of the HEMT device is also evaluated. To avoid erroneous and physically meaningless values of logic parameters in characterizing such non-optimized threshold voltage device, we have followed the method proposed in [4-15]. A sub-threshold slope of 115mV/dec and Drain Induced Barrier Lowering (DIBL) of 200mV/V after gate sinking were obtained. For device without gate sinking, the subthreshold slope and DIBL were 115 mV/dec and 178 mV/V, respectively. Fig. 10 shows the calculated intrinsic gate delay (CV/I) as function of ION/IOFF ratio for the device with and without gate sink and with various choices of the threshold voltage as defined in [4-16] at VDS = 0.6V. As is observed from the figure, a low calculated gate delay of 0.78 psec for gate-sinking device with ION/IOFF ratio maintained in the order of 103 was achieved as compared to that of 0.83 psec for the device without gate sink. The very low intrinsic gate delay performance is again attributed to the decrease in the Cgs after the gate sinking process.
These superior performances have also made such device a potential candidate for future high-speed and low-power logic applications.
4.4 Conclusion
In this paper, the use of the Pt buried gate technology for the enhancement of the
RF and logic performance of the HEMTs has been demonstrated. The HEMTs exhibit high Ids =1418mA/mm; high gm =1590 mS/mm, and a fT (fmax) of 494 GHz (390 GHz) after gate sinking. This is believed to be the highest value ever achieved for an 80 nm HEMT devices. In evaluating the devices for ultra-low DC power consumption LNA applications, the device exhibits the minimum noise figure at 17 GHz was 0.82 dB with corresponding associated gains 14 dB when biased at a VDS of 0.3 V.
Additionally, the logic performance of such device has also been characterized and a very low intrinsic gate delay (0.78 psec) with an ION/IOFF ratio in the excess of 103were obtained at VDS = 0.6 V. Overall, the performance improvement after gate sinking was mainly attributed to the increase of gm and the decrease in the corresponding capacitances of the device. The results demonstrate that superior HEMT device performance for high frequency, high-speed and low-power logic applications can be achieved through very simple gate sinking process with optimal epitaxy structure.
Fig. 4-1 The schematic view of the device structure and the insert SEM image is the 80-nm T-shaped gate after recess before silicon nitride passivation.
0.0 0.2 0.4 0.6 0.8 1.0 0
200 400 600 800 1000 1200 1400 1600
Device with gate sinking
Vg = -1 V Vg = -0.75 V Vg = -0.5 V Vg = -0.25 V Vg = 0 V
D rai n curr ent (m A /m m )
Drain-source Voltage, V
D(V)
Fig. 4-2 Drain-source current versus drain-source voltage curve for device with gate sinking.
0.0 0.2 0.4 0.6 0.8 1.0 0
300 600 900 1200 1500
Device without gate sinking Vg = 0 ~ -1V, step:-0.25V
D rai n current (m A/ m m )
Drain-source Voltage, V
D(V)
Fig. 4-3 Drain-source current versus drain-source voltage curve for device without gate sinking.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
InAs/In0.7Ga0.3As HEMTsGate-drain breakdown voltage (VBR)= 3.6 V Compliant IDG = 1 mA/mm
Gate-drain current I GD (mA/mm)
Gate-drain voltage V
GD(V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
G ate -d ra in c urr en t I
GD( mA /mm)
Gate-drain voltage V
GD(V)
Fig. 4-4 Two terminal gate-to-drain breakdown characteristics of device with/without gate sinking
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
D rai n-source current I
ds(m A /m m )
Gate-source Voltage, V
gs(V)
Transconduct ance g
m(m S/ m m )
before gate sinking After gate sinking at 2500C for 3 min
Fig. 4-5 Transconductance versus gate-source voltage before and after gate sinking at 250oC for 3 min.
1 10 100 1000 0
10 20 30 40
f
max= 390 GHz
f
T=494 GHz U
H
21MAG/MSG
Gai n ( dB)
Frequency (GHz)
L
g= 80 nm W
g= 2 x 50
µm V
D= 0.8 V V
G= -0.5 V
Fig. 4-6 Frequency dependence of the current gain H21, the power gain MAG/MSG, and the unilateral gain U of the InAs/In0.7Ga0.3As composite channel HEMTs. The frequency range was from 5 to 80 GHz, and the device was biased at Vds = 0.8V and Vgs = -0.5V.
1 10 100 1000 0
10 20 30 40 50
f
max=360 GHz f
T=390 GHz
InAs HEMTs Lg=80nm Wg=2X50 µm VD=0.8V Vg=-0.55V
MAG/MSG H
21U
Gai n ( dB )
Frequency (GHz)
Fig. 4-7 Typical current gain H21, MAG/MSG, and unilateral gain U as a function of
Fig. 4-7 Typical current gain H21, MAG/MSG, and unilateral gain U as a function of