The HEMT structure was grown by molecular beam epitaxy on a 2-in diameter InP substrate. The schematic of the structure is shown in Fig.1 and given as follows, a 50-Å InAs channel layer with 20-Å In0.7Ga0.3As upper subchannel and 30-Å In0.7Ga0.3As lower subchannel were grown on top of the 500-nm-thick InAlAs buffer layer. The In0.7Ga0.3As sub-channels were applied to enhance the electron confinement in the thin InAs layer and improve the electron transport properties [4-10]. A 40-Å-thick InAlAs spacer, a Si-δ-doping with 5×1012 cm-2, a 10-nm-thick InAlAs barrier. A 4-nm-thick InP etching stop, and a 35-nm-thick InGaAs cap layer
with 2×1018 cm-3 Si-doping were grown on top of the composite channel layers.
For the device fabrication, the active area of the device was isolated by wet etch.
The ohmic contacts were formed with 3 µm source-drain spacing by evaporating Au/Ge/Ni/Au on heavily doped n-InGaAs cap layer and then alloyed at 250oC for 25 second to attain low contact resistance (Rc). For the T-shaped gate process, it was performed by the 50kV JEOL electron beam lithography system (JBX 6000 FS) with trilayer e-beam resist. Succinic acid/H2O2/NH4OH solution was used for gate recess and then Pt (12nm)/Ti (60nm)/Pt (80nm)/Au (180nm) were deposited as Schottky gate metal and lift off by ZDMAC to form 80-nm T-shaped gate. The insert SEM image is the unpassivated T-shaped gate formed after recess. A 100-nm thick silicon nitride was deposited as passivation layer by PECVD at 250oC for 10 min. Finally, thermal annealing at 250oC for 3 minutes in forming gas ambient was carried out for gate sinking to further recess the channel. The contact resistance was 0.032 Ω‧mm after gate sinking process, which remained almost unchanged as compared to that of 0.021 Ω‧mm before annealing.
4.3 Result and Discussion
Fig. 2 shows the DC I-V curve of the device with 2×50 µm gate width using gate sinking technology. The device exhibited very good pinch-off characteristic and the saturation current of 1418 mA/mm at VDS = 1V and Vgs = 0V as compared to the drain current of 1267 mA/mm for device before gate sinking showed in Fig. 3. This very high drain current density was mainly due to the superior electron mobility in the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel and the non-degrading performance of the ohmic contact during gate annealing. In addition, the gate sinking occurrence might cause the decrease of the drain current. In this studied, although the gate
sinking occurred, the drain current increased. The extracted values of source resistance Rs was 1.35 Ω for device without gate sinking compared to 1.22Ω for device with gate sinking. As a result, it is conclude that the reduction of parasitic resistance by the suppression of the formation of surface traps is the main reason for the performance enhancement of the device, because the increase in current is as high as 151 mA/mm [4-10]. As for the gate-drain breakdown voltage (VDG,BR), the value decreased from 3.6V for device without sinking (Fig. 4a) to 2.4V for that with sinking (Fig. 4b), which is mainly due to the reduction in the Schottky barrier thickness after gate sinking process.
The transconductance gm and the drain source current plotted as functions of Vgs
for devices without and with gate annealing are included in Fig. 5. As is observed from the figure, the peak gm value has increased from 1470 mS/mm for the device without gate sinking to 1590 mS/mm for that with gate sinking, both measured at VDS
= 0.5 V. This increase is mainly attributed to the sinking of Pt atoms into the InP etching stop layer which in turn shifted the gate metal front closer to the two-dimensional electron gas (2DEG) channel. Meanwhile, the threshold voltage shifted from -0.91 (without gate sinking) to -0.8 V (with gate sinking) when biased at VDS = 0.5V. The threshold voltage is defined as the Vgs when Ids reaches 1mA/mm.
A slight reduction in the gate leakage current from 1.66 × 10-6 A (without gate sinking) to 6.3 × 10-7A (with gate sinking) was also observed when biased at VDS = 0.8V and Vgs = 0V owing to the increase in the thickness of the amorphous layer under gate which diminished the leakage path because of the reduction of the grain boundaries [4-8], [4-11].
The S-parameters of the 2×50 µm device were measured from 5 to 80 GHz using on-wafer probing system with HP8510XF network analyzer. Fig. 6 and Fig. 7 show the frequency dependence of the current gain H21, the power gain MAG/MSG, and the
Mason’s unilateral gain U of the device with/without gate sinking measured at VDS = 0.8V and Vgs = -0.5V. The parasitic effects (mainly capacitive) due to the probing pads have been carefully removed from the measured S-parameters using the same method as in [4-12] and the equivalent circuit model in [4-13]. Since the geometry of the probing pads are relatively large compared to the device itself, the S-parameters of the open probing pads have been carefully characterized through full-wave electromagnetic simulations with measurement. Standard gradient optimization routine with tolerance level of delta S less than 0.01% were set as the convergence criterion during the fitting process. The capacitance at the gate-source end was extracted to be 10.2 fF and the capacitance at the gate-drain end was about 8.6 fF. The extracted gate resistance was about 4Ω. A very high current gain cut-off frequency fT
of 494 GHz and the maximum oscillation frequency fmax of 390 GHz were obtained for device with sinking as compared to that of fT = 390 GHz and fmax = 360 GHz for the device without sinking. This improvement in the RF performance was due to the increase of gm and the decrease of the gate-to-source capacitance (Cgs) in the applied gate bias range resulting from the gate sinking process. This decrease in Cgs was also evidenced from the measured S-parameters (even before the removal of parasitic elements) where a S11 contour with smaller “radius” with respect to the center of Smith Chart was observed as shown in Fig. 8, indicating a small capacitance value seen at the input port. Similar trend of reduction in (Cgs) values due to gate sinking process has also been observed in [4-14]. Table 4.1 summarizes the extracted intrinsic parameters for devices with and without gate sinking at same bias conditions. The increase in fT is mainly caused by the decrease of Cgs and increase of the transcondutance.
The noise performances for devices with/without gate sinking at drain voltage biases VDS = 0.3 V, and VDS = 0.1 V are shown in Fig. 4-9 and 4-10 with frequency
range from 1 GHz to 17 GHz at optimum bias conditions. The measured minimum noise figures (NFmin) at 17 GHz were 0.82 dB and 1.19 dB for devices with gate sinking and without gate sinking at VDS = 0.3 V, respectively. In addition, the corresponding associated gains (Ga) were 14 dB and 10 dB, respectively. The ultra-low dc power dissipation for gate sinking device (without gate sinking) is 1.14 (1.32) mW/mm, respectively. These results show great potential for ultra-low power high frequency LNA applications.
The effect of gate sinking on the gate delay performance of the HEMT device is also evaluated. To avoid erroneous and physically meaningless values of logic parameters in characterizing such non-optimized threshold voltage device, we have followed the method proposed in [4-15]. A sub-threshold slope of 115mV/dec and Drain Induced Barrier Lowering (DIBL) of 200mV/V after gate sinking were obtained. For device without gate sinking, the subthreshold slope and DIBL were 115 mV/dec and 178 mV/V, respectively. Fig. 10 shows the calculated intrinsic gate delay (CV/I) as function of ION/IOFF ratio for the device with and without gate sink and with various choices of the threshold voltage as defined in [4-16] at VDS = 0.6V. As is observed from the figure, a low calculated gate delay of 0.78 psec for gate-sinking device with ION/IOFF ratio maintained in the order of 103 was achieved as compared to that of 0.83 psec for the device without gate sink. The very low intrinsic gate delay performance is again attributed to the decrease in the Cgs after the gate sinking process.
These superior performances have also made such device a potential candidate for future high-speed and low-power logic applications.
4.4 Conclusion
In this paper, the use of the Pt buried gate technology for the enhancement of the
RF and logic performance of the HEMTs has been demonstrated. The HEMTs exhibit high Ids =1418mA/mm; high gm =1590 mS/mm, and a fT (fmax) of 494 GHz (390 GHz) after gate sinking. This is believed to be the highest value ever achieved for an 80 nm HEMT devices. In evaluating the devices for ultra-low DC power consumption LNA applications, the device exhibits the minimum noise figure at 17 GHz was 0.82 dB with corresponding associated gains 14 dB when biased at a VDS of 0.3 V.
Additionally, the logic performance of such device has also been characterized and a very low intrinsic gate delay (0.78 psec) with an ION/IOFF ratio in the excess of 103were obtained at VDS = 0.6 V. Overall, the performance improvement after gate sinking was mainly attributed to the increase of gm and the decrease in the corresponding capacitances of the device. The results demonstrate that superior HEMT device performance for high frequency, high-speed and low-power logic applications can be achieved through very simple gate sinking process with optimal epitaxy structure.
Fig. 4-1 The schematic view of the device structure and the insert SEM image is the 80-nm T-shaped gate after recess before silicon nitride passivation.
0.0 0.2 0.4 0.6 0.8 1.0 0
200 400 600 800 1000 1200 1400 1600
Device with gate sinking
Vg = -1 V Vg = -0.75 V Vg = -0.5 V Vg = -0.25 V Vg = 0 V
D rai n curr ent (m A /m m )
Drain-source Voltage, V
D(V)
Fig. 4-2 Drain-source current versus drain-source voltage curve for device with gate sinking.
0.0 0.2 0.4 0.6 0.8 1.0 0
300 600 900 1200 1500
Device without gate sinking Vg = 0 ~ -1V, step:-0.25V
D rai n current (m A/ m m )
Drain-source Voltage, V
D(V)
Fig. 4-3 Drain-source current versus drain-source voltage curve for device without gate sinking.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
InAs/In0.7Ga0.3As HEMTsGate-drain breakdown voltage (VBR)= 3.6 V Compliant IDG = 1 mA/mm
Gate-drain current I GD (mA/mm)
Gate-drain voltage V
GD(V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
G ate -d ra in c urr en t I
GD( mA /mm)
Gate-drain voltage V
GD(V)
Fig. 4-4 Two terminal gate-to-drain breakdown characteristics of device with/without gate sinking
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
D rai n-source current I
ds(m A /m m )
Gate-source Voltage, V
gs(V)
Transconduct ance g
m(m S/ m m )
before gate sinking After gate sinking at 2500C for 3 min
Fig. 4-5 Transconductance versus gate-source voltage before and after gate sinking at 250oC for 3 min.
1 10 100 1000 0
10 20 30 40
f
max= 390 GHz
f
T=494 GHz U
H
21MAG/MSG
Gai n ( dB)
Frequency (GHz)
L
g= 80 nm W
g= 2 x 50
µm V
D= 0.8 V V
G= -0.5 V
Fig. 4-6 Frequency dependence of the current gain H21, the power gain MAG/MSG, and the unilateral gain U of the InAs/In0.7Ga0.3As composite channel HEMTs. The frequency range was from 5 to 80 GHz, and the device was biased at Vds = 0.8V and Vgs = -0.5V.
1 10 100 1000 0
10 20 30 40 50
f
max=360 GHz f
T=390 GHz
InAs HEMTs Lg=80nm Wg=2X50 µm VD=0.8V Vg=-0.55V
MAG/MSG H
21U
Gai n ( dB )
Frequency (GHz)
Fig. 4-7 Typical current gain H21, MAG/MSG, and unilateral gain U as a function of frequency of the 0.08 × 100 µm2 HEMTs before gate sinking.
Gate Sinking Non Gate Sinking
Gate Sinking Non Gate Sinking
Fig. 4-8 Measured S11 of devices with and without gate sinking under the same bias condition. Note that this bias condition gives the smallest intrinsic gate delay for the devices.
1 10
Fig. 4-9 Measured noise performance of the device at drain voltage VDS = 0.1V (a) device with gate sinking, Ids = 0.25 mA/mm (b) device without gate sinking, Ids = 0.34 mA/mm.
1 10
Fig. 4-10 Measured noise performance of the device at drain voltage VDS = 0.3V (a) device with gate sinking, Ids = 3.80 mA/mm (b) device without gate sinking, Ids = 2.52 mA/mm.
10
110
210
310
41
10
110
210
310
41
0.7 0.8
G ate d ela y ( pse c) 0.9
I
ON/I
OFFWith gate sinking
2
In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs VCC @ 0.6 V
Without gate sinking
Fig. 4-11 The calculated intrinsic gate delay as a function of ION/IOFF ratio with various choices of the threshold voltage for device with/without sink.
Table 4.1 Summary of the HEMT device parameters with and without gate sinking.
InAs/ In0.7Ga0.3As HEMTs Cgs Cgd Cds Gm (RF) fT (GHz) fmax (GHz) Without gate sinking 73.3 fF 16.3 fF 5.3fF 201mS 390 GHz 360 GHz Gate sinking 60.5 fF 16.6 fF 3.7fF 208mS 494 GHz 390 GHz
Chapter 5
InAs-Channel Based Quantum Well Transistors for High-Speed and Low-Voltage Digital Applications
5.1 Introduction
For device scaling in Si technology, the physical gate length of Si transistors used in the current 65 nm generation node is about 30 nm and the size of the transistor will reach 10 nm in 2011. The International Technology Roadmap of Semiconductors Winter Public Conference 2007 (ITRS 2007) also forecasted integration of planar III-V compound semiconductor FETs with Si technology is one of the promising solutions for the CMOS technology to extend Moore’s law well into the next decade [5-1] – [5-5]. Generally, III-V materials have about 50 to 100 times higher electron mobility than Si and the resulting III-V-based transistors are showing very attractive merits over scaled Si MOSFETs. The extremely high transconductance and excellent RF performance have been demonstrated recently by InAlAs/InGaAs MHEMTs on GaAs substrate or InP substrate with ultra short gate length [5-6,5-7].
Low DC power consumption is always a highly desired property for practical system applications. However, maintaining device performance with low drain bias can only be achieved through optimized device technology which also plays a critical role for high-speed low-power digital applications. Having the properties of electron mobility as high as 20,000 cm2/Vs at room temperature, higher electron peak velocity, low electron effective mass and a reasonable energy bandgap (0.36 eV), InAs
materials have attracted numerous attentions as channel layer of Quantum Well FETs (QWFETs) for future high-speed and low-power digital applications [5-8].
In this letter, nano scale In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel QWFETs were fabricated and evaluated for high-speed and low-power digital applications. The devices demonstrated excellent DC, RF, and logic performances, indicating the suitability for ultra-high speed and low power digital applications.
5.2 Experimental
The epitaxial layer structure of the InAs-channel QWFETs was grown by molecular beam epitaxy (MBE) on 2-in InP substrate. Fig. 5-1 shows the detailed epitaxial structure of the 80 nm InAs-channel QWFETs in this study. The In0.7Ga0.3As sub-channels were applied to enhance the electron confinement in the thin InAs layer and improve the electron transport properties [5-8]. An InP layer could provide a good gate etching stop layer as well as a good surface passivation of InAlAs layer to avoid kink effect and reduce the hot-electron surface damage [5-9]. Besides, with the use of the InP etching stop layer, the lateral recess length (Lr) can be easily controlled and RF performance can be improved [5-10,5-11]. The room temperature 2DEG density and electron mobility measured were 4.34×1012 /cm2 and 12,000 cm2/Vs, respectively.
For the device fabrication, mesa isolation was done by a phosphoric based solution first. The device was etched to the buffer layer in order to attain a good isolation. After rapid thermal annealing of ohmic metal (Au/Ge/Ni/Au) in forming gas ambient, low ohmic contact resistance (RC) and sheet resistance were achieved and measured by transmission line method. The values were 0.02 Ω‧mm and 37.4Ω/□, respectively. A conventional tri-layer resist system of ZEP-520/PMGI/ZEP520 was used for the T-shaped gate fabrication by E-Beam lithography with double exposure
and double development. The recess etching was performed carefully using pH-adjusted solution of succinic acid (S.A.) and H2O2 mixture to selectively etch heavily doped cap layer over InP layer. After gate metal deposition, the T-shaped gate was formed by lift-off technique. The gate length of the T-shaped gate was 80nm with 2µm source-to-drain spacing achieved. Finally, a 100-nm thick silicon nitride was deposited as passivation layer by PECVD at 250 oC for 10 min. Special attention must be paid during the heat treatment process to avoid the degradation of the contact resistance values since these values are critical for high-speed low-power digital applications.
5.3 Results and Discussion
Fig. 5-2 shows the measured current-voltage characteristics of a 0.08 × 40 µm2 device. As observed from the figure, this device can be well pinched off with a threshold voltage (VT) of -0.81 V and the maximum drain-source current of 1015 mA/mm at VDS = 0.5 V and Vgs = 0V. The threshold voltage is defined as the Vgs when Ids reaches 1mA/mm. This very high drain current density was mainly due to the superior electron mobility in the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel and the very low ohmic contact resistance. The transconductance gm and the drain source current versus Vgs with various VDS are shown in Fig. 5-3. The maximum gm peak of the device at a VDS of 0.5 V was 1900 mS/mm. The extremely high transconductance was due to higher carrier concentration and superior electron transport properties in the InAs channel. Compared with InxGa1-xAs QWFETs, the In0.52Ga0.48As QWFETs shows a transconductance of 823 mS/mm at VDS = 1.5 V and is shown in Fig 5-4. On the other hand, the transconductance of In0.7Ga0.3As QWFETs is 1050 mS/mm at VDS
= 1.5 V showing in Fig 5-5. The results clearly indicated that the InAs-channel
QWFETs can be biased at a low supply voltage to reduce overall dc power consumption, while maintaining relatively high current density and transconductance.
The two terminal gate-to-drain breakdown voltage (BVGD) was measured to be -2.5 V, defined at IGD = -1mA/mm.
The S-parameter of the device was measured using Cascade MicrotechTM on-wafer probing system with HP8510XF vector network analyzer from 5 to 80 GHz.
A standard Load-Reflection-Reflection-Match (LRRM) calibration method was used to calibrate the measurement system and the calibrated reference planes were at the tips of the corresponding probes. The parasitic effects (mainly capacitive) from the probing pads have been carefully removed from the measured S-parameters using the same method as in 12 and the equivalent circuit model in 13. Since the geometry of the probing pads are relatively large compared to the device itself, the S-parameters of the open probing pads have also been rigorously characterized through full-wave electromagnetic simulations with measurement. The capacitance at the gate-source end and gate-drain end were extracted to be 13.9 fF and 10.3 fF, respectively. Before RF measurements, we must find the optimum DC bias to obtain the maximum current gain and power gain. Fig. 5-6 shows the Ids and VDS dependence of fT curves. From the figure, InAs device could exhibits exceeding 360 GHz at VDS = 0.5 V at the range of 200 mA/mm to 500 mA/mm. The current gain cutoff frequency (fT) and maximum available (stable) gain (MAG/MSG) as a function of frequency are plotted in Fig. 5-7.
The extracted current gain cut-off frequency fT and maximum oscillation frequency fmax are 393 GHz and 260 GHz at drain bias of 0.5 V, respectively, by extrapolating H21 and MAG/MSG with a -20 dB/decade slope. Apparently, the excellent fT is owing to the extremely high transconductance value. Moreover, the dc power dissipation was 5.8 mW when the device was biased at peak fT and fmax.
Care must be taken while biasing devices with such narrow energy bandgap values
since the occurrence of impact ionization will certainly degrade the performance of devices. Fig. 5-8 (a) shows the measured H21 at 80 GHz as a function of drain voltages for InAs/In0.7Ga0.3As channel HEMTs. It is obvious that H21 has the highest gain at drain voltage 0.8 V and decreases when the bias voltage increases. The main reason is that the impact ionization occurred at VDS = 0.8 V and the generated electrons failed to keep up with the electronic field modulation at RF frequency, causing a drop in RF gain even at higher drain voltages. The gate current plotted as a function of gate voltage at different drain bias is shown in Fig. 5-8 (b). The dramatic increase in gate leakage current further evidenced the occurrence of impact ionization for biases higher than 0.8. This is because some holes produced during gate voltage increase transferred over the barrier to the gate region due to the impact ionization phenomenon.
The procedure as proposed by R. Chau, et. al [5-1] was adopted for the evaluation of digital performance of such non-optimized VT device to avoid possible erroneous and physically meaningless values of logic parameters. The on-state (off-state) current was defined as the Ids corresponding to a Vgs 2/3 (1/3) of the difference between the drain bias and the threshold voltage. Fig. 5-9 shows the
The procedure as proposed by R. Chau, et. al [5-1] was adopted for the evaluation of digital performance of such non-optimized VT device to avoid possible erroneous and physically meaningless values of logic parameters. The on-state (off-state) current was defined as the Ids corresponding to a Vgs 2/3 (1/3) of the difference between the drain bias and the threshold voltage. Fig. 5-9 shows the