Chapter 4 Conclusion and Future Works
4.1 Conclusion
In this study, by taking advantage of HC-TFTs to analyze the subthreshohld characteristics of poly-Si TFTs fabricated with MILC scheme, the impacts of the location-dependent film crystallinity of the poly-Si films on device characteristics are carefully studied. Moreover, since this unique test structure is also suitable for spatially resolving the location-dependent damage induced by hot carrier stress, the HC-TFTs have also been successfully used in this study to investigate the local change in internal devices during operation.
Our results show that the MILC devices depict superior device characteristics except for the increased leakage current arisen from metal contamination. We also found that the MILC device characteristics are closely related to the distance of its channel layer to the seeding window. We have proven that the ASW shows superior device characteristics if the channel length is short enough so that the SPC mechanism is not triggered. The inferior subthreshohld characteristics in short-channel SSW devices are due to the defect-rich region in the center of the channel. However, in long-channel devices, the occurrence of SPC granular structure in ASW devices will mitigate the merits of MILC process so the device characteristics become similar to the long-channel SSW devices. Finally, the impacts of defect-rich region and SPC granular structure on device characteristics with various channel length are also analyzed with the help of HC-TFTs, and the results are confirmed by SEM pictures.
26
The hot carrier effects under various stress gate bias and stress drain bias have been studied in Chapter 3. In sum, a larger positive Vth shift and more serious degradation in SS are resulted as the voltage difference between drain and gate (i.e., VD-VG) is increased, arising from the increase of electron injection in the gate oxide as well as the generation of defects in the channel or at the oxide/channel interface.
For the condition with VG = 0 V, VD = -20 V, a portion of the electrons generated by BTB tunneling would inject into gate oxide by FN tunneling and then get trapped in the oxide.
The difference of hot carrier effects between SPC and MILC devices was also investigated by HCTFTs. Due to the improved mobility of conduction carriers in MILC devices, the conduction carriers under hot carrier stress are more likely to accumulate their kinetic energy. As a result, the probability of surmounting the energy barrier height (3.1 eV) at the oxide/channel interface is higher in the MILC samples under the same stress condition as compared with the SPC ones, and more electrons will get trapped during stressing, rendering a larger Vth shift. On the other hand, SPC poly-Si films are relatively fine granular structure in nature as compared with the MILC ones. The larger number of weak bonds in its channel could be easily struck and broken by energetic carriers during stressing and lead to the generation of additional defects. As a result, degradation of SS and on-current is worse in the SPC samples.
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4.2 Suggested Future Work
Although the effects of ASW and SSW on the MILC devices were already investigated in this study, however, the seeding window size and the channel thickness will also affect the film crystallinity but details about the effects remain unclear. To further improve device performance, these effects should be addressed in the future.
The hot carrier stress under the operation of AC mode (i.e., dynamic) is more complex than DC mode, and it is also worthy to study and understand the difference in this regard between the MILC and SPC devices under AC stress. On the other hand, the negative bias temperature instability (NBTI) is another serious reliability issue for p-channel TFTs [37]. The mixed effect of NBTI and hot-carrier effect should be distinguished and evaluated. HC-TFTs should be a viable vehicle for addressing this issue.
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33
Figure 1. The formation process for MILC [17].
34
Figure 2-1. MILC process of -Si with Ni as the seed.
(a) (b)
Figure 2-2. (a) Symmetrical and (b) asymmetrical seeding window arrangements.
35
Figure 2-3. Cross-sectional view of poly-TFT device
(a)
36
(b)
(c)
Figure 2-4. SEM top view of a MILC sample. Enlarged views of the sample showing (b) the interface of MIC/MILC and (c) intersection of SPC/MILC.
MILC
37
Figure 2-5. Top view of HC-TFT device and the various dimension parameters are displayed in table 2-1.
Figure 2-6. Test transistor (TT) and (b) monitor transistors (MTs) (the darker parts) embedded in a HC-TFT.
38
(a) (b)
Figure 2-7. HC-TFT test structures with (a) asymmetric seeding window (ASW) and (b) symmetric seeding window (SSW).
B1-TT L/W=10/5 m
Gate Voltage (V)
-12 -10 -8 -6 -4 -2 0 2 4 6
Drain Current (A)
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
MILC SPC
V= -0.1 V V= -3 V
Figure 2-8. Comparisons of transfer characteristics between SPC and MILC devices and the performance parameter are summarized in table 2-2.
39
40
41
(c)
Figure 2-10. Typical transfer characteristics of ASW and SSW devices with channel length of (a) 0.6, (b) 2, and (c) 10 μm.
L/ W = 10 / 20 m ASW : Vth = - 2.57 V SS = 373 mV/dec.
SSW: Vth = - 2.60 V SS= 389 mV/dec.
VG (V)
-12 -10 -8 -6 -4 -2 0 2 4 6
I D
(A)
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
ASW SSW
V= -0.1 V V= -3 V
42 subthreshold swing (SS) of ASW and SSW devices.
43
Figure 2-12. SEM picture for the region of DMT in an HC-TFT with ASW. (B1 type with structural parameters listed in Table 2-1)
Figure 2-13. SEM picture for the region of CMT in an HC-TFT with ASW (B1 type).
Channel length of this device is 10m, and the region is about 10~11
m away from the seeding window.
44
Figure 2-14. SEM picture for the region of SMT in an HC-TFT with ASW (B1 type).
Channel length of this device is 10m, and the region is about 14~15
m away from the seeding window.
B1
Gate Voltage (V)
-12 -10 -8 -6 -4 -2 0 2 4 6
Drain Current (A/m)
10-17 10-16 10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
SMT CMT DMT
ASW
Figure 2-15. Transfer characteristics of SMT, CMT and DMT in an HC-TFT with ASW (B1 type).
45
Figure 2-16. Defect-rich region formed in the SSW device (conventional device).
Channel length of this device is 10m, and the region is at the central of channel.
Gate Voltage (V)
-12 -10 -8 -6 -4 -2 0 2 4 6
Drain Current (A/m)
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4
DMT SMT CMT
SSW
B1
Figure 2-17. Transfer characteristics of SMT, CMT and DMT in an HC-TFT device with SSW (B1 type).
Defect rich region
46
(a)
(b)
Figure 2-18. SEM pictures of the poly-Si channel in the middle region of CMT in an HC-TFT with SSW (B1 type). The magnification ratio is (a) 50k X and (b) 60k X.
Tip of MILC
47
Figure 2-19. Top view of a cross type TFT device containing a test transistor (TT, along the horizontal direction) and a monitor transistor (MT, along the vertical direction).
AB3
Gate Voltage (V)
-12 -10 -8 -6 -4 -2 0 2 4 6
Drain Current (A/m)
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
TT MT
Figure 2-20. Typical transfer characteristics of TT and MT for AB3 device and the extracted parameters are displayed in table 2-3.
48
Figure 3-1. Schematic illustration for the creation of defects in the p-channel device under hot carriers stress.
49
Figure 3-2. The I-V curves before and after stress measured under (a) forward mode, and (b) reverse mode. The stress was applied with VG = Vth-3 V, VD= -15 V.
50
(a)
(b)
Figure 3-3. Schematic illustration for (a) BTBT occurring at drain side and (b) suppression of the BTBT after stress by charges trapped in the oxide.
51
Figure 3-4. The I-V curves before and after stress measured under (a) forward mode and (b) reverse mode. The stress was applied with VG = Vth-5 V, VD= -15 V.
52
53
54
B2, Stress drain bias : -15 V Time : 1000s
Stress Gate Voltage
-12 -10
-8 -6
-4 -2
Delta Vth
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
DMT TT SMT CMT
Figure 3-7. Threshold voltage shift under the stress condition of VD = -15 V and various gate bias for 1000 s.
55
56 Stress gate bias : Vth-3 V B2
Figure 3-9. (a) Shift of threshold voltage and (b) subthreshold swing as a function of stress drain bias under the stress condition of VG = Vth – 3 V for 1000s.
57 Stress condiotion:
Gtae bias = Vth-3 V Drain bias = -20 V Time : 1000s
Gate Overdrive (VG - Vth) (V)
-12 -10 -8 -6 -4 -2 0 2 4 6
58
59
Figure 3-11. Degradation of (a) on-current and (b) subthreshold swing, and (c) shift of threshold voltage under the stress condition of VD = -20 V and various gate bias for 1000 sec.
Figure 3-12. Transfer characteristics of the TT with various applied drain bias.
B2, TT
60
Figure 3-13. Schematic illustration for band diagrams at VG = 0 V and VD= -20 V along (a) vertical direction (located in the drain/gate overlap region of the TT) and along (b) channel direction, respectively, in which the BTB tunneling and FN tunneling processes are described.
61
0 200 400 600 800 1000 1200 1400 1600
Delta Vth (V)
0 200 400 600 800 1000 1200 1400 1600
Delta Ion (%)
62
B2, Stress condition : VG = -5.5 V, VD = -20 V
Time (s)
0 200 400 600 800 1000 1200 1400 1600
Delta SS (mV/dec.) subthreshold swing as a function of stress time. The stress condition is VG
= Vth – 3 V and VD = -20 V.
Figure 3-15. Subthreshold characteristics of DMT before and after DC stress at VG = Vth-3 V and VD= -20 V for various time.
63
Figure 3-16. Subthreshold characteristics for an SPC test transistor before and after stress measured under (a) forward mode and (b) reverse mode under stress condition of VG = Vth-3 V and VD= -20 V for 1000 sec. [35].
64
65
Figure 3-18. (a) Shift of threshold voltage, and (b) on-current degradation as a function of stress drain bias for SPC devices under the stress condition of VG = Vth – 3 V [35].
66
Figure 3-19. Schematic illustration for energy distribution of channel carriers in MILC and SPC devices under the same hot carrier stress condition.
67
68
Vita
姓名：林庭輔 性別：男
出生：西元 1986 年 01 月 19 日 出生地：台灣
學歷：國立交通大學電子工程研究所 2008 年 9 月 ~ 2010 年 7 月 國立交通大學材料與科學系 2004 年 9 月 ~ 2008 年 6 月 明道高級中學
2001 年 9 月 ~ 2004 年 6 月 論文題目：
金屬誘發側向結晶複晶矽 P 型多晶矽薄膜電晶體的元件特性及熱載子效應研究 A Study on Device Characteristics and Hot-Carrier Effects of P-Channel Metal-Induced-Lateral Crystallized Poly-Si Thin-Film Transistors