Thesis Organization

There are four chapters in the thesis. In Chapter 1, the application of LTPS TFTs, three kinds of LTPS preparation techniques, and the associated reliability issues are briefly introduced. In the next chapter, we describe the novel test structure, its fabrication process, and its capability in resolving the location-dependent device characteristics before and after the hot-carrier tests.

In Chapter 3, results of the reliability characterization under DC (static) stress condition are presented and analyzed by using the novel test structure. Major focus is to pinpoint the location where major damage region is induced and identifies its degradation mechanism. A comparison and discussion of the degradation mechanisms between SPC and MILC devices are also given. Finally, we summarize the conclusion and suggest future work in Chapter 4.

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Chapter 2

Fabrication and Electrical Characteristics of MILC Devices

2.1 Device Fabrication and Operating Principle of HC-TFTs

First, six-in. silicon wafers covered with 100nm-thick thermal oxide were used as the starting substrates, followed by deposition of a 100nm-thick α -Si film with low-pressure chemical vapor deposition (LPCVD) at 550 ℃. Then, a 100nm-thick low temperature oxide deposited by plasma enhanced chemical vapor deposition (PECVD) was used as a block layer. After formation of the seeding windows, a thin 5nm Ni layer was deposited by E-gun, followed by 540 ℃ thermal annealing in furnace for the purpose of MILC crystallization, as shown in Fig. 2-1. In this thesis, two splits of seeding window arrangement were exploited, as shown in Fig. 2-2. In one split, the window was opened only at the drain region, denoted as Asymmetric Seeding Window (ASW), while the other one has the windows opened at both source and drain regions, denoted as Symmetric Seeding Window (SSW).

After finishing MILC process, we removed the Ni layer and block oxide by wet etching steps. Then a 30nm-thick PECVD oxide for gate dielectric and a 150nm-thick LPCVD poly-Si gate material were deposited. Next, after accomplishing gate patterning and exposure of the source and drain regions, the source, drain, and gate regions were doped by self-aligned BF₂⁺ implantation at a

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dose of 5×10¹⁵ /cm² and energy of 50 keV. Dopant activation was performed at 600

℃ for 12 hours by furnace, and then a PECVD oxide layer of 200 nm was deposited and used as the passivation layer to prevent the penetration of humidity and impurity.

Finally, contact-hole patterning and metallization steps were performed, followed by a sintering treatment at 400 ^oC for 30 min. Figure 2-3 shows the final cross-section of TFT devices. The SPC device fabrication is similar to MILC device except the crystallization of the active layer: the SPC split skipped the Ni seed deposition and transformed the Si channel layer from α-Si to poly-Si by a thermal treatment done at 600 ℃ for 24 hours in furnace.

One test wafer was used to analyze the granular texture after MILC process. Prior to taking the SEM pictures, the specimens were soaked in Secco etch for 25 seconds.

Some of the results are shown in Figs. 2-4 (a) ~ (b). In Fig.2-4(a), upper left corner shows MIC grains, right lower corner shows SPC grains, and in between is the MILC region which contains needle-like grains. Enlarged views of the regions close to the MIC/MILC and MILC/SPC interfaces are shown in Figs. 2-4(b) and 2-4(c), respectively.

In this thesis, two kinds of devices were characterized for better understanding of the impacts of MILC process on device performance. In addition to the conventional layout schemes shown in Fig. 2-2 which are used for measuring basic characteristics and investigating the effects of channel length, width, as well as the arrangement of the seeding windows, the other type is termed HC-TFT with the layout scheme shown in Fig. 2-5, which is configured with four pairs of p

+

electrodes at the edges of the channel. Major dimensional parameters are listed in Table 2-1. Roles of each components embedded in the test structure can be clearly understood with the help of Figs. 2-6(a) and 2-6(b). In the x- (i.e., horizontal) direction of Fig. 2-6(a), one pair of

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p⁺ regions located at the two edge sides of lateral channel in the HC-TFT is called the

“test transistor” (TT), which imitates the channel of a conventional device. The other three pairs paralleled in the y-(i.e., vertical) direction construct three transistors called

“monitor transistors” (MT), as shown in Fig. 2-6(b), which are capable of analyzing the asymmetrical and location-dependent degradation along the channel of test transistor (TT) caused by the MILC process and the HC stress testing. As can be seen in the figures, the TT and MTs share a common gate electrode lying over the entire channel. Therefore, the localized change along the test transistors, caused by structural issue of needle-like MILC grains in the channel or damage under bias stress, can be characterized by probing the current-voltage (I-V) characteristics of the corresponding MT. In Fig. 2-6(b), according to their position relative to the channel of the test structure, the three MTs are denoted as SMT (i.e., source-side MT), CMT (i.e., central MT), and DMT (i.e., drain-side MT). As aforementioned, the ASW and SSW splits for location of seeding windows are also established in HC-TFTs, as shown in Fig. 2-7(a) and Fig. 2-7(b), respectively.

2.2 Measurement Setup

The subthreshold and output characteristics were measured by a Keithley 4200 semiconductor characterization system with Keithley Interactive Test Environment (KITE) software. During the process of measurement, temperature- regulated hot chuck was maintained at 30 ℃.

The major electrical parameters of devices can be extracted from the measurement of I-V curves. The threshold voltage, denoted as “V_th”,is defined as the value of VG when ID equals 10nA × under VD of 0.1V, where W and L are channel

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width and channel length, respectively. The subthreshold swing, denoted as “SS”, is calculated by the following equation:

SS = . (Eq. 2-1) Moreover, the change of threshold voltage (Δ Vth) and subthreshold swing (Δ SS) after bias stressing are calculated by the equations:

Δ Vth = Vth,stress - Vth,fresh,

Δ SS = SSstress - SSfresh, (Eq. 2-2) where the notation “fresh” and “stress” refer to the conditions before and after stressing, respectively. The on-current (I_on) is defined as the value I_D at V_G = -10V.

After stressing, the deviation of on-current is formulated by (ΔIon / Ifresh) × 100%.

Similarly, ΔIon = Ion,stress – Ion,fresh, where Ion,stress is defined as the value at VG= -10+Δ Vth. Finally, the field-effect mobility (μFE) is estimated by gm,max, which is described by the following equations.

gm = , μ_FE =

(Eq.2-3) where C_ox is the capacitor of gate insulator.

2.3 Basic Electrical Characteristics

It is well known that the active layer prepared by MILC process takes advantage of needle-like grains directing across the channel from drain to the source, and the reduction in the quantity of trapped centers improves the carrier mobility as well as the device performance [29]. Fig. 2-8 shows the ID-VG curve for MILC and SPC devices; it is worthy to note that the MILC device shows greatly improved

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characteristics in terms of higher carrier mobility, lower Vth and SS as compared with the SPC one. The extracted performance parameters are summarized in Table 2-2.

According to the results, it is illustrated that a smaller grain size (in average) and absence of directional arrangement of grains along the channel degrade the performance of SPC devices [30].

It seems that MILC devices have better electrical characteristics than the SPC one. However, one disadvantage in application is the enhancement of leakage current arisen from metal contamination. This condition can be understood in Fig. 2-9(a) by comparing the difference in off-state I_D between forward and reverse modes. Here the

“forward mode” denotes the case when the drain bias is applied to the heavily doping region where seeding window is located while the other electrode without seeding window is grounded and serves as the source. For “reverse mode” of operation, the above arrangement is simply interchanged. The leakage current is obviously higher under forward mode in the ASW device, as shown in Fig. 2-9(a). However, such difference is unobserved for the SSW device, whose leakage current is consistent between the two modes, as shown in Fig. 2-9(b). Note the leakage levels in the present case are high and comparable to that of the forward mode exhibited in the ASW device (Fig. 2-9(a)). These high leakage levels can be attributed to the existence of nickel-rich phases near the junction region. The contamination tends to induce additional defect levels inside the channel layer which are responsible for the increased leakage current. These defects act as generation centers and enhance the leakage at low V_D via trap-assisted thermal generation process, and the leakage at high VD via trap-assisted field emission [31] [32]. As a result, the issue of metal contamination in MILC device must be considered to prevent the undesirable increase of leakage current. In this thesis, the offset region between gate edge and seeding

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window is set at 5

m. As compared with self-aligned seeding arrangement, such

offset can help reduce the number of nickel at the junction of drain [31].

2.4 Effects of Channel Length and Seeding Window Configuration

As mentioned above, the film crystallinity of a MILC film is location-dependent and related to distance from the seeding window as well as the seeding window arrangement. Certainly such property will draw impacts on device performance and worth investigation.

Figures 2-10(a), (b), and (c) show typical transfer curves of SSW and ASW devices with channel length at 0.6, 2, and 10 μ m, respectively. Threshold voltage (Vth) and subthreshold swing (SS) of the two types of device as a function of channel length (L) are shown in Figs. 2-11(a) and (b), respectively. In Fig. 2-11(a), the ASW devices show Vth roll-off phenomenon, seeming to indicate the occurrence of short-channel effect. However, the SS shown in Fig. 2-11(b) improves with decreasing channel length, indicating that better film crystallinity in shorter-channel devices also accounts for the Vth reduction as compared with long-channel ones. On the other hand, the SSW devices generally exhibit worse performance in terms of higher Vth (absolute value) and SS than ASW ones at the same Length. Interestingly, the difference between the two types of devices is most significant at L of 2 and 5 m, and diminishes as L either decreases or increases.

From the above, it is seen that devices with shorter channel have superior Vth and SS to long channel ones. Such outcome is believed to arise from the variation in film crystallinity across the channel. To confirm this we performed SEM analysis on a B1 HC-TFTs (see Table 2-1) with ASW to check the film crystallinity in different regions

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of the channel. Excellent crystalline quality can only be observed in the DMT region which is most close to the MIC area, as shown in Fig.2-12. In this picture the surface looks quite flat that the grain boundaries are hardly resolved. In the range of CMT, the appearance of needle-like grains can be observed in Fig. 2-13, where the grain size is obviously smaller than that in the DMT region. Finally, at the source side, as shown in Fig. 2-14, it is apparent that the grains already become smaller and discrete, a feature associated with the occurrence of the SPC process [32].

The differences in film crystallinity actually reflect on the electrical characteristics of the monitor transistors, as shown in the Fig. 2-15. It is clear that the best performance among three monitor transistors is DMT and the worst one is SMT, confirming the difference in film quality examined with the SEM technique.

In Fig. 2-11, it is observed that the V_th and SS for the SSW devices are inferior to the ASW ones. This is believed to be related to the intersection of the two MILC fronts growing from the two seeding windows located at source and drain regions.

One SEM evidence is given in Fig. 2-16. This picture was taken from an SSW device and a defect-rich region is clearly observed in the middle of the channel. The abundance of defects acting as trap centers will degrade device characteristics [33].

Such defect-rich region draws different impact on devices with various channel length, as shown in Fig. 2-11(b) where the SS for SSW improves with decreasing length. This is mainly attributed to the improved crystallinity as the channel region gets closer to the seeding windows as analyzed in the ASW case. On the other hand, as L is increased from 5 to 10

m, the SSW devices characterized in Figs. 2-11(a) and (b)

show slightly decreased Vth and SS and reduce the difference with the ASW ones. As have been shown in Fig. 14, SPC granular structure is predominant at the central part of the channel for such long-channel devices. This would dilute the impact of the

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aforementioned defect-rich region on the device performance and explain why the difference between the ASW and SSW devices diminishes.

The above inference can be verified from the I-V curves of MTs embedded in an SSW HC-TFT shown in Fig. 2-17 and SEM pictures in Fig. 2-18. The measured results in Fig. 2-17, which has been normalized to the channel width, clarify the much superior performance in DMT and SMT to that of CMT. Figure 2-18(a) shows obvious jagged granular structure resulted in the middle of a CMT due to the confrontation of the two MILC fronts, and it signifies that many grain boundaries have been formed in the neighborhood of jagged structure. An enlarged view illustrated in Fig. 2-18(b) displays that there are many defects and sprawl grains near the jagged structure. Existence of such defect-rich region certainly impacts the device characteristics.

It is also worthy to know the impacts of granular structure of the poly-Si films on device characteristics, such as the lying orientation of needle-like grains as well as the location-dependent film crystallinity, are probed by a special test device shown in Fig.

2-19. In the device, in addition to the TT, an MT is also embedded with its source-to-drain direction vertical to the TT. Typical transfer characteristics are shown in Fig. 2-20, in which the drain current has been normalized to the channel width. It can be observed that the on-current of the TT is higher than that of the MT. The extracted parameters are summarized in Table 2-3. It can be seen that TT exhibits higher on-current and field-effect mobility than the MT. This is primarily attributed to the reduced number of grain boundaries counted from source to drain in the TT than that in the MT, owing to the needle-like grains originating from the seeding window [34].

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Table 2-1. Dimensions of two types of HC-TFT testers.

Table 2-2. Performance parameters extracted from Fig. 2-8.

Table 2-3. Major parameters extracted from Fig. 2-19.

(V) (mV/dec.) (cm²/Vs)

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Chapter 3

Hot Carrier Degradation under Static Stress

In order to study the degradation induced in MILC devices due to hot-carrier effects, various static stress conditions were executed on the HC-TFTs. The change in the characteristics of test transistor and monitor transistors were recorded and analyzed. The difference between MILC and SPC devices were resolved by taking advantage of HC-TFTs.

3.1 Hot Carrier Stress under Mild Stress Bias

Mechanisms of hot-carrier degradation in p-channel MILC devices are similar to other types of poly-Si TFTs with the schematic shown in Fig. 3-1. This figure illustrates that holes obtain energy from the high electric field near the drain junction to form “hot carriers”. As the energy of the hot holes is sufficiently high, impact ionization process may trigger and generate electron-hole pairs. Some of the generated electrons may become energetic and surmount the barrier height at the oxide interface and then inject into gate insulator to form negative oxide trap charges which cause positive shift in threshold voltage. The hot carriers may also release their energy near oxide/channel interface and in the channel, and leave additional defects and interface states therein which will degrade the subthershold swing and mobility.

Figure 3-2 displays the electrical characteristics for a test transistor with SSW

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before and after DC stress. The stress testing was done under VD = -15 V and VG = Vth

- 3 V for 1000 s. It can be observed that the only obvious change before and after stress for the I-V curve in Fig. 3-2 (a) is the off current, which is suppressed under the forward mode and becomes independent of the gate bias. Under the reverse mode, the I-V curves before and after stress resembles each other with negligible change. In the figures the fresh device exhibits an off current which increases with increasing difference between the drain voltage and the gate voltage, a feature characteristic of band-to-band tunneling (BTBT) conduction process shown in Fig 3-3(a). In the figure direct BTBT is assumed, in the present case the defects presenting in the poly-Si layer would contribute to the trap-assisted paths and further enhance the conduction. As aforementioned, some electrons would be generated by impact ionization near the drain junction and then got trapped in the gate oxide near the drain junction. The negative charges would raise the local potential, relieve the electric field and suppress the BTBT current, as shown in Fig. 3-3(b). This explains the suppression of off-state current in Fig. 3-2(a) after the stress. For the reverse mode shown in Fig. 3-2(b), the nominal source now is where BTBT is taking place and the current is not affected since negligible electrons are trapped wherein.

In fact, it is hard to obtain sufficient information to resolve the degree of degradation under hot-carrier stress just by analyzing the forward and reverse modes of transfer curves, and also hard to conceive details about the location-dependent damage in the device. For example, Figs. 3-4(a) and (b) show the device characteristics before and after stress with stress condition the same as that of Fig. 3-2 except with a different gate bias VG = Vth - 5 V. The information revealed in the figures is basically the same as that given in Figs. 3-2(a) and (b) and cannot distinguish the major impact resulting from the use of different gate bias during

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stressing. However, the monitor transistors contained in the HCTFTs can be used to break such constraint. Fig. 3-5 and Fig. 3-6 show the characteristics of the monitor transistors of the devices characterized in Figs. 3-2 and 3-3, respectively. As can be seen in the figures, the major difference arising from different gate stress voltage is clearly reflected on the characteristics of DMT. Specifically, the lower gate bias (absolute value) under hot carrier stress operation has resulted in a larger shift in the threshold voltage of the DMT shown in Fig. 3-5(a), as compared with that shown in Fig. 3-6(a). Obviously the different outcomes are related to the amount of electrons trapped in the oxide. During the stress with identical V_D, (e.g., -15V), an increase in gate voltage reduces the voltage drop between drain and gate (ie. VD-VG) and therefore the electric field in the gate oxide therein reduces as well. As a result, the probability of electron injecting into the oxide is slashed and causes smaller shift in the threshold voltage, as shown in Fig. 3-6(a). Such effect associated with stress gate bias can be more clearly understood from the results illustrated in Fig. 3-7. In the figure we can find that the shift in threshold voltage is noticeable only in the DMT and increases with decreasing VG.

3.2 Hot Carrier Stress under Severe Stress Bias

Compared to the mild stress drain voltage investigated in last section, a raised drain voltage will increase not only the lateral electric field to enhance the impact ionization but also the vertical electric field. The latter would result in more electron trapping events as well as more generated interface states. To illustrate such impacts, we stressed the TT with a high VD of -20 V and VG = Vth - 3 V for 1000 s. In this case,

Compared to the mild stress drain voltage investigated in last section, a raised drain voltage will increase not only the lateral electric field to enhance the impact ionization but also the vertical electric field. The latter would result in more electron trapping events as well as more generated interface states. To illustrate such impacts, we stressed the TT with a high VD of -20 V and VG = Vth - 3 V for 1000 s. In this case,

在文檔中 金屬誘發側向結晶複晶矽P型多晶矽薄膜電晶體的元件特性及熱載子效應研究 (頁 21-0)