Chapter 1 Introduction
2.2 Measurement Setup
The subthreshold and output characteristics were measured by a Keithley 4200 semiconductor characterization system with Keithley Interactive Test Environment (KITE) software. During the process of measurement, temperature- regulated hot chuck was maintained at 30 ℃.
The major electrical parameters of devices can be extracted from the measurement of I-V curves. The threshold voltage, denoted as “Vth”,is defined as the value of VG when ID equals 10nA × under VD of 0.1V, where W and L are channel
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width and channel length, respectively. The subthreshold swing, denoted as “SS”, is calculated by the following equation:
SS = . (Eq. 2-1) Moreover, the change of threshold voltage (Δ Vth) and subthreshold swing (Δ SS) after bias stressing are calculated by the equations:
Δ Vth = Vth,stress - Vth,fresh,
Δ SS = SSstress - SSfresh, (Eq. 2-2) where the notation “fresh” and “stress” refer to the conditions before and after stressing, respectively. The on-current (Ion) is defined as the value ID at VG = -10V.
After stressing, the deviation of on-current is formulated by (ΔIon / Ifresh) × 100%.
Similarly, ΔIon = Ion,stress – Ion,fresh, where Ion,stress is defined as the value at VG= -10+Δ Vth. Finally, the field-effect mobility (μFE) is estimated by gm,max, which is described by the following equations.
gm = , μFE =
(Eq.2-3) where Cox is the capacitor of gate insulator.
2.3 Basic Electrical Characteristics
It is well known that the active layer prepared by MILC process takes advantage of needle-like grains directing across the channel from drain to the source, and the reduction in the quantity of trapped centers improves the carrier mobility as well as the device performance [29]. Fig. 2-8 shows the ID-VG curve for MILC and SPC devices; it is worthy to note that the MILC device shows greatly improved
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characteristics in terms of higher carrier mobility, lower Vth and SS as compared with the SPC one. The extracted performance parameters are summarized in Table 2-2.
According to the results, it is illustrated that a smaller grain size (in average) and absence of directional arrangement of grains along the channel degrade the performance of SPC devices [30].
It seems that MILC devices have better electrical characteristics than the SPC one. However, one disadvantage in application is the enhancement of leakage current arisen from metal contamination. This condition can be understood in Fig. 2-9(a) by comparing the difference in off-state ID between forward and reverse modes. Here the
“forward mode” denotes the case when the drain bias is applied to the heavily doping region where seeding window is located while the other electrode without seeding window is grounded and serves as the source. For “reverse mode” of operation, the above arrangement is simply interchanged. The leakage current is obviously higher under forward mode in the ASW device, as shown in Fig. 2-9(a). However, such difference is unobserved for the SSW device, whose leakage current is consistent between the two modes, as shown in Fig. 2-9(b). Note the leakage levels in the present case are high and comparable to that of the forward mode exhibited in the ASW device (Fig. 2-9(a)). These high leakage levels can be attributed to the existence of nickel-rich phases near the junction region. The contamination tends to induce additional defect levels inside the channel layer which are responsible for the increased leakage current. These defects act as generation centers and enhance the leakage at low VD via trap-assisted thermal generation process, and the leakage at high VD via trap-assisted field emission [31] [32]. As a result, the issue of metal contamination in MILC device must be considered to prevent the undesirable increase of leakage current. In this thesis, the offset region between gate edge and seeding
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window is set at 5
m. As compared with self-aligned seeding arrangement, such
offset can help reduce the number of nickel at the junction of drain [31].2.4 Effects of Channel Length and Seeding Window Configuration
As mentioned above, the film crystallinity of a MILC film is location-dependent and related to distance from the seeding window as well as the seeding window arrangement. Certainly such property will draw impacts on device performance and worth investigation.
Figures 2-10(a), (b), and (c) show typical transfer curves of SSW and ASW devices with channel length at 0.6, 2, and 10 μ m, respectively. Threshold voltage (Vth) and subthreshold swing (SS) of the two types of device as a function of channel length (L) are shown in Figs. 2-11(a) and (b), respectively. In Fig. 2-11(a), the ASW devices show Vth roll-off phenomenon, seeming to indicate the occurrence of short-channel effect. However, the SS shown in Fig. 2-11(b) improves with decreasing channel length, indicating that better film crystallinity in shorter-channel devices also accounts for the Vth reduction as compared with long-channel ones. On the other hand, the SSW devices generally exhibit worse performance in terms of higher Vth (absolute value) and SS than ASW ones at the same Length. Interestingly, the difference between the two types of devices is most significant at L of 2 and 5 m, and diminishes as L either decreases or increases.
From the above, it is seen that devices with shorter channel have superior Vth and SS to long channel ones. Such outcome is believed to arise from the variation in film crystallinity across the channel. To confirm this we performed SEM analysis on a B1 HC-TFTs (see Table 2-1) with ASW to check the film crystallinity in different regions
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of the channel. Excellent crystalline quality can only be observed in the DMT region which is most close to the MIC area, as shown in Fig.2-12. In this picture the surface looks quite flat that the grain boundaries are hardly resolved. In the range of CMT, the appearance of needle-like grains can be observed in Fig. 2-13, where the grain size is obviously smaller than that in the DMT region. Finally, at the source side, as shown in Fig. 2-14, it is apparent that the grains already become smaller and discrete, a feature associated with the occurrence of the SPC process [32].
The differences in film crystallinity actually reflect on the electrical characteristics of the monitor transistors, as shown in the Fig. 2-15. It is clear that the best performance among three monitor transistors is DMT and the worst one is SMT, confirming the difference in film quality examined with the SEM technique.
In Fig. 2-11, it is observed that the Vth and SS for the SSW devices are inferior to the ASW ones. This is believed to be related to the intersection of the two MILC fronts growing from the two seeding windows located at source and drain regions.
One SEM evidence is given in Fig. 2-16. This picture was taken from an SSW device and a defect-rich region is clearly observed in the middle of the channel. The abundance of defects acting as trap centers will degrade device characteristics [33].
Such defect-rich region draws different impact on devices with various channel length, as shown in Fig. 2-11(b) where the SS for SSW improves with decreasing length. This is mainly attributed to the improved crystallinity as the channel region gets closer to the seeding windows as analyzed in the ASW case. On the other hand, as L is increased from 5 to 10
m, the SSW devices characterized in Figs. 2-11(a) and (b)
show slightly decreased Vth and SS and reduce the difference with the ASW ones. As have been shown in Fig. 14, SPC granular structure is predominant at the central part of the channel for such long-channel devices. This would dilute the impact of the15
aforementioned defect-rich region on the device performance and explain why the difference between the ASW and SSW devices diminishes.
The above inference can be verified from the I-V curves of MTs embedded in an SSW HC-TFT shown in Fig. 2-17 and SEM pictures in Fig. 2-18. The measured results in Fig. 2-17, which has been normalized to the channel width, clarify the much superior performance in DMT and SMT to that of CMT. Figure 2-18(a) shows obvious jagged granular structure resulted in the middle of a CMT due to the confrontation of the two MILC fronts, and it signifies that many grain boundaries have been formed in the neighborhood of jagged structure. An enlarged view illustrated in Fig. 2-18(b) displays that there are many defects and sprawl grains near the jagged structure. Existence of such defect-rich region certainly impacts the device characteristics.
It is also worthy to know the impacts of granular structure of the poly-Si films on device characteristics, such as the lying orientation of needle-like grains as well as the location-dependent film crystallinity, are probed by a special test device shown in Fig.
2-19. In the device, in addition to the TT, an MT is also embedded with its source-to-drain direction vertical to the TT. Typical transfer characteristics are shown in Fig. 2-20, in which the drain current has been normalized to the channel width. It can be observed that the on-current of the TT is higher than that of the MT. The extracted parameters are summarized in Table 2-3. It can be seen that TT exhibits higher on-current and field-effect mobility than the MT. This is primarily attributed to the reduced number of grain boundaries counted from source to drain in the TT than that in the MT, owing to the needle-like grains originating from the seeding window [34].
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Table 2-1. Dimensions of two types of HC-TFT testers.
Table 2-2. Performance parameters extracted from Fig. 2-8.
Table 2-3. Major parameters extracted from Fig. 2-19.
(V) (mV/dec.) (cm2/Vs)
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Chapter 3
Hot Carrier Degradation under Static Stress
In order to study the degradation induced in MILC devices due to hot-carrier effects, various static stress conditions were executed on the HC-TFTs. The change in the characteristics of test transistor and monitor transistors were recorded and analyzed. The difference between MILC and SPC devices were resolved by taking advantage of HC-TFTs.
3.1 Hot Carrier Stress under Mild Stress Bias
Mechanisms of hot-carrier degradation in p-channel MILC devices are similar to other types of poly-Si TFTs with the schematic shown in Fig. 3-1. This figure illustrates that holes obtain energy from the high electric field near the drain junction to form “hot carriers”. As the energy of the hot holes is sufficiently high, impact ionization process may trigger and generate electron-hole pairs. Some of the generated electrons may become energetic and surmount the barrier height at the oxide interface and then inject into gate insulator to form negative oxide trap charges which cause positive shift in threshold voltage. The hot carriers may also release their energy near oxide/channel interface and in the channel, and leave additional defects and interface states therein which will degrade the subthershold swing and mobility.
Figure 3-2 displays the electrical characteristics for a test transistor with SSW
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before and after DC stress. The stress testing was done under VD = -15 V and VG = Vth
- 3 V for 1000 s. It can be observed that the only obvious change before and after stress for the I-V curve in Fig. 3-2 (a) is the off current, which is suppressed under the forward mode and becomes independent of the gate bias. Under the reverse mode, the I-V curves before and after stress resembles each other with negligible change. In the figures the fresh device exhibits an off current which increases with increasing difference between the drain voltage and the gate voltage, a feature characteristic of band-to-band tunneling (BTBT) conduction process shown in Fig 3-3(a). In the figure direct BTBT is assumed, in the present case the defects presenting in the poly-Si layer would contribute to the trap-assisted paths and further enhance the conduction. As aforementioned, some electrons would be generated by impact ionization near the drain junction and then got trapped in the gate oxide near the drain junction. The negative charges would raise the local potential, relieve the electric field and suppress the BTBT current, as shown in Fig. 3-3(b). This explains the suppression of off-state current in Fig. 3-2(a) after the stress. For the reverse mode shown in Fig. 3-2(b), the nominal source now is where BTBT is taking place and the current is not affected since negligible electrons are trapped wherein.
In fact, it is hard to obtain sufficient information to resolve the degree of degradation under hot-carrier stress just by analyzing the forward and reverse modes of transfer curves, and also hard to conceive details about the location-dependent damage in the device. For example, Figs. 3-4(a) and (b) show the device characteristics before and after stress with stress condition the same as that of Fig. 3-2 except with a different gate bias VG = Vth - 5 V. The information revealed in the figures is basically the same as that given in Figs. 3-2(a) and (b) and cannot distinguish the major impact resulting from the use of different gate bias during
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stressing. However, the monitor transistors contained in the HCTFTs can be used to break such constraint. Fig. 3-5 and Fig. 3-6 show the characteristics of the monitor transistors of the devices characterized in Figs. 3-2 and 3-3, respectively. As can be seen in the figures, the major difference arising from different gate stress voltage is clearly reflected on the characteristics of DMT. Specifically, the lower gate bias (absolute value) under hot carrier stress operation has resulted in a larger shift in the threshold voltage of the DMT shown in Fig. 3-5(a), as compared with that shown in Fig. 3-6(a). Obviously the different outcomes are related to the amount of electrons trapped in the oxide. During the stress with identical VD, (e.g., -15V), an increase in gate voltage reduces the voltage drop between drain and gate (ie. VD-VG) and therefore the electric field in the gate oxide therein reduces as well. As a result, the probability of electron injecting into the oxide is slashed and causes smaller shift in the threshold voltage, as shown in Fig. 3-6(a). Such effect associated with stress gate bias can be more clearly understood from the results illustrated in Fig. 3-7. In the figure we can find that the shift in threshold voltage is noticeable only in the DMT and increases with decreasing VG.
3.2 Hot Carrier Stress under Severe Stress Bias
Compared to the mild stress drain voltage investigated in last section, a raised drain voltage will increase not only the lateral electric field to enhance the impact ionization but also the vertical electric field. The latter would result in more electron trapping events as well as more generated interface states. To illustrate such impacts, we stressed the TT with a high VD of -20 V and VG = Vth - 3 V for 1000 s. In this case, the device characteristics of the TT shown in Fig. 3-8(a) exhibit similar trend revealed in Fig. 3-2(a) and Fig, 3-4(a). However, in Fig. 3-8(b), the I-V curves of the DMT
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deviate significantly after the stress, while negligible changes are found in the results of CMT and SMT as shown in Fig. 3-8(c) and Fig. 3-8(d), respectively. When a comparison is made between Fig. 3-5(a) and Fig. 3-8(b), it is clear that a larger positive shift in Vth is resulted as the stress drain voltage is increased, arising from the increase of electron injection in the gate oxide. Figs. 3-9(a) and (b) show the shift in Vth and SS as a function of the stress drain voltage. It can be seen that increasing electron trapping in the DMT with increasing stress drain voltage stated above is clearly illustrated in Fig. 3-9(a). Another major impact is the increase in SS for the DMT devices, as shown in Fig. 3-9(b). This phenomenon can be better understood with the I-V curves shown in Figs. 3-10(a) and (b), in which the drain currents of the DMTs depicted in Fig. 3-8(b) and Fig. 3-5(a), respectively, are expressed as a function of gate overdrive (VG-Vth). The inferior characteristics arise mainly from the generation of additional defects in the channel and interface states at oxide/channel interface. With higher stress drain voltage, the resultant damage is stronger in term of worse SS, as evidences in Figs. 3-9(b), 3-10(a), and 3-10(b).
As aforementioned, the raise in stress Vg would alleviate the vertical electric field in the oxide near the drain junction to reduce the amount of trapped electrons.
However, such damage is minor as the stress drain voltage is mild and hard to detect with the TT only. It thus needs a high stress drain voltage to resolve the degradation mechanism. Figures 3-11(a), (b) and (c) show the on-current, SS degradation, and Vth
shift, respectively, of TT and MTs contained in this tester as a function of stress VG
with VD = -20 V for 1000 sec. It can be seen that the DMT shows the highest sensitivity to the applied stress conditions. In Fig. 3-11(c), it is interesting to see that the Vth shift of DMT monotonically increases with decreasing VG, which can be used to explain the same trend about the drain current degradation shown in Fig. 3-11(a).
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This is owing to the increase in (VG - VD) as VG becomes smaller, so that the strength of electric field in the gate oxide of the DMT increases. For VG = 0, the high field strength would result in significant F-N tunneling process, resulting in significant degradation in SS and Vth shift. However, the SS degradation shown in Fig. 3-11(b) exhibits a dip at VG = -2.5V. Such trend is different from that shown in Figs. 3-11(a) and (c). To more clearly understand such disparity, we examine the subthreshod characteristics of the TT device under various VD. We can see that, at VG = 0, a significant GIDL current which is comparable or even higher than that at VG = -2.5V is observed. This means that additional carriers are present in the channel during stressing at VG = 0 which may become energetic and result in damage. However, the damage mechanism is presumably different from that of normal channel hot carrier effects when VG is larger than Vth (absolute value). This explains why the SS degradation trend shown in Fig. 3-11(b) is different from that of on current degradation and Vth shift.
Band diagrams at VG = 0 along the vertical direction (located in the DMT) and along channel direction are illustrated in Figs. 3-13(a) and (b), respectively, in which the band-to-band tunneling process is described. That is, due to the strong drain bias, a portion of the electrons generated by BTB tunneling would not only cause impact ionization near the drain junction but also tunnel or surmount the barrier height at the oxide interface and then get trapped in the oxide. On the other hand, most of the electrons would drift along the channel and contribute to the GIDL shown in Fig. 3-12.
The voltage drop occurs mainly in the DMT region, and it is believed that these electrons may degrade the channel as they drift through the DMT region. This would result in aggravated SS degradation observed in Fig. 3-11(b)
Figures 3-14(a), (b), (c) show the relation between shift of Vth, on-current
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degradation, and SS degradation, respectively, with stress time under stress condition at VG = Vth - 3 V and VD = -20 V. For DMT, the change of Vth (Fig. 3-14(a)) mainly occurs in the beginning and tends to saturate as the stress time is sufficiently long.
This can be more clearly understood with the transfer curves of the DMT shown in Fig. 3-15. Such saturation is reasonable owing to the trapping of the electrons which causes the shift of Vth and consequently a reduction in the vertical electric field in the oxide. Similar situation also happens to the cases of on-current and SS degradation described in Fig. 3-14(b) and Fig. 3-14(c).
3.3 Hot Carrier Effects in MILC and SPC Devices
As aforementioned, due to the reduced number of grain boundaries presenting along the channel, the MILC devices have superior performance over SPC devices.
The hot carrier effects in MILC devices have already been analyzed in Sections 3-1 and 3-2. Finally, in this section, we address the difference in post-stress characteristics between MILC and SPC devices. To make a comparison between MILC and SPC
The hot carrier effects in MILC devices have already been analyzed in Sections 3-1 and 3-2. Finally, in this section, we address the difference in post-stress characteristics between MILC and SPC devices. To make a comparison between MILC and SPC