Chapter 5 Conclusions
A fully integrated, low voltage and low power CMOS LC-VCO with negative conductance enhancement and common mode noise reduction is proposed and implemented by TSMC 0.18-μm 1P6M CMOS process. The design uses the conventional NMOS only cross-coupled topology combined with an NMOS pair to improve the phase noise performance in low voltage operation. The proposed LC-VCO consumes 1 mW with 0.51 V supply voltage. The measured phase noise at 1 MHz offset frequency is -112.24 dBc/Hz at 3.3GHz. Although the supply voltage and power consumption are obviously improved, there is still a lot of space for noise reduction. Several extensive studies have been underway to further reduce the phase noise of LC-VCOs. In this field, it maybe worth our effort in the future works, such as low phase noise LC-VCOs.
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