Chapter 4 Design of a Fully Integrated Low Voltage Low
4.3 D esign and Analysis of the Proposed LC VCO
4.3.2 Common Mode Noise Reduction
Common mode noise is an unwanted noise, which upconvert to the carrier frequency and result serious jitter and weak phase noise performance in LC VCOs.
For this reason, we employ a common mode noise reduction method to suppress the common mode noise [11-12]. Figure 4.10 shows the common mode noise rejection of the proposed LC VCO.
Figure 4.10 Common mode noise reduction of the proposed LC VCO diagram.
The common mode voltage Vcm is
T (
m
I ) Vcm V
≅ + g (4-4)
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
where I is the total current in the VCO, VT and gm are the threshold voltage and transconductance of the NMOS respectively. The -△Vgb and +△Vgb are the gate to bulk terminal voltage of the proposed NMOS pair (M3 and M4) and varactors (C1 and C2) respectively. In order to reduce the common mode noise, the symmetry of differential tuning is needed. According to mathematical analysis, the capacitances of NMOS pair and varactors can be shown as
0 1
(- )
Where C0 is the zero bias capacitance, the Vncm is common mode noise and the kv1 and kv2 are the capacitor gain of NMOS pair and varactors respectively. If the perfectly selection is achieved such thatv1
k = − k
(4-6) then the total capacitance C is
C = 2 C
0+ 2 kv Vgb Δ
(4-7) where C=CN+CV, △Vgb =+△Vgb –(-△Vgb). In equation (4-7), the common noise is canceled out. If not, the gain of the common mode noise is
k
v1− k
v2 (4-8) As the common mode noise rejection has been explained above, the compared results between proposed LC VCO and conventional one is presented in next section.Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
4.4 Simulation Results
Figure 4.11 shows the simulated phase noise with different body bias of the NMOS pair. As we can see, the best phase noise is around 0.6 V.
0.0 0.2 0.4 0.6 0.8
Figure 4.12 Compared phase noise of two LC VCOs.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
In the proposed LC VCO, the phase noise is -118.32 dBc/Hz at 1 MHz offset from carrier frequency. The improvement between conventional and proposed LC VCOs is about 6 dBc/Hz at 1 MHz offset frequency. Another parameter Kvco is also improved as shown in Figure 4.13.
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 60.0M
Figure 4.13 The compared result of Kvco.
As shown in equation (4-9), the figure of merit (FOM) is widely used to compare the VCO performance among the different designs
( )
10 log 20 log 0 proposed VCO are evaluated and are equal to -192 dBc/Hz.In addition, in order to match the simulated results, the pad-effect which is provided by national chip implementation center (CIC) as shown in Figure 4.14
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
should be take into consideration. In post simulation, we finished the EM simulation by Agilent advanced design system (ADS) Momentum design tool.
Figure 4.14 The equivalent model of pad-effect.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
4.5 Measured Results
In this section, the measurement results of the proposed LC-VCO are presented. In Figure 4.15 and Figure 4.16, the chip layout and microphotograph of the proposed LC-VCO are shown, respectively. The LC-VCO is fabricated in TSMC 0.18-μm 1P6M CMOS process. Its chip area including pads is 0.61×0.76 mm2.
Figure 4.15 The chip layout of the proposed LC-VCO.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
Figure 4.16 The Microphotograph of the proposed LC-VCO.
The LC-VCO chip was measured by on-wafer probe method. Figure 4.17 shows that the measured phase is -112.24 dBc/Hz with 0.51 V supply voltage.
According to the measured current in Figure 4.18, the chip drew a total DC current is 2.05 mW. The power consumption which including buffer circuits of the LC VCO is 1.05 mW. Figure 4.19 shows the output spectrum. The measured VCO’s gain is drawn in Figure 4.20. In table 4.2, the measured results are summarized and compared with related LC VCOs.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
Fig. 4.17 Measured phase noise of the proposed LC VCO.
Fig. 4.18 Measured characteristics of the proposed LC VCO.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
Fig. 4.19 Output spectrum of the proposed LC VCO.
Fig. 4.20 The measured gain of the proposed LC VCO.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
Chapter 5 Conclusions and Future Work
Chapter 5 Conclusions
A fully integrated, low voltage and low power CMOS LC-VCO with negative conductance enhancement and common mode noise reduction is proposed and implemented by TSMC 0.18-μm 1P6M CMOS process. The design uses the conventional NMOS only cross-coupled topology combined with an NMOS pair to improve the phase noise performance in low voltage operation. The proposed LC-VCO consumes 1 mW with 0.51 V supply voltage. The measured phase noise at 1 MHz offset frequency is -112.24 dBc/Hz at 3.3GHz. Although the supply voltage and power consumption are obviously improved, there is still a lot of space for noise reduction. Several extensive studies have been underway to further reduce the phase noise of LC-VCOs. In this field, it maybe worth our effort in the future works, such as low phase noise LC-VCOs.
References
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