Chapter 1 Introduction
1.3 Thesis Organization
There are five chapters of the thesis. Chapter 2 deals with the basic concepts and parameters of VCOs. In chapter 3, some advanced popular VCO topologies are reviewed. In chapter 4, we proposed a design of low voltage and low power consumption CMOS LC VCO with the simulated and measured results. Chapter 5 conclusion is drawn.
Chapter 2 Design Basics of CMOS LC VCO
Chapter 2 Design Basics of CMOS VCO
2.1 Fundamental Characteristics of LC VCO
In general, the VCO is a spontaneous circuit which starts up by inherent noise and retains a stable oscillation by positive feed back and negative resistance. The VCO is used as a local oscillator that generates a precise periodic waveform for frequency up and down translation in mixer. In the analysis of VCOs, the negative resistance model (one-port network) is widely used. As shown in Figure 2.1, the oscillator is treated as two parts that one is an active circuit part and the other is resonant circuit part.
Figure 2.1 Negative resistance model of a VCO.
Chapter 2 Design Basics of CMOS LC VCO
When the resonator or a LC-tank resonates at a target frequency, an existed loss, represented by an equivalent resistance Rp (mostly comes from the inductor), reduces the oscillated amplitude and results in operation stop. Therefore, the active circuit provides an equivalent negative resistance -Rs to compensate the energy loss.
As shown in Figure 2.2, the negative resistance -2/gm needs to satisfy the condition that
2/gm ≧ Rp (2-1)
Figure 2.2 Negative resistance model of NMOS cross-coupled LC VCO
Chapter 2 Design Basics of CMOS LC VCO
The feedback model (one-port network) is also a popular method and is widely used in the oscillator analysis. Figure 2.3 shows the block diagram of the feedback model. The transfer function of the output/input is given as
( ) ( )
( ) 1 ( ) ( )
Xo s A s
Xs s = A s H s
− (2-2) where is complex frequency. The oscillation will keep in certain amplitude if the open loop gain
s
( ) ( ) ( )
Ao s = A s H s
(2-3) with
Ao ( ) 1 ω
0=
&∠ Ao j ( ω
0) = 0
(2-4) This is the so-called Barkhauen criterion, whereω0 is the radian frequency of oscillation. The Barkhauen criterion of the feedback circuit is a necessary condition but not a sufficient condition. Actually, the loop gain was chosen to be at least two or three times.Figure 2.3 Feedback model of a VCO.
Chapter 2 Design Basics of CMOS LC VCO
2.2 LC Tank
Figure 2.4 shows the series resonant circuit and the parallel resonant circuit with input impedance Zin given by, respectively,
Zin R j L 1
Figure 2.4 (a) Parallel resonator (b) series resonator.
The energy stored in the L and C are given by, respectively,
1 2 he input impedance and oscillating frequency are
T
Zin R= (2-8)
0 1
ω ω= = LC (2-9)
Chapter 2 Design Basics of CMOS LC VCO
From the analysis of LC-tank, the Q (quality) factor is given as average enegy store
Q=ω average energy loss per cycle (2-10)
Therefore the Q factor of the resonant circuit is 0
One of the most important characteristic of VCOs is phase noise which represents the purity and stability of the output signal of a VCO. The signal to noise ratio (SNR) is also affected by phase noise greatly in a transceiver. In light of ideal case, the output spectrum of an oscillator has only one impulse at the fundamental frequency as shown in Figure 2.5(a). In practice, however, the output spectrum of an oscillator is not so clear due to the spurious signals come from its harmonics or intermodulation products. Then the noise skirts which spread the fundamental output tone at oscillated frequency in a VCO, as shown in Figure 2.5(b).
An ideal sinusoidal wave form is defined as
( ) cos( 0 )
V t = A ωt+ (2-12) φ where A is the oscillated amplitude, ω0 is oscillated frequency and φ is a random phase. The waveform function should be
V t( )= A t f( ) (ω0t+φ( ))t (2-13) where the oscillated amplitude A t( ) and phase φ( )t are functions of time t, the function f has the period of 2π . The jitter can cause the amplitude fluctuation and phase fluctuation in a VCO. Mostly, the amplitude fluctuation can be neglected due to
Chapter 2 Design Basics of CMOS LC VCO
the voltage limiter or nonlinearity effect of the circuits, but the phase fluctuation can not.
Figure 2.5 Output spectrum of ideal and realistic oscillators.
There are several methods to describe the frequency fluctuation of VCOs.
Here, we briefly present some works about phase noise model, one is D. B. Leeson and the other is A. Hajimiri.
2.3.1 Leeson’s Model
As the empirical method, the phase noise of signals is usually expressed in the description that relative to the carrier power per Hertz of bandwidth (dBc/Hz). The phase noise is typical expressed as [2]
( )
10log SSB Hz,1(
0) (
C
L P d
P
ω ω
ω ⎡ + Δ ⎤
Δ = ⎢ ⎥
⎣ ⎦ Bc Hz
)
(2-14) whereΔω is the offset frequency form the carrier frequency, PSSB Hz,1(
ω0+ Δω)
Chapter 2 Design Basics of CMOS LC VCO
represents the single sideband (SSB) power at a frequency offset ofω0+ Δ from the ω carrier with a measurement bandwidth of 1Hz, and PC is the carrier power, as shown in Figure 2.6.
Figure 2.6 The diagram of the oscillator power spectrum around the fundamental.
In 1966, D. B. Leeson proposed a model to describe the phase noise, this model is expressed as [2],
where F is the excess noise factor, K is the Boltamann’s constant, T is the absolute temperature, PS is the average power consumption of resonator, ω0 is the oscillator frequency, QL is the loaded Q, and
Δ ω
1 f3 is the corner frequency. Figure 2.6 does not express the actual shape of a SSB spectrum for a VCO, the actual SSB phase noise often approximate to the diagram shown in Figure 2.7, which shows the typical regions of phase noise of VCOs from the Lesson’s phase noise model. According to Figure 2.7, the corner frequencyΔ ω
1 f3 of 1 f phase noise should be equaled to 3 the corner frequencyΔ ω
1 f of 1 f phase noise of a device. However, after theChapter 2 Design Basics of CMOS LC VCO experimental steps, the
Δ ω
1 f3 is not equal to theΔ ω
1 f in an actual oscillator. The1 f3
ω
Δ
is a kind of empirical result without any physics significance. The powerspectral density of flicker noise of active devices (MOS) is proportional to 1 f . This results in the 1 f region and closes the oscillated frequency. 3
From equation (2-14), increasing the Q factor of a LC-tank and PS can improve phase noise effectively, but the Q factor and PS are usually restricted by the poor-Q inductor in CMOS process and low power applications respectively.
Figure 2.7 Phase noise curve of Lesson’s model.
Leeson’s phase noise model includes an empirical factor F in the description.
Therefore it can not analyze the phase noise of a VCO precisely. A more accurate model is proposed by Hajimiri and T. Lee in 1998 [8].
Chapter 2 Design Basics of CMOS LC VCO
2.3.2 Hajimiri Model
The Hajimiri model introduces impulse sensitivity function (ISF) to analyze the phase noise. This model can explain the mechanisms that how the flicker noise upconvert to phase noise in a VCO. An oscillator can be modeled as a system with n noise source inputs and two outputs that are the instantaneous amplitude and excess phase of an oscillator. Noise inputs to the system are in the form of current sources injecting into circuit nodes and voltage sources in series with circuit branches. For each noise input source, both systems can be considered as single-input, single-output systems. Then the time and frequency-domain fluctuations of and
can be characterized as the two equivalent systems shown in Figure 2.8.
( )
Figure 2.8 Phase and amplitude impulse response model.
A time varying impulse response can be written as [8]
( ) ( ) (
0where qmax is the maximum charge displacement across the capacitor and u(t) is the
Chapter 2 Design Basics of CMOS LC VCO unit step, τ is the time when the impulse is injected and Γ
( )
x is the impulsesensitivity function (ISF). Using the relevant Fourier series, then the Γ
(
ω τ0)
can beexpanded as
The phase noise depends on the time when the noise current is injected. In Figure 2.9 (a), the impulse at the zero crossing causes phase noise only and does not cause amplitude noise. As shown in Figure 2.9 (b), the impulse as the peak causes amplitude noise only. The amplitude of impulse response of phase depends on the time when the impulse is injected. The increment of amplitude is ΔV = ΔQ/C and the timing of the zero crossings does not change. In this system, the phase displacement depends on that the impulse is applied, the system is time variant.
t
Figure 2.9 Waveforms for impulse excitation.
Chapter 2 Design Basics of CMOS LC VCO
For a given impulse sensitivity function oscillator, the excess phase due to the noise current can be obtained
To general belief, the phase noise 1/f 3 is identical to the flicker noise 1/f. The equation
⎛ Δ
(2-19) indicates that the 1/f 3 region can be reduced once the Fourier coefficient C0 is diminished. On the other hand, the meaning of diminished C0 is the more symmetrical output waveform is achieved in a VCO. The Hajimiri model provides the exhaustive analysis on phase noise. This model can help the designer to understand the noises from each source and how they affect the phase noise. Finally, the designer can suppress the phase noise in an efficient way.
Chapter 3 Advanced Design of Related Works
Chapter 3 Advanced Design of Related Works
3.1 Basic CMOS LC VCO Topologies
Figure 3.1 (a)-(d) show the prototypes of conventional CMOS LC VCOs published in [2], [8-10]. Topologies in Figure 3.1 (a) with a tail current source and in Figure 3.1 (b)-(c) with top current sources have the advantage of less supply voltage due to less stages are stacked in vertical. Because they are not all control by the DC bias once the current sources are employed in Figure 3.1 (a)-(c), the VCOs could reduce the sensitivity of the proposed circuit gain versus the supply voltage effectively.
But, it means that the more supply voltage may be needed. Furthermore, the current sources will down convert the noise around 2 f by channel length modulation to the 0 phase noise and degrades the phase noise.
Because of the flicker noise performance in PMOS is better than that in NMOS, the cross-coupled PMOS LC VCO were usually employed as the active circuit as shown in figure 3.1 (b). The difference between Figure 3.1 (a) and Figure 3.1 (c) is that the output DC level is close to supply voltage and close to ground respectively.
Chapter 3 Advanced Design of Related Works
Figure 3.1 (a) NMOS cross-coupled LC VCO with a bottom current source. (b) PMOS cross-coupled LC VCO with a top current source. (c) NMOS cross-coupled LC VCO with a top current source. (d) Complementary cross-coupled LC VCO.
Chapter 3 Advanced Design of Related Works
In Figure 3.1 (d), the complementary LC VCO not only has the more symmetric topology which could suppress the 1 f noise up-conversion by its symmetric waveforms but also generates the output waveforms which are twice of that in NMOS or PMOS only architectures, therefore the complementary architecture has the better phase noise performance. However, comparing to another topologies in Figure 3.1, the complementary one consumes more voltage headroom and the larger size of transistors are needed to get enough transconductance to loose the overdrive voltage at low voltage operation, which results the increase of parasitic capacitance and decrease of tuning range. The LC VCOs in Figure 3.1 (a-c) have the related larger voltage headroom, the wider tuning range and the smaller size of transistors to start the oscillation than that in Figure 3.1 (d). But the cost is that the AM −FM conversion from the current source reducing the phase noise performance.
Figure 3.2 shows the LC VCO of two differential frequency tuning tanks [11-12]. Four varactors are used for frequency tuning instead of two varactors which
are employed in conventional design. When using varactors with the contrary polarities, the common mode voltage for V+ and V- are cancelled out. The varactors in Figure 3.2 are accumulation mode MOS varactors [13]. Tuning of all LC-tank oscillators may be achieved by tuning its effective capacitance with an appropriate bias control voltage (V+ and V-). Since CMOS junction capacitors have relatively poor Q, it is advisable to use as much junction capacitance as necessary to achieve the desired tuning range.
Chapter 3 Advanced Design of Related Works
Figure 3.2 Schematic of two differential frequency tuning LC VCO.
3.2 Related CMOS LC VCO Issues
In the past research, effort to reduce phase noise has been published in several methods, one of that is to reduce phase noise of the LC-VCO by adding external circuits and enhancing the quality factor (Q) [14]. In this method, the tail current is made large when the oscillator output voltage reaches its peak value and when the sensitivity of the output phase to injected noise is the smallest; the tail current is made small during the zero crossings of the output voltage when the phase noise sensitivity is large. But, this method consumes more voltage headroom and power consumption
Chapter 3 Advanced Design of Related Works
due to its tail current source. As shown in Figure 3.3 which proposes a harmonic tuned (HT) method that suppresses the harmonic frequency of the circuit by opening the fundamental and third frequencies and shortening the second harmonic by inserting L2, L3, C3 and C4 as a harmonic tuning network [5]. This method can reduce the phase noise effectively but the drawbacks are to increase the chip area and power consumption.
Figure 3.3 Schematic of simplified HT CMOS LC VCO
Chapter 3 Advanced Design of Related Works
Figure 3.4 shows the full PMOS LC VCO with a top current source [15]. In most cases, the major noise contributor in VCOs is the channel noise form CMOS transistors [16]. In this condition, the use of PMOS is more attractive since the PMOS transistors have lower 1 f noise than that in NMOS transistors [3], [17].
Furthermore, the large capacitor CE parallels the current source is needed because of the transistors of the differential pair might carry very little current for a fraction of the cycle. Thus, the duty cycle of the drain current waveform is reduced significantly.
As a result, the drain current noise injection during the zero-crossing of the tank differential voltage can be reduced and the better phase noise performance is achieved.
In addition, the CE attenuates both the high-frequency noise components of the tail current and the voltage variations on the tail node. The improvement of voltage variations results in more symmetric waveforms and smaller harmonic distortion in VCO outputs.
Figure 3.4 Full PMOS LC VCO
Chapter 3 Advanced Design of Related Works
It is well known that the higher quality factor can be achieved by exciting an inductor differentially rather than single ended [18]. Therefore, as shown in Figure 3.4, the use of a symmetric center-tapped inductor not only has the more symmetric output waveforms of the LC-tank but also has the benefits of the coupling factor to increase the inductance value and can lead to save the chip area.
In the design of low power CMOS LC VCO, current-reused is a method in common use [6-7], [19]. Figure 3.5 shows the schematic of the current-reused CMOS LC VCO. The current-reused LC-VCO uses both NMOS and PMOS transistor in cross-coupled pair as a negative conductance generator to achieve low power consumption easily. The series stacking of NMOS and PMOS allows the supply current to be reduced by half compared to that of the conventional LC-VCO while providing the same negative conductance. This topology is not only low power consumption but also low cost since it used only one inductor and two MOS transistors..
Figure 3.5 The current-reused LC VCO
Chapter 3 Advanced Design of Related Works
Another method for a VCO to operate in low power consumption is the transformer feedback (TF) structure [20]. As shown in Figure 3.6, the drain and source voltages are decreased when the gate voltage is increased simultaneously. The reduction of the source voltage lowers the ground potential effectively and allows the drain voltage to sweep to a negative potential before the transistor gets into the linear region. As a result, the phase synchronization provides extra voltage headroom for the drain oscillation, the drain voltage could swing above the supply voltage and the source voltage could swing below the ground level. Furthermore, the drain and source signals oscillate in phase. Substantially, the oscillation amplitude is enhanced, and consequently, the supply voltage can be reduced for the same phase noise with lower power consumption. In Figure 3.6, the TF VCO uses a single transformer for the feedback across the drain and source terminals, which structure is similar to the Hartley design [21-23].
Figure 3.6 Transformer-feedback LC VCO
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
4.1 Introduction
As the modern CMOS process technology has been scaled down and the market trend moves toward a greater scale of integration gradually, the reduction of power consumption has become considerably important to portable devices in the applications of wireless communication system. As we can see in Table 4.1, weather the RF technology or the analog and mixed signal technologies, all the supply voltage are forced to reduce by the shrink of process technology [24].
In general, the most direct and efficient way to reduce power consumption in circuit design is to reduce the supply voltage. However, the supply voltage is relies on the threshold voltage chiefly. Once the supply voltage can be reduce, the MOS transistors may go into subthreshold regime, this result will bring about the decrease of reliability. Furthermore, unfortunately, the low supply voltage is usually limits the output signal amplitude, which leads to degrades the signal to noise ratio and deteriorates the phase noise performance in turn.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
2.5-1.8 1.8-1.5 1.6-1.3 1.5-1.2 1.2-0.9 0.9-0.6 0.8-0.5
Frequency
(GHz) 1.8-2.5 2.5-3.5 3.0-4.0 3.5-5.0 5.0-6.5 6.5-9.5 9.5-13
In this chapter, we propose the design of low voltage and low power consumption CMOS LC-VCO with negative conductance enhancement and common mode noise reduction method. The section 4.2 briefly describes the low voltage LC VCO topology that can operate with less voltage headroom compared to complementary LC VCO topology due to less transistors are stacked in vertical direction. In the section 4.3, the low voltage LC-VCO with negative conductance enhancement method and common mode noise rejection is proposed. Comparing to conventional LC VCO, the simulated results are illustrated in section 4.4. In section 4.5, the measured results are shown.
Chapter 4 Design of a Fully Integrated Low Voltage Low Power CMOS LC VCO
4.2 Low Voltage and Low Power LC VCO
In the design of LC VCO in low voltage operation, it mostly restricted by the threshold voltage of MOS transistors. However, as the advancement of CMOS process technology continue increasing, the threshold voltage of MOS transistors can be reduced to milivoltage level. It is a good deal for the design of low supply voltage LC VCOs. However according to the Leeson model of phase noise, we can see that there have two ways to improve the phase noise performance, one is to increase Q factor and another is to increase the average power in the LC-tank. Due to the serious loss of inductor in CMOS process technology, the first method mostly dominated by inductor which has the poor Q factor than varactors. The later method means that the more power consumption (or supply voltage) is needed. In the consideration of power-saving, this method is not efficient enough. Therefore, how to design a low voltage, low power consumption LC VCO and maintain comparable phase noise level is a difficult problem.
Figure 4.1 shows the conventional design of low supply voltage LC VCO. The LC-VCO consists of two deferential symmetrical inductors (L1 and L2), two accumulation-mode MOS varactors (C1 and C2) and a MIM capacitor (C3). The NMOS cross-coupled pair (M1 and M2) serves as the negative resistance to compensate for the energy losses from the LC-tank. The C3, L1 and L2 set the fix frequency while the C1 and C2 with the control voltage make the frequency tunable.
The circuit has a symmetric topology to create symmetric output waveforms, which
The circuit has a symmetric topology to create symmetric output waveforms, which