A high linear transconductor employing negative impedance load for high frequency
UWB LPF has been presented in Chapter 3 & Chapter 4. These techniques improve the
linearity and improve the harmonic distortion. Using negative impedance load makes the filter
suitable for high frequency. The LPF circuit implemented in 0.18-µm CMOS process shows a
band ripple of ±1.32dB while drawing 43.2 mW from a 1.8-V supply. If for a SOC
application, the buffer is not needed to drive an ADC and the power consumption will be
about 36.2mW from a 1.8-V supply. Compare the filter with other spec. in Chapter 5. This
topology is applied to the RF front-end design for the UWB direct conversion transceiver.
6.2 Recommendations for Future Work
To increase the accuracy of this filter, the quality tuning and frequency tuning circuit can
be combined in the filter [15] [16] [17]. In the VCO tuning loop both frequency and quality
factors can be tuned. The VCO consists of two integrators and its frequency and quality factor
can be controlled. Figure 6.1 shows the Master-Slave frequency tuning technique by PLL.
The circuit generates the control voltage (Vtune) which makes the frequency of VCO based
on Gm-C gyrator is equal to the reference frequency. By this control voltage, the cutoff
frequency of the filter can be set to the desired value. A quality factor adjustment circuit is
also designed to compensate for the parasitic resistance shown in Figure 6.2.
There are three cases for the Q-tuning loop:
(a)If the integrators of the VCO have phase lead at the oscillating frequency ωo
(1/Qint(ωo) >0 ), the poles of the VCO are in the left complex half-plane. The VCO output is
a sine wave with exponentially decreasing amplitude.
(b) If the integrators of the VCO have phase lag at ωo (1/Qint(ωo) <0 ), the poles of the
VCO are in the right complex half-plane. The VCO output is a sine wave with exponentially
increasing amplitude.
(c) Finally if the integrators of the VCO have no phase error at ωo (1/Qint(ωo) = 0 ), the
poles of the VCO are in jω axis. The VCO output is a sine wave with constant amplitude.
The Q-tuning loop controls the mplitude of the VCO in a way that it will oscillate with a
constant amplitude at infinite Qint(ωo).
Figure 6.1 Frequency tuning technique
Figure 6.2 Quality tuning technique
The other way to reduce the transconductance variation due to threshold-voltage
variation is to use a threshold-voltage compensation circuit [18]. Figure 6.3 shows a
conventional current source with threshold voltage compensation. Neglect the channel length
modulation, the current source I2 can be expressed as:
Then the current source is varied with the difference between Vtc1 and Vt2 rather than Vt2.
If the transistors MC1 and M2 are locally matched, the current I2 is independent of the
threshold voltages.
Figure 6.3 bias circuit using threshold compensation technique
50 100 150 200 250 300 350 400 450
Figure 6.4 the filter magnitude response with four transistor corner cases
50 100 150 200 250 300 350 400 450
0 500
-70 -60 -50 -40 -30 -20 -10 0
-80 10
Frequency (MHz)
Magnitude (dB)
SS SF FS
FF
Figure 6.5 after adding voltage threshold compensation biasing circuit
If we consider the four transistor corner cases the cutoff frequency will vary from
200MHz (SS) to 270MHz (FF) as shown in Figure 6.4. After adding voltage threshold
compensation biasing circuit, the SF & FS cases will be restrained in Figure 6.5. The
implementation of this bias skill or other tuning networks will be in the Future works.
The LC ladder topology can be used as broadband matching. The original method of LC
ladder filter depends on the input / output impedance as shown in Figure 6.6. The synthesis
steps are to match input impedance to output impedance. If the LC filter load impedance is the
circuit input like Distributed Amplifier (DA), the difference of is that the DA input impedance
would change with frequency. The principle of broadband matching can make the DA input
equal to source impedance with a wide frequency range. The theory of broadband matching
may not suit for receiver for the lack of NF optimization and detail analysis can be found in
(a)General filter (b)Broadband matching Figure 6.6 LC ladder can be used to match complex load
For high frequency applications, all the Gm blocks have to be implemented with high
output impedance and high quality factor. Since the negative impedance load can increase
differential gain and make common mode gain less than one, besides it doesn’t cost additional
power. If the Gm block have RHP-zero about one hundred times higher than the most high
frequency pole or zero, adding negative impedance to other Gm is suitable for high frequency
filter.
Appendix A
Symmetric & Un-symmetric Differential Pair
The cross-coupled quad cell can be shown in Figure A.1. Assume all the MOSFET are in
the saturation region and neglect body effect. The square-law function can be characterized
as:
)2
( GS th
D k V V
I = − (A.1)
Figure A.1Cross-coupled quad cell
Neglect channel length modulation and second-order effects in this analysis, the pair M1
and M2 in Figure A.1 can has relation as:
vn M1
vp
M2
(n+1)I
M3 M4
(n+1)I (n+1)I-i
k nk k nk
(n+1)I+i
I+i1 nI-i1
I-i2 nI+i2
nk
After some arrangements for (A.2):
n
(A.4) can be obtained:
( ) ( )
After calculating (A.5):
[ ]
For the same reason, we can deduce that:
If the input signal level increases, M1 will first enter into cut-off region, that is,
n
The input signal level continues to increase, M2 will also cut-off.
( ) ( )
From the above analysis, we can calculate the bounded value of y1 and y2 as following
shows.
Having (A.12) we can determine large-signal transconductance characteristic gm12 by
straight forward differentiation.
adding and subtracting output currents in input stage, approximate cancellation of the
remaining nonlinearities can be obtained.
Figure A.2 Symmetric & un-symmetric differential pair
vn vn vn
(n+1)I (2d)I (n+1)I
(n+d+1)I (n+d+1)I
I nI nI I
gon gop
k nk pk pk nk k
VDD
The calculation can be easily to obtain the normalized transfer function yd of
symmetrical differential pair, which is listed below:
Determine the normalized transconductance characteristic gmd from yd :
equation (A.13) and (A.15), gm is fully determined by the three parameters: n, d and p. Thus,
we can impose three conditions upon the characteristics gm12 and gmd in order to determine
uniquely the values of n, d and p.
According to the normalized transfer characteristic, we have the following assumptions
[5]:
1. The value of parameter n has to be chosen in such a way that gm12 is constant in the right neighborhood of x=[(n+1)/n]0.5
2. The values of d and p have to be chosen in such a way that gmd(x) vanished exactly for x=
±[(n+1)/n]0.5
3. The values of d and p have to be chosen in such a way that gmd(0) = gm12(0) - gm12([(n+1)/n]0.5).
From the three assumptions, we can uniquely determining the values of n, p and d as
shown in table A.1.
Table A.1 OTA design parameters
n p d
4.236 1.288 0.796
Appendix B
LC Ladder analysis
WhereY2,4 =sC1,2 , 6 1 5
out
calculate (a):
calculate (b):
Ro
calculate (c):
Ro
calculate (d):
Ro
Add (a) ~ (b):
Reference
[1] “FCC Notice of Proposed Rule Making, Revision of Part 15 of the Commission’s Rules Regarding Ultra-Wideband Transmission Systems,” Federal Communications Commission, Washington, DC, ET-Docket 98-153.
[2] Bram Nauta, “A CMOS transconductance-C filter technique for very high frequencies,”
IEEE J. Solid-State Circuits , vol. 27, no.2, pp. 142-153 , February. 1992
[3] Stanislaw Szczepanski, Jacek Jakusz, and Rolf Schaumann “A linear fully balanced CMOS OTA for VHF filtering applications ,” IEEE Transactions on circuits and systems , vol. 44, no. 3, pp. 174-187, March 1997.
[4] Celma S., Sabadell J., Aldea C., and Martinez P.A., “CMOS pseudo-differential transconductor for VHF applications,” Electronics Letters , Volume: 35 , Issue: 18, pp.
1540-1542 September. 1999
[5] Slawomir Koziel, and Stanislaw Szczepanski, “Design of Highly Linear Tunable CMOS OTA for Continuous-Time Filters ,” IEEE Transactions on circuits and systems , vol. 49, no.
2, pp. 110-122, February 2002.
[6] Harrison, J.; Weste, N. “A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedbacks,” Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
[7] Pankaj Pandey,Jose Silva-Martinez, and Xuemei Liu, “A 500 MHz OTA-C 4th order Lowpass Filter with Class AB CMFB in 0.35um CMOS Technology,” Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004 , 3-6 ,pp. 57-60 October. 2004
[8] Mingdeng Chen, Mohieldin, A.N., and Jose Silva-Martinez , “Linearized OTAs for high-frequency continuous-time filters: a comparative study”. 2002. MWSCAS-2002.
The 2002 45th Midwest Symposium on , Volume: 3 , 4-7 August. 2002.
[9] Paul R. Gray and Robert G. Meyer, Stephen H. Lewis, Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits,” 4th edition, 748-784, 2000.
[10] F.Krummenacher, N.Joehl, “A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” IEEE J. of Solid-State Circuits, Vol. 23,pp 750-758, June 1998.
[11] Torrance, R.R., Viswanathan,T.R., and Hanson, J.V., ”CMOS voltage to current transducers”, IEEE Trans. Circuits Syst., 1985, 32, pp. 1097-1104
[12] C.S. Kim, Y.H. Kim, S.B. Park, “New CMOS Linear Transconductor,” Electronics Letters, Vol.28 No.21, October 1992.
[13] Khorramabadi, P.R. Gray, “High Frequency CMOS Continuous-time Filters,”IEEE J.
Solid-State Circuits, Vol. SC-19, pp. 939-948, Dec. 1984.
[14] G.A. De Veirman , R.G. Yamasaki, “Design of a Bipolar 10-MHz Programmable Continuous-Time 0.05° Equiripple Linear Phase Filter,” IEEE J. of Solid-State Circuits, Vol. 27, pp. 324-331, March 1992.
[15] Choi Yu Wing, “A 70MHz CMOS Gm-C Bandpass Filter with Automatic Tuning” Ph.D.
dissertation, Univ. of Hong Kong of Science and Technology, Aug. 1999.
[16] J.S. Martinez,S.J. Steyaert, “A 10.7MHz 68-dB SNR CMOS Continuous Time Filter with On-Chip Automatic Tuning ”IEEE JSSC.vol.27, No.12, Dec. 1992
[17] Rolf Schaumann, Mac E.Van Valkenburg, ”DESIGN OF ANALOG FILTERS ” Oxford express, 2001
[18] Shu Yuan Chin, Chung Yu Wu, “A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources ”IEEE JSSC.vol.29, No.11, Nov. 1994
[19] Chen, Wai-Kai, ”Broadband matching : theory and implementations ” World Scientific, 1988
[20] Shinichi Hori, Tadashi Maeda, Hitoshi Yano, Noriaki Matsuno, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Tomoyuki Yamase, Robert Walkington, and Hikaru Hida “A Widely Tunable CMOS Gm-C With a Negative Source Degeneration Resistor Transconductor ”Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European 16-18 Sept. 2003 Page(s):449 – 452
[21] Luo Zhenying, M.F. Li, Young Lian, and S.C. Rustagi, “CMOS Transconductor Design For VHF Filtering Applications,” IEEE Circuits and Systems, 2003. ISCAS '03.
[22] Actur Lewinski, and Jose Silva-Martinezi, “OTA Linearity Enhancement Technique for High Frequency Applications With IM3 Below -65dB,” IEEE Transactions on Circuits and Systems II Volume 51, Issue 10, Oct. 2004 Page(s):542 - 548
[23] Jose Silva-Martinez, Joseph Adut, Jose Miguel Rocha-Perez, Moises Robinson, and Shahriar Rokhsaz, “A 60-mW 200-MHz Continuous-Time Seventh-Order Linear Phase Fitler With On-Chip Automatic Tuning System,” IEEE Solid-State Circuits, IEEE Journal of Volume 38, Issue 2, Feb. 2003 Page(s):216 - 225
[24] Armin Tajalli, and S. Mojtaba Atarodi, “A Compact Biquadratic Gm-C Filter Structure For Low-Voltage and High Frequency Applications,” IEEE Circuits and Systems, 2003.
ISCAS '03. Proceedings of the 2003 International Symposium on Volume 1, 25-28 May 2003 Page(s):I-501 - I-504 vol.1
[25] Shiro Dosho, Takashi Morie, and Hirokuni Fujiyama, “A 200-MHz Seventh-Order Equiripple Continuous-Time Fitler by Design of Nonlinearity Suppression in 0.25-um CMOS Process,” IEEE Solid-State Circuits, IEEE Journal of Volume 37, Issue 5, May 2002 Page(s):559 - 565
[26] Giacomino Bollati, Stefano Marchese, Marco Demicheli, and Rinaldo Castello, “An Eighth-Order CMOS Low-Pass Filter with 30-120MHz Tuning Range and Programmable Boost,” IEEE Solid-State Circuits, IEEE Journal of Volume 36, Issue 7, July 2001 Page(s):1056 - 1066
[27] Adan Lopez-Martinez, Regina Antonio-Chavez, and Jose Silva-Martinez, “A Full CMOS 150 MHz OTA-C 7th Order Linear Phase Filter,” IEEE Low Power/Low Voltage Mixed-Signal Circuits and Systems, 2001. (DCAS-01). Proceedings of the IEEE 2nd Dallas CAS Workshop on 26 March 2001 Page(s):P11 - P14
[28] Xiaoqiang Shou, and Michael Green, “A Programmable VHF CMOS Read-Channel Continuous-Time Filter With On-Chip Tuning,” IEEE Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on Volume 1, 6-9 May 2001 Page(s):208 - 211 vol. 1
[29] Adan Lopez-Martinez, Regina Antonio-Chavez, and Jose Silva-Martinez, “A 150 MHz Continuous-Time Seventh Order 0.05 degree Equiripple Linear Phase Filter With Automatic Tuning System,” IEEE Circuits and Systems, 2001. ISCAS 2001. The 2001
[30] Shanthi Pavan, Yannis P. Tsividis, and Krishnaswamy Nagaraj, “Widely Programmable High-Frequency Continuous-Time Fitlers in Digital CMOS technology,” IEEE Solid-State Circuits, IEEE Journal of Volume 35, Issue 4, April 2000 Page(s):503 - 511
[31] Venu Gopinathan, Maurice Tarsia, and Davy Choi, “Design Consideration and Implementation of a Programmable High-Frequency Continuous-Time Filter and Variable-Gain Amplifier in Submicrometer CMOS,” IEEE Solid-State Circuits, IEEE Journal of Volume 34, Issue 12, Dec. 1999 Page(s):1698 - 1707
[32] Bruno Stefanelli, and Andreas Kaiser, “A 2-um CMOS Fifth-Order Low-Pass Continuous-Time Filter for Video-Frequency Applications,” IEEE Solid-State Circuits, IEEE Journal of Volume 28, Issue 7, July 1993 Page(s):713 - 718
[33] Hassan O.Elwan and Mohammed Ismail, “A Novel Digitally Controlled CMOS Current Follower For Low Voltage Low Power Applications,” IEEE Circuits and Systems, 1998.
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Volume 2, 31 May-3 June 1998 Page(s):335 - 338 vol.2
[34] Sang-Soo Lee, Rajesh H. Zele, David J. Allstot, Guojin Liang, “A CMOS Continuous-Time Current-Mode Filter Technique,” IEEE Circuits and Systems, 1992.
ISCAS '92. Proceedings., 1992 IEEE International Symposium on Volume 4, 3-6 May 1992 Page(s):2021 - 2024 vol.4
[35] Marki Kosunen, Kimmo Koli, Kari Halonen, “A 50MHZ 5th Order Elliptic LP-Filter Using Current Mode Gm-C Topology,” IEEE Circuits and Systems, 1998. ISCAS '98.
Proceedings of the 1998 IEEE International Symposium on Volume 1, 31 May-3 June 1998 Page(s):512 - 515 vol.1
[36] Armin Tajalli, Mojtaba Atarodi, “A 1.8-V Supply, 33-MHz Cut-off Frequency, gm-C Filter in 0.18-um CMOS Technology,” IEEE Microelectronics, The 14th International Conference on 2002 - ICM11-13 Dec. 2002 Page(s):50 - 53
[37] J. Glinianowicz, J. Jakusz, S.Szczepanski, and Y. Sun, “High-frequency two-input CMOS OTA for continuous-time filter applications,”, IEE Proceedings on Circuits, Devices and Systems Volume 147, Issue 1, Feb. 2000 Page(s):13 - 18
簡 歷
姓 名： 楊富昌
性 別： 男
籍 貫： 台灣省桃園縣
生 日： 西元 1981 年 4 月 24 日
地 址： 桃園縣龜山鄉忠孝街 37 巷 12 號 2F
學 歷： 國立交通大學電子研究所碩士班系統組 2003/09 ~ 2005/06
國立中央大學電機工程學系電子組 1999/09 ~ 2003/06
台灣省立武陵高中普通科 1996/09 ~ 1999/06
論文題目： A High Speed Fifth Order Gm-C Filter For Ultra-wideband Wireless Applications
適用於超寬頻無線通訊之高速五階轉導-電容濾波器設計