Electrostatic discharges (ESD) lies in I/O pins and using device to protect circuits form
high-voltage, high-current stresses. The stresses can cause reliability failure in short time and
the I/O circuitry of a chip would not work properly. ESD protection circuits provide low
resistance paths under high-voltage conditions to dissipate the energy in ESD pulses, while in
normal condition the ESD circuits would not function. The voltage limit the toleration of gate
oxide voltage is only about 5V in 0.18µm process. If there were not any ESD protection
circuits the gate oxide will be broken easily. Figure 5.9 shows the most popular ESD
protection circuits. Diode chain protection provides ESD path through VDD or GND, and a
large gate ground NMOS will break down once a large potential across the VDD and GND,
and induces the charge in VDD flows through NMOS to GND.
Figure 5.9 ESD protection circuits
The gate ground MOS shall prevent lightly-doped-drain which is common in deep
submicron process. The distance between drain contact and boundary of gate and diffusion
must be enlarged to sustain higher static charge. Contacts on guard ring are also avoided
because that makes the break down of ESD device harder. The ESD circuits provided by
UMC ensure 3.6kV in human body mode (HBM) test but induce about 40fF nonlinear
capacitance in each pad.
Figure 5.10 Simplified package model
Figure 5.10 shows the simplified package model for each pin. Each pin has a finite
self-inductance with 1-nH. Multiple bond wires and pins are used to decrease the equivalent
inductance and resistance on the VDD and ground pins. A large on-chip capacitor, which is
composed of four MIM capacitors in this chip, is used to stabilize the difference between
VDD and ground, and reduces the risk of inter-stage coupling. Electrostatic discharge (ESD)
may result in CMOS devices permanent damage without protection circuits.
Figure 5.11 Package pin assignment
Figure 5.11 is the QFN20 package pin assignment and the IC is packed by SPIL. The
chip is differential input / differential output. The un-label pads are not connected since the
lower part of chip is used as on-wafer test-key.
Fig 5.12 shows the PCB schematic design and we can see the bias path has two
capacitors connected to ground. Higher value capacitor is near power supply and lower value
is near the chip. The capacitors are using to filter out supply noise. Fig 5.13 shows the PCB
layout based on Figure 5.12 and the design is achieved by using Protel PCB. There are four
Metal layers for our PCB. The signal path has to put on top Metal and bias path can be put on
any layers.
Figure 5.12 PCB Schematic
Figure 5.13 PCB layout
For measuring the timing and frequency domain parameters, the equipments needed to
perform the measurement as listed below: Power Supply x 4, Spectrum Analyzer x 1,
Oscilloscope x 1, and ESG x1. The measurement plan is shown in Figure 5.14. There needs
two transformers for the purpose of converting differential to single end. The transformer
Ohm ration is 1:4. That is, the transformer can convert 200Ohm impedance to 50Ohm. So it
needs two 100 Ohm in series. Input signal uses AC couple while R1 can separate signal to
ground.
The oscilloscope is used to measure most of the static parameters. Such as output swing
and timing signal waveform. The spectrum analyzer is used to measure most of the frequency
domain parameters, like magnitude response, total harmonic distortion (THD), one db
compression point (P1db)
Figure 5.14 Measurement Plan
5.4 Measurement Result and Comparison
5.4.1 Magnitude Response
The magnitude response has 226 MHz bandwidth for -10dBm input as shown in Figure
5.15. The pass band gain is -4.07 dB with ±1.32 dB passband ripple. The additional loss
comes from transformer and transmission line. The chip consumes 24 mA, that is, the power
dissipation is 43.2mW. The difference is due the device variation since the Gm cells and
capacitors are designed small in favor of high frequency application.
(a) Measurement Result
(b)Post-Simulation Result 1dB/
205 210 215 220 225 230 235 240 245
1 2 3 4 5 6 7 8 9 10 11 12
Cutoff frequency (MHz)
Figure 5.16 Cutoff frequency measurement results
Figure 5.16 shows the cutoff frequency measurement results. The filter cutoff frequency
depends on capacitance will vary in magnitude response. Although the minimum node
capacitance has been chosen as 0.4pf, the layout parasitic capacitance which comes from the
metal line is about 0.15pf. Then the MIM capacitance is only about 0.25pf which the variation
will become more serious. The average value of cutoff frequency is about 225MHz.
The magnitude response with low frequency is shown as Figure 5.17. Since the ESG
generates signal as low as 250 kHz. The magnitude response ranges from 250 kHz to 20 MHz.
The input signal is AC couple through a RC which sets frequency at 120 kHz, so the
magnitude will have little loss at 250 kHz.
Figure 5.17 magnitude response with -10dBm input (250 kHz ~ 20MHz)
5.4.2 Harmonic Distortion
Post Layout Simulation Result:
Figure 5.18 Spectrum and transient response with 0.4Vpeak input at 20MHz
Figure 5.19 Spectrum and transient response with 0.4Vpeak input at 200MHz
Measured Result:
Figure 5.20 Measured spectrum and transient response with 0.4Vpeak input at 200MHz
Figure 5.21 Measured spectrum and transient response with 0.4Vpeak input at 200MHz
The simulation input signal is 0.4Vpeak, the input signal is chosen as 3dBm after
canceling the input transformer loss. Summarize from Figure 5.18 to Figure 5.21 the
harmonic distortion analysis be listed as Table 5.4.
Figure 5.18 Figure 5.19 Figure 5.20 Figure 5.21
Total Harmonic distortion -33.27dB -41.06bB -23.38dB -41.28dB
Output swing (Vp-p) 554 mV 430 mV 334 mV 279 mV
Table 5.4 Harmonic Distortion Analysis
Since differential to single end needs output transformer which has loss about 3dB, the
measured output swing is less than post layout simulation.
5.4.3 One dB compression point
The one dB compression point (P1dB) shows in Figure 5.22. (a) and (b) are input P1dB at
20MHz and 200MHz. Their values are 1.5 dBm and -1.1 dBm respectively.
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
-35 -30 -25 -20 -15 -10 -5 0
Input signal
Output signal
(a) P1dB @ 20MHz input
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
-35 -30 -25 -20 -15 -10 -5 0
Input signal
Output signal
(b) P1dB @ 200MHz input
Figure5.22 One dB compression point (P1dB)
5.4.4 Comparison
Table 5.5 is the comparison of filter with measurement, specification and post-sim. The
3dB frequency and pass band ripple do not meet specification. The reason is process variation
and mismatch.
Parameters Specification Post-Simulation Measurement
3dB frequency 245MHz 248 MHz 226 MHz
loss @ 260、、、300MHz 、 -12dB, -20dB -12.1dB , -36.9dB -15.5dB , <40dB
Power dissipation 30mW 32.25mW 43.2mW
Pass band ripple 1dB 0.92dB 1.32dB
Table 5.5 Filter comparison with specification
In order to compare many filters with the same FOM, the Dynamic Range can be
obtained by P1dB as (5.3):
(5.3)
The Pmdos is minimum detectable output power (dBm) and is defined as:
Ga(dB) X(dB)
NF 10log(BW)
Po
P
mdos= + + + +
(5.4)Where Po =Noise floor = -174dBm/MHz BW = Device Operating bandwidth (Hz) NF = Device Noise figure (dB)
X = 3dB typically
mdos
dB
P
P
R =
1−
D
Figure5.23 Noise figure analysis
Figure 5.23 is noise figure analysis, the noise figure is 32.292dB with -5.818
passband gain. Then the dynamic range can be calculated:
Take (5.2) to calculate FOM, the filter comparisons with measurement can be list as
Table 5.6.
Technique Bandwidth Topology Power DR(dB) VDD FOM(dB)
This work 0.18μm 226MHz 5th elliptic 43.2mW 58.14dB 1.8V 61.55dB
[6] 0.18μm 1GHz 5th elliptic 90mW 64dB 1.8V 55.35dB
[4] 0.8μm 60MHz 3rd elliptic 12mW 57dB 2.7V 64.54dB
[5]-1 0.5μm 29.6MHz 3rd elliptic 39.9mW 76dB 5V 63.28dB
[5]-2 0.5μm 29.9MHz 3rd elliptic 46.2mW 77dB 5V 63.42dB
Table 5.6 Filter comparisons with measurement
58.138dB
07 . 4 3 292 . 32 54 . 83 174 1
. 1
D
1=
+
−
−
− +
−
=
−
= P
dBP
mdosR
Chapter 6
Conclusion and Future Work
This thesis has presented a high linear transconductor employing negative impedance
load for high frequency UWB LPF. It has enabled the implementation of a 226 MHz high
speed LPF in a 0.18μm CMOS technology. This topology has been applied to the analog
front-end for the UWB direct conversion receiver & transmitter which perform high speed,
high linearity and wide bandwidth. In conclusion, the key contributions presented in previous
chapters are summarized below.
6.1 Conclusion
A high linear transconductor employing negative impedance load for high frequency
UWB LPF has been presented in Chapter 3 & Chapter 4. These techniques improve the
linearity and improve the harmonic distortion. Using negative impedance load makes the filter
suitable for high frequency. The LPF circuit implemented in 0.18-µm CMOS process shows a
band ripple of ±1.32dB while drawing 43.2 mW from a 1.8-V supply. If for a SOC
application, the buffer is not needed to drive an ADC and the power consumption will be
about 36.2mW from a 1.8-V supply. Compare the filter with other spec. in Chapter 5. This
topology is applied to the RF front-end design for the UWB direct conversion transceiver.
6.2 Recommendations for Future Work
To increase the accuracy of this filter, the quality tuning and frequency tuning circuit can
be combined in the filter [15] [16] [17]. In the VCO tuning loop both frequency and quality
factors can be tuned. The VCO consists of two integrators and its frequency and quality factor
can be controlled. Figure 6.1 shows the Master-Slave frequency tuning technique by PLL.
The circuit generates the control voltage (Vtune) which makes the frequency of VCO based
on Gm-C gyrator is equal to the reference frequency. By this control voltage, the cutoff
frequency of the filter can be set to the desired value. A quality factor adjustment circuit is
also designed to compensate for the parasitic resistance shown in Figure 6.2.
There are three cases for the Q-tuning loop:
(a)If the integrators of the VCO have phase lead at the oscillating frequency ωo
(1/Qint(ωo) >0 ), the poles of the VCO are in the left complex half-plane. The VCO output is
a sine wave with exponentially decreasing amplitude.
(b) If the integrators of the VCO have phase lag at ωo (1/Qint(ωo) <0 ), the poles of the
VCO are in the right complex half-plane. The VCO output is a sine wave with exponentially
increasing amplitude.
(c) Finally if the integrators of the VCO have no phase error at ωo (1/Qint(ωo) = 0 ), the
poles of the VCO are in jω axis. The VCO output is a sine wave with constant amplitude.
The Q-tuning loop controls the mplitude of the VCO in a way that it will oscillate with a
constant amplitude at infinite Qint(ωo).
Figure 6.1 Frequency tuning technique
Figure 6.2 Quality tuning technique
The other way to reduce the transconductance variation due to threshold-voltage
variation is to use a threshold-voltage compensation circuit [18]. Figure 6.3 shows a
conventional current source with threshold voltage compensation. Neglect the channel length
modulation, the current source I2 can be expressed as:
Then the current source is varied with the difference between Vtc1 and Vt2 rather than Vt2.
If the transistors MC1 and M2 are locally matched, the current I2 is independent of the
threshold voltages.
Figure 6.3 bias circuit using threshold compensation technique
50 100 150 200 250 300 350 400 450
Figure 6.4 the filter magnitude response with four transistor corner cases
50 100 150 200 250 300 350 400 450
0 500
-70 -60 -50 -40 -30 -20 -10 0
-80 10
Frequency (MHz)
Magnitude (dB)
SS SF FS
FF
Figure 6.5 after adding voltage threshold compensation biasing circuit
If we consider the four transistor corner cases the cutoff frequency will vary from
200MHz (SS) to 270MHz (FF) as shown in Figure 6.4. After adding voltage threshold
compensation biasing circuit, the SF & FS cases will be restrained in Figure 6.5. The
implementation of this bias skill or other tuning networks will be in the Future works.
The LC ladder topology can be used as broadband matching. The original method of LC
ladder filter depends on the input / output impedance as shown in Figure 6.6. The synthesis
steps are to match input impedance to output impedance. If the LC filter load impedance is the
circuit input like Distributed Amplifier (DA), the difference of is that the DA input impedance
would change with frequency. The principle of broadband matching can make the DA input
equal to source impedance with a wide frequency range. The theory of broadband matching
may not suit for receiver for the lack of NF optimization and detail analysis can be found in
(a)General filter (b)Broadband matching Figure 6.6 LC ladder can be used to match complex load
For high frequency applications, all the Gm blocks have to be implemented with high
output impedance and high quality factor. Since the negative impedance load can increase
differential gain and make common mode gain less than one, besides it doesn’t cost additional
power. If the Gm block have RHP-zero about one hundred times higher than the most high
frequency pole or zero, adding negative impedance to other Gm is suitable for high frequency
filter.
Appendix A
Symmetric & Un-symmetric Differential Pair
The cross-coupled quad cell can be shown in Figure A.1. Assume all the MOSFET are in
the saturation region and neglect body effect. The square-law function can be characterized
as:
)2
( GS th
D k V V
I = − (A.1)
Figure A.1Cross-coupled quad cell
Neglect channel length modulation and second-order effects in this analysis, the pair M1
and M2 in Figure A.1 can has relation as:
vn M1
vp
M2
(n+1)I
M3 M4
(n+1)I (n+1)I-i
k nk k nk
(n+1)I+i
I+i1 nI-i1
I-i2 nI+i2
nk
After some arrangements for (A.2):
n
(A.4) can be obtained:
( ) ( )
After calculating (A.5):
[ ]
For the same reason, we can deduce that:
If the input signal level increases, M1 will first enter into cut-off region, that is,
n
The input signal level continues to increase, M2 will also cut-off.
( ) ( )
From the above analysis, we can calculate the bounded value of y1 and y2 as following
shows.
Having (A.12) we can determine large-signal transconductance characteristic gm12 by
straight forward differentiation.
adding and subtracting output currents in input stage, approximate cancellation of the
remaining nonlinearities can be obtained.
Figure A.2 Symmetric & un-symmetric differential pair
vn vn vn
(n+1)I (2d)I (n+1)I
(n+d+1)I (n+d+1)I
I nI nI I
gon gop
k nk pk pk nk k
VDD
The calculation can be easily to obtain the normalized transfer function yd of
symmetrical differential pair, which is listed below:
Determine the normalized transconductance characteristic gmd from yd :
equation (A.13) and (A.15), gm is fully determined by the three parameters: n, d and p. Thus,
we can impose three conditions upon the characteristics gm12 and gmd in order to determine
uniquely the values of n, d and p.
According to the normalized transfer characteristic, we have the following assumptions
[5]:
1. The value of parameter n has to be chosen in such a way that gm12 is constant in the right neighborhood of x=[(n+1)/n]0.5
2. The values of d and p have to be chosen in such a way that gmd(x) vanished exactly for x=
±[(n+1)/n]0.5
3. The values of d and p have to be chosen in such a way that gmd(0) = gm12(0) - gm12([(n+1)/n]0.5).
From the three assumptions, we can uniquely determining the values of n, p and d as
shown in table A.1.
Table A.1 OTA design parameters
n p d
4.236 1.288 0.796
Appendix B
LC Ladder analysis
WhereY2,4 =sC1,2 , 6 1 5
out
calculate (a):
calculate (b):
Ro
calculate (c):
Ro
calculate (d):
Ro
Add (a) ~ (b):
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