3.3 Linearization Techniques for gm cells
3.3.1 Source degeneration
(a) Source degeneration (b) Saturated transistor Figure3.3 Source degeneration technique
In Figure3.3 (a), the degeneration resistance can be changed dynamically with the input
signal amplitude. Qualitatively, when the amplitude of the input signal rises, the triode-mode
degeneration MOS resistors will be more biased to reduce the synthesized resistance and
provide less degeneration. The gm reduction from larger input signal is therefore compensated
by the degeneration resistance adjustment. The transconductance relationship is expressed as
) 4 / (
1
1 31
K K
g
mg
m= +
(3.13) where K is 0.5µnCoxW/LThe other technique using saturated transistor as degeneration resistor shown in Figure
3.3(b), the equivalent gm is [11]:
1 2 1
/
1
m mm
m
g g
g g
= +
(3.14) The rise of gm then compensates for the drop of gm expressed in Eq. (3.5). However, the
compensation is not adaptive. Therefore it is suitable when the range of tolerance of gm is
relatively large.
3.3.2 Active biasing
(a) (b) Figure3.4 Adaptive bias degeneration[12]
From (3.4) & (3.5), the nonlinear characteristic of differential pairs is observed to come
from the expression id I
K V 1 2
2
− . This term can be cancelled by canceling the Vid term in the
expression. The method is to make the biasing current compensation for the non-linear term:
2
2 id DC
ss
KV I
I = + (3.15) where IDC is the DC bias current.
Now the bias Iss supplies IDC when Vid = 0 for the static bias. When there is a signal, an
additional bias current KVid2/2 will compensate for the drop of the gm. This can be verified by
inserting the new Iss into Eq. (3.3):
DC t
gs D
D I K V V I
I 1 + 2 =2 ( − )2 = (3.16) As a result, a constant gm is obtained because Vgs-Vt of each input transistor is constant.
One of the designs is shown in Fig. 3.4(a).
In this design, all transistors are matched except M5-M8. For this cascoded circuit, when
there is an input signal, the same amplitude appears at the drains of M1 and M2 because the
loading is 1/gm3,4 and gm3,4=gm1,2. Here, ro1,2 >> 1/gm1,2 is assumed and the capacitance at that
node and the loss of the level shifter M5-M8 are ignored. Both gates of Mb1 and Mb2 sense the
differential voltage. Because the drains of Mb1 and Mb2 are connected together, a bias current is
obtained as in (3.2) and (3.15). The required active biasing is then established.
When the gm cell is used for high frequency applications, say 250 MHz, the capacitance
effect at the drains of M1 and M2 and the sources of M5 and M6 will reduce the effective signal
increase the voltage gain of M1 and M2. This ensures that the KVid 2/2 is enough to compensate
for the non-linearity.
The same linearization effect can be achieved by connecting the gates of Mb1 and Mb2 to
the 2 inputs respectively. But in the common-mode sense, now the conductance of Mb1 and
Mb2 increases in phase with the input signal. This is a kind of feed-forward and thus causes a
boost-up of the common-mode gain. As a result, CMRR drops and common-mode instability
will be resulted.
There is a modified design that can operate at a lower supply voltage. The schematic is
shown in Fig. 3.4(b). Instead of controlling the gate bias of the bias transistor Mb, a differential
pair M3-M6 acts as a bias current. Both pairs share the same bias current source.
When the signal amplitude is small, M3 and M4 are in saturation region while M5 and M6
are in triode region. M3-M6 drain out some of the bias current. When the signal amplitude is
positive and large, M6 will go into saturation region and M5 will be cut off. Smaller sum of the
bias current will be drained out by M3-M6. That means more current will be supplied to M1
and M2 to compensate for the drop of gm. As a result, an active biasing is achieved.
3.3.3 Cross-coupling
Figure3.5 Cross-coupling gm cell
A simple differential pair can cancel out the even order harmonics of distortion of Io. The
remaining odd order harmonics can be cancelled out by cross coupling 2 differential pairs
with the same distortion but with different gm values. The circuit is shown in Figure 3.5.
The 3rd order harmonic is the main concern since it is now the most significant distortion.
From Eq. (3.5), the 3rd order harmonic distortion (HD3) of Io can be obtained as:
2 3 3
3 2 2 ss Vid
I
HD = K (3.17)
Since HD3 depends on the ratio of K3/2and Iss1/2only, the distortion can be cancelled by
connecting 2 differential pairs in parallel with different gm but with the same distortion. K3,4
and K1,2 are related to Iss2 and Iss1 as follows:
vn M1
vp
M2
Iss1
M3 M4
Iss2 ID1-ID4 ID2-ID3
1
The corresponding effective gm is then given by:
]
But the non-linearity cancellation is not complete due to the difference in second order
parameters such as the mobility between the 2 differential pairs. The incomplete cancellation
is more significant when Iss2 << Iss1 though more extra power consumption due to Iss2 is saved.
The perfect cancellation happens when Iss2 approaches Iss1. Yet the resultant gm also tends to
zero. There is also a problem of the smaller CMRR. The reason is that the differential gain is
reduced by M3 and M4 whereas the common-mode gain is enhanced. This can be a serious
problem for the common-mode stability if the gm cell is used to construct gyrators for Gm-C
low pass filters. Another disadvantage is the additional noise of M3 and M4. The factor of the noise to a simple differential pair is[1 ( )3]
linear gm is required because the gm is obtained from the cancellation of 2 relatively large gm’s.
3.3.4 Unbalance differential pairs
Figure3.6 Unbalance differential pairs
Two differential pairs with a symmetrical but opposite-signed input offset voltage can
compensate for the drop of the gm of each other so that a flat gm can be obtained at a certain
offset. The schematic and the basic operation principle are shown respectively in Figure 3.6
In the schematic, K1=K2 and K3=K4. The differential pairs M1,4 and M2,3 have symmetrical offset voltage because the sizes of the transistors are different in each differential pair. To find
the offset voltage, the point where Id1=Id4 and Id2 = Id3 has to be found:
2 4
, 3 2 2
, 1 4 , 3 2 ,
1 d ( gs t offset) ( gs t offset)
d I K V V V K V V V
I = ⇒ − − = − +
) (
4 , 3 2
, 1
4 , 3 2
, 1
t gs
offset V V
K K
K
V K −
+
= −
⇒
(3.20)
If the non-linear gm expression of (3.5) is included, the compensation is not complete due
to the squared term:
vn M1
vp
M2
Iss1
M3 M4
Iss2
ID1+ID3 ID2+ID4
]
3.3.5 Symmetric and un-symmetric differential pairs
Figure3.7 Symmetric & un-symmetric pairs
The linearity technique can combine two skills in order to further improver its linearity. If
we use cross-coupling and unbalance differential pairs together, then the gm core is called
“Symmetric & Un-symmetric differential pairs” [5].
Figure.3.7 shows the proposed Gm by using symmetrical & unsymmetrical differential
pair with negative impedance. NMOS M5&M1, M2&M6 have unsymmetrical aspect ratio n,
and symmetrical pair M3&M4 makes gm as flat as possible. The transistors and current have
different ratios:
vn vn vn
(n+1)I (2d)I (n+1)I
(n+d+1)I (n+d+1)I
I nI nI I
gon gop
k nk pk pk nk k
VDD
p n M
M M M
M
M 1 : 2 : 3 = 6 : 5 : 4 = 1 : :
(3.22)The detail analysis of this gm core can be seen in Appendix A.
The gm can be obtained [5]:
k I n
n n n
gmd n
) 1 (
1 )
1 (
4
+
−
= + (3.23)
where n is aspect ratio , I is normalized current, and
L CoxW
k µ
2
= 1 .
By choosing appropriate transistor ratio n, p, and d, the range of flat gm:
k I n
vid ( +n 1)
≤ (3.24)
Above linearity technique can be summarized as Table 3.1 and the advantage and
disadvantage of gm cells will list in it [15]:
Linearization types Advantages Disadvantages Degeneration of Figure 3.3(a) 1.Simple and Fast
2.Low sensitive to common mode input signals
1.Linear range is limited to Vin<VDSAT
2.Not effective Degeneration of Figure 3.3(b) 1.Wider linear range than (a)
2.Low sensitive to common mode input signals
1.More silicon area 2.Low power efficiency
Adaptive Bias 1.Small gm variation over a wide range
1.Need good matching for biasing transistors Cross Coupling 1.Better power efficiency
than source degeneration.
2.Small gm variation over a wide range
1.The transconductance is very small
Unbalance differential pair 1.Good power efficiency 2.Good CMRR
1. Small gm variation for a limited range only.
Symmetric & Un-symmetric differential pair
1.Suitable for high frequency 2.Highly linear Gm
Symmetric pair wastes power
Table 3-1 Table of comparisons of various gm cells
3.4 High Output Impedance Techniques for gm cells
To improve the gyrator quality factor, the gm integrator must have high DC gain with
desired gm value. That is, the gm needs high output impedance. There are two techniques
implemented to increase that. First technique is to cascade high Rout element [5]. And second
one is to use negative impdeace load (NRL)[3].
3.4.1 Cascade High Rout Element
Figure 3.8 Cascoded 2nd stage to improve Rout
The high gm output impedance need cascoded MOS structure as gm load. For some
linearity technique needs more voltage headroom, it is not suitable in deep sub-micron era.
Some papers “separate linearity and high Rout” as shown in Figure 3.8. Although it can
release the problem, the 2nd stage amplifier needs addition power and cascade reduces output
swing so it’s not a good solution. The best solution requires only one linear gm and has high
differential gm & low common mode gain. It will be shown in next section.
3.4.2 Negative Impedance Load (NRL)
Figure3.9 Negative Impedance Load
Linear Gm 1st stage
Gm +
-Amp
Cascode amplifier 2nd stage
VDD
M1 M3 bias M4 M2
In Im
-
+m n
Consider the NRL in Figure 3.9. M3 & M4 introduce local positive feedback between
the output terminals m & n which generate a negative resistance to compensate the parasitic
output resistance of the whole transconductance circuit. A bias voltage connects to the
substrate of M3 & M4 in order to control the threshold voltage. This is a simple way to
control the NRL without generating extra internal node. The voltage of bias has to be
carefully limited in several hundreds milli-volts in order to prevent from latch-up.
Applying again the square-law characteristic for devices M1-M4 and (3.6), the current
differential output voltage, and kp=0.5µpCoxW/L is the transconductance parameter.
The negative impedance is:
]
The negative impedance load can be combined with all the differential gm to increasing
their output impedance as shown in Figure 3.10. In (a) the output impedance is 1/(go1+go2).
If the NRL is used in (b) and design go3 = - go4, then the output impedance is infinite
(ideally). The advantage of NRL is that it only needs to bias at same current string, so it saves
power.
(a) without NRL (b) with NRL Figure3.10 Gm core with/without NRL
3.5 Symmetric & un-symmetric pairs with NRL
HF filter needs poles & zeros at higher frequency. So there has some trade-off between
gm and capacitance. Because poles and gm-divide-C have direct proportion, gm value can
design at a small value while capacitance also is small to maintain original pole vale. But
small capacitance value means worse process variation. If we choose higher gm value, the
power dissipation can not match stringent specification for UWB system.
Several high frequency CMOS Gm-C filters are introduced inverter type gm to achieve
minimum node and implemented negative impedance. Nevertheless the linearity is limited
power by connecting negative impedance in parallel with the output nodes of the basic Gm [3].
Because of avoiding the use of stacked devices, the Gm proposed in [4] is very suitable in low
supply voltage. But in deep submicron technology, there still needs high linearity skill to fix
serious linearity problems. In this thesis, a symmetrical & un- symmetrical differential pair
with negative impedance is introduced and a high frequency low power elliptic filter for
UWB applications can be achieved.
.
Figure3.11 Symmetric & un-symmetric with NRL
The symmetric & un-symmetric differential pair with NRL is shown in Figure 3.11.
PMOS M11&M12 work as negative impedance load. The output impedance can be controlled
by tuning body potential vb1 of M11&M12.
vn vn vn
VDD
vb2 vb2 vb2
vb1
M1 M2 M4 M3 M5 M6
M7 M9 M8
M10 M11 M12 M13
vp vp
vp
outn outp
(n+1)I (2d)I (n+1)I
(n+d+1)I (n+d+1)I
I nI nI I
gon gop
k nk pk pk nk k
The Gm differential and common mode gain can be shown [4]:
right-half-plane zero. Even so, a gyrator based filter built with Gm blocks will remain stable.
This is owing to the feedback loops inherent to a filter constructed with gyrators. It will be
analyzed in chapter 4 and the result shows that the RHP zero doesn’t matter if negative
impedance is not too “negative”.
Figure3.12 non-ideal Gm-C integrator
The Gm and capacitor can be connected as integrator, for integrator is the basic
element in all the filters. If the Gm non-ideal effect like finite RHP-zero and finite output
C 1/go
V
inV
outgm*(1-sτ)
Figure 3.13. The frequency with phase at -45o is the f3db for integrator and -135o is Gm
RHP-zero, respectively. The -90o phase shift region is between two frequencies.
(a) Magnitude
response
(b) Phase
response Figure 3.13 Frequency of non-ideal Gm-C integrator
The Quality factor for the integrator is shown in (3.28)
))) (
arg(
tan(
)
(
intint
ω H j ω
Q = −
(3.28)
From (3.27) and (3.28), the expression for quality factor of the proposed symmetric &
un- symmetric Gm integrator is:
gm
md
T
g o gm
g
Q ω τ
ω ω
ω = ⋅ ( ′ − ∆ ) − ⋅ )
( 1
int
(3.29)
where ωT is Gm integrator unit-gain frequency, and τgm is the Gm RHP-zero. For 250MHz filter, the 1/τgm will be far in 25GHz in order to have acceptable quality factor. This limits
the linearity topology. The principle for Gm integrator can be applied to Gm-C filter.
Chapter 4
Filter Analysis & Implementation
The filter topology will be analyzed in this chapter. Some topologies exhibit excellent performance and are suitable for high frequenccy. The topology of passive elliptic
LC ladder filter is introduced in Section 4.1. Section 4.2 shows the element replacement to
implement high frequency filter in CMOS process. The sensitivity property will be in Section
4.3.
4.1 LC ladder filter
(a) (b)
Figure 4.1 the 5th elliptic LC ladder
There are two possible topologies to implement the 5th order elliptic filter by LC ladder
structure. The zeros are generated by the LC tanks at their resonant frequencies. One LC tank
generates two complementary zeros. The parallel LC tank forms an “open circuit” which cuts
off the input-output path at the tank’s resonant frequency. On the other hand, the serial LC
tank forms a ”short circuit” at resonant frequency (zeros) as shown in Figure 4.1. The parallel
LC tank topology is preferred owing to less inductor, therefore less gyrators are used. There
are four Gms for a gyrator, so Figure 4.1(b) is power wasting topology. Moreover, serial LC
tank topology does not have desired capacitance to ground in all the nodes and will distort
frequency response. If the LC tank is lossless, there will be a very high Q zero. In the CMOS
process, the on-chip inductors have serious parasitic effect and the resistance variation is
serious. The LC ladder can’t be implemented by simply putting some RLC components,
especially when the circuit is used for high frequency application. The LC ladder filter has
good sensitivity property. In previous chapter, the transconductor is introduced in the form of
inductors or resistances. The detail transfer function of 5th elliptic LC ladder filter is analyzed
in Appendix A.
4.2 LC Gm-C filter
As mentioned above, the variation of on-chip resistors is critical. And passive inductor
has parasitic resistance which can’t achieve a high Q and high frequency zeros in the CMOS
process. Since these restrictions are serious, the passive element must be replaced by analog
circuits. Although circuits need power to boost and have worse linearity, there are many
circuit technique to increasing linearity in last chapter. Figure 4.2 & 4.3 show the common
Figure 4.2 Differential Gm connected as resistance
Figure 4.3 Differential Gm connected as inductance by gyrator approach
The Gm block has non-ideal effects which are finite output impedance and RHP-zero.
When Gm is connected as passive element, it will add parasitic components as shown in
Figure 4.4 and 4.5. In order to reduce go and increase τ, the Gm should be design by a simple
structure with some circuit to increase Rout.
Figure 4.4 resistor implemented by non-ideal Gm with finite 1/go and RHP-zero
(a) (b)
Figure 4.5 Inductor implemented by non-ideal Gm with finite (a) Rout (b) RHP-zero
The gyrator using integrator has -90o phase shift, but in chapter 3 the integrator shows
very poor behavior at low and high frequency. That is, the phase of the integrator is very far
from being -90o for frequency f <<fint3db and f >>fRHP_zero. We can analyze simple gyrator
shown in Figure 4.6. From (4.1) we can draw Rin V.S. frequency plot. The curve has two
corners which point to Gm fint3db and fGmBW, respectively. When signal frequency is low (f
<<fint3db), the gyrator acts as resistor with the value depends on Rout of the Gm. Even at DC
frequency, the resistor only causes little loss without changing response. But when signal
frequency is high (f >>fRHP_zero ), it does not matter whether the phase of the integrator is still
-90 o or not : the capacitors connected to the filter nodes will short circuit them because their
impedance goes to zero, whether the integrator performs well or poorly, and we will get the
typical attenuation of the signal at high frequencies.
Figure 4.6 Non-ideal Gm effects the inductor
Another question will rise if the Gm output impedance is too “negative” and the Gm will
have the right-half-plane zero. For a stand-alone integrator, it could become unstable. Even so,
a gyrator built with Gm blocks will remain stable. This is owing to the feedback loops
inherent to a filter constructed with gyrators as shown in Figure 4.7. It can be found that
gyrator based inductor input impedance Rin is negative at zero frequency. But when the
inductor lies in LC ladder filter, the filter response at DC will be stable due to the input/output
impedance of the filter shown in Figure 4.8. That is the Gm could be designed at negative
output impedance which is not too far from zero.
(4.1)
gm*
(1-s ) -1/go C -1/go
Vx Ix
-gm*
(1-s )
Figure 4.7 Negative impedance at DC frequency
Figure 4.8 LC ladder low frequency gain with negative impedance
After element replacement, the filter has changed from Figure 4.1 to Figure 4.9. Input
current source is made by Gm for its high input resistance. Grounded resistance is replaced by
circuit shown in Figure 4.2. The floating inductor is made of at least four Gm. The circuit has
to connect output buffer in order to load high capacitance measure equipment. The simple
common source follower can be used as a buffer design for its excellent frequency response.
0
) ( ) ) (
0 (
>
+
− +
−
= +
L b
a S
L
R R R
R H R
Figure 4.9 the 5th elliptic ladder filter using Gm-C technique
The internal nodes gain may be a serious problem since it could be higher than output
gain. And for UWB receiver, the filter is the last element in receiver path. The filter input
swing is very large. If the internal node swing is higher than output swing, the Gm blocks
may saturate and reduce dynamic range. The reason of internal node peaking is that it is band
pass transform function in Figure 4.10(b). The analysis is assumed using 3rd elliptic Gm-C
filter with ideal Gm and filter has the same input/output impedance. Since the most serious
internal node peaking comes from the two capacitors of gyrator circuits, there must have some
adjustment. In Figure 4.10 (a), the X & Y are defined by the connection with internal
capacitor. The output of X and the input of Y connect with the internal capacitor. For a
desired inductor value with minimum power and acceptable process variation, the internal
capacitor can be chosen as 0.4pf. Then the product of X and Y is known as 4gm2 and the gm
is the transconductance of unit Gm since this can relax the design complexity and variation.
Figure 4.10(b) is the internal nodes magnitude response when X = Y = 2gm. We can see Vb
has magnitude about 3 times larger than Va in the pass band and this ratio is decided by X &
Y. Consider all the information, the X/Y ratio can be found as 1/4 in Figure 4.10(c). After
adjustment, the result can be shown in Figure 4.11 and we can see all the internal response is
less than one except a little higher in the pass band edge.
less than one except a little higher in the pass band edge.