Conductance Method

Methods of quantifying D_it, the trap level energy position and the degree of Fermi level (un)pinning are important in the development of high quality interface between high-κ dielectric and III-V materials [41-43]. It is often impractical to fabricate MOSFET for III-V devices because the transistor fabrication process may introduce other issues. Therefore, MOSCAP structures are commonly used to study the dielectric/substrate interface, dating back to 1960s. The conductance method including the effects of the energy distribution of interface states in the bandgap and surface potential fluctuation (SPF), which has been established by Nicollian and Geotzberger, is a powerful and sensitive tool to determine Dit. Fig 2.22 (a) shows that a n-type MOSCAP applies to a small amplitude (~25 mV) ac signal with frequency f (typically between 1 MHz and 100Hz) superimposing on a dc gate bias, V_g. Also shown are the conduction and valence band DOS, Ddos, an arbitrary interface states density distribution, the Fermi level EF and the intrinsic level EI. Fig. 2.22 (a) assumes that the band diagram of this MOSCAP is in depletion region. The gate voltage, inducing a space charge and band bending,ψ_s ,determines the Fermi level position at the interface. A periodic change in ψs is caused by the ac small signal and the Fermi level at the interface oscillates around the energy level position determined by the dc gate bias. Only traps with energy levels that are near the Fermi level are able to change their occupancy. An equivalent circuit model for a MOSCAP with interface states in depletion region, including the gate oxide capacitance, Cox, the

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semiconductor capacitance, C_dos(ω,ψ_s), interface trap capacitance, C_it(ω,ψ_s), equivalent parallel conductance, Gp(ω,ψs) and a series resistance, Rs, is shown in Fig.

2.22 (b). The circuit model shown in Fig. 2.22 (b) assumes that the minority carrier response is negligible. Fig. 2.22 (c) shows the equivalent circuit of impedance analyzer with the measured capacitance, C_m, and conductance, G_m. The frequency dependence is related to the characteristic trap response time,



  ² ,

where ω is the angular frequency,

f

2 (f=measurement frequency)

The interface trap capacitance is related to the interface states density by

it

it q D

C  ² ,

where q is the elemental charge

The trap response time for electron or hole is given by Shockley-Read-Hall statistics of capture and emission rate:

 

The conductance method is based on analyzing the loss that is caused by the change in the trap level charge state. G_p/ω is given in terms of the measured capacitance, Cm, the oxide capacitance, Cox, and the measured conductance, Gm, by comparison the circuit of Fig. 2.22 (b) and Fig. 2.22 (c), shown as follows:

24 account and the normalized conductance is shown as follows:

 

Maximum loss occurs when interface traps are in resonance with the applied ac signal.

For Eq. (2.3) we find applying Eq. (2.5). Fig. 2.23 (a) (b) show trap level position calculated from Eq. (2.3) using the values for the average thermal velocity and the band DOS for In_0.53Ga_0.47As and a capture cross section σ = 1×10^-17 cm². The characteristics trap frequency as a

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windows at given temperature and the limited range of typical measurement frequency.

2.5.1 Comparison between FGA and PMA

Fig. 2.24 (a) (b) and Fig. 2.25 (a) (b) show conductance maps of Al₂O₃/TMA-treated In_0.53Ga_0.47As MOSCAPs with FGA or with PMA, on both p- and n-type (100)-oriented In0.53Ga0.47As, respectively, at temperature 300K. These maps show the magnitude of normalized parallel conductance (G_p/ω)/Aq as a function of ac frequency f and the gate voltage VG. The Dit is estimated by multiplying the peak value, [(Gp/ω)/Aq]max, with a factor of 2.5[see Eq. 2.6]. In Fig. 2.24 (b), there is a remarkable response appearing at VG= -2 volts and frequency between 1 kHz and 100 Hz. We speculate that this response might be slow traps or border traps [section 2.3.2].

The samples with FGA, shown in Fig. 2.24 (a), don’t show the response at the same region, which indicates H₂ annealing is able to passivate these slow traps and reduces the frequency dispersion in accumulation. For n-type MOSCAPs, we also observe that the slow traps are effectively passivated by hydrogen annealing and lower interface states exist in the samples with FGA [Fig. 2.25(a)].

Fig. 2.26 (a) (b) and Fig. 2.27 (a) (b) show the parallel conductance curves of Al2O3/TMA-treated In0.53Ga0.47As MOSCAPs with FGA or with PMA, on both p- and n-type (100)-oriented In0.53Ga0.47As, respectively, at temperature 300K by using Eq.

2.4. The G_p/ω-f curves from V_G= -1 to 1 volt for p-type and V_G= 0.5 to -1.5 volts for n-type are demonstrated here, and D_it can be obtained by multiplying peak value with a factor of 2.5. It is clearly known that MOSCAPs with FGA have lower interface states than MOSCAPs with PMA. According to Eq. 2.3, the frequency corresponding

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to peak value can transfer to trap position in band gap; consequently, D_it profiles can be done by the conductance method. The Dit profiles of MOSCAPs with FGA and with PMA are shown in Fig. 2.28 (a) (b), assuming the capture cross section to be 10^-17 cm². We can only observe the interface states near midgap because of material properties and measurement temperature (300K). This result corresponds to our previous graph, Fig 2.23 (a) (b). It is noted that the interface states near midgap can be reduced slightly about 22.28% (E_t= 0.428 eV) by hydrogen annealing,

2.5.2 MOSCAPs with FGA under Various PDA Conditions

Fig. 2.29 (a) (b) (c) and Fig. 2.30. (a) (b) (c) show parallel conductance maps of Al₂O₃/TMA-treated In_0.53Ga_0.47As MOSCAPs with FGA under different PDA conditions, on both p- and n-type (100)-oriented In0.53Ga0.47As, respectively, at temperature 300K. These maps show the magnitude of normalized parallel conductance (Gp/ω)/Aq as a function of ac frequency f and the gate voltage VG. The D_it is estimated by multiplying the peak value, [(G_p/ω)/Aq]_max, with a factor of 2.5[see Eq. 2.6]. For p-type MOSCAPs, all plots show that a distinct response of D_it exists at the gate voltage between 0 and 1 volt and lower frequency. The color variation in this region is getting dramatic as the temperature of PDA is above 400 ^oC. This indicates D_it dramatically increases, causing higher frequency dispersion in this region. For the samples with PDA 500 ^oC for 120 s, we also see the minority carrier response at gate voltage between 1 and 2 volt; furthermore, we speculate that the response appearing at VG= -2 volts and lower frequency may be the slow traps, resulting in higher frequency dispersion at V_G= -2 volts. For the n-type MOSCAPs, the response of D_it is obviously seen at gate voltage between 0 and -2 volts and. In addition, we also observe slight

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response of slow traps appearing on the samples with PDA 500 ^oC for 120 s.

Consequently, in order to retain our interface and oxide quality, higher PDA temperature should be avoided. PDA of 500 ^oC seriously degrades electrical characteristics due to the presence of border traps and higher Dit. We suppose that higher interface traps appearing at PDA 500 ^oC might be the precipitation of arsenide or As- states and the considerable existence of As2O5, and border traps might be the diffusion of arsenic oxides into Al₂O₃ during higher temperature of PDA, discussed in previous section 2.3.3.

Fig. 2.31 (a) (b) (c) and Fig. 2.32 (a) (b) (c) show parallel conductance curves of Al2O3/TMA-treated In0.53Ga0.47As MOSCAPs with FGA under different PDA conditions, on both p- and n-type (100)-oriented In_0.53Ga_0.47As, respectively, at temperature 300K. The Gp/ω-f curves from VG= -1 to 1 volt for p-type and VG= 0.5 to -1.5 volts for n-type are demonstrated here, and D_it can be obtained by multiplying peak value with a factor of 2.5. It is found that the peak value is getting larger as the temperature of PDA increases for p-type. For n-type MOSCAPs, the peak value is almost the same but its position is nearly pinned at the frequency between 10 kHz and 1 kHz when the temperature of PDA is above 400 ^oC. Fig. 2.33 (a) (b) (c) show the Dit profiles of Al2O3/In0.53Ga0.47As (100) with post-metallization FGA under various PDA conditions, assuming the capture cross section to be 10^-17 cm². It is obviously seen that the higher PDA temperature is, the higher Dit exist close to midgap. Dit

increases 322.65% at E_t= 0.377 eV after PDA 500 ^oC for 120 s, which indicates the degradation of interface quality.

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2.5.3 Comparison between the orientation of (100) and (111)A

Fig. 2.34 (a) (b) (c) (d) show parallel conductance maps of Al2O3/TMA-treated In_0.53Ga_0.47As MOSCAPs with FGA under different PDA conditions on p-type (111)A-oriented In0.53Ga0.47As at temperature 300K. It is noted that the response of slow traps only appears in the samples only with FGA, shown in Fig. 2.34 (a). This response disappears at other PDA temperature. Compared to Table 2.2, it seems that the electrical characteristics of MOSCAPs under PDA 300 ^oC with FGA is the best in all the samples for (111)A orientation. Even though we don’t observe the slow trap response at the samples with PDA 400 ^oC and 500 ^oC, there’s been an upward trend in the frequency dispersion at VG= -2 volts. In addition, the minority carrier response is strong in all samples, especially for only FGA one.

Fig. 2.35 (a) (b) (c) (d) show parallel conductance curves of Al2O3/TMA-treated In_0.53Ga_0.47As MOSCAPs with FGA under different PDA conditions on p-type (111)A-oriented In0.53Ga0.47As at temperature 300K. We observe that the interface states are reduced after PDA. However, the peak position is weakly pinned at frequency around 10 kHz for MOSCAPs with PDA temperature above 400 ^oC. Fig.

2.36 shows the Dit profiles of Al2O3/In0.53Ga0.47As (111)A with post-metallization FGA under various PDA conditions, assuming the capture cross section to be 10^-16 cm². The interface states can be reduced about 67% at the trap energy of 0.347 eV after PDA 300 ^oC for 120 s. The proper temperature of PDA is very important;

otherwise higher temperature could damage the gate oxide and degrade the interface between gate dielectric and substrate, causing higher frequency dispersion, higher Dit, and Fermi level pinning. Eventually, we demonstrate the D_it profilesof the best PDA

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conditions for the orientation of (100) and (111)A. In comparison with the orientation of (100), we find that the interface states of (111)A are even larger. The overviews of Dit values of MOSCAPs under various thermal treatments are shown in Table 2.5.