The conductance method is a basic and useful tool for interface engineering. It can extract interface states over band gap directly from impedance measurements of MOSCAPs by varying the temperature. Analyzing Al2O3/In0.53Ga0.47As interfaces with the conductance method, we can clearly find the best oxide and interface qualities under various process conditions and different substrate orientations. Our primary purpose in this chapter is to design the optimum process conditions for gate stack, also corresponding to fabrication of p-MOSFETs later.
Firstly, we study the effect of different thermal annealing. Compared to PMA, frequency dispersion in accumulation can be efficiently reduced by FGA. In addition, midgap traps have been slightly decreased after FGA. Subsequently, MOSCAPs under different PDA with FGA have also been discussed. It is noted that MOSCAPs under PDA 500 oC for 120 s with FGA show the worst electrical characteristics.
Furthermore, higher PDA temperature is, the higher Dit exists near midgap. The reason for the degradation of electrical characteristics may be the lower ratio of As2O3
to As2O5 and the existence of As-As states or As- states, which is shown in our XPS analysis.
Next, in our experiment, the electrical characteristics of In0.53Ga0.47As (100) is better than In0.53Ga0.47As (111)A, such as lower frequency dispersion and lower Dit, Hence, the (100)-oriented substrate would be used to fabricate MOSFETs.
30
Furthermore, the reason for studying different PDA conditions is the lift-off process used in gate patterning of MOSFETs. Because the developer solution used in this lift-off process is capable of etching Al2O3, we manage to strengthen our gate oxide by thermal annealing or other methods. In general, Al2O3 would be strong as the PDA temperature becomes high. However, excess thermal budget is not suitable for In0.53Ga0.47As substrates, probably resulting in degradation of electrical characteristics.
Therefore, we have to find the optimum process conditions not only for anti-etch gate dielectricbut also for lower Dit. In our study, the MOSCAPs with PDA 300 oC for 120 s have demonstrated quite good electrical characteristics. Other methods like depositing thin HfO2 on Al2O3 can be considered.
31
Reference (Chapter 2)
[1] M. Yokoyama, R. Iida, S. Kim, N. Taoka, Y. Urabe, H. Takagi, T. Yasuda, H.
Yamada, N. Fukuhara, M. Hata, M. Sugiyama, Y. Nakano, M. Takenaka, and S.
Takagi, “Sub-10-nm extremely thin body InGaAs-on-insulator MOSFETs on Si wafers with ultrathin Al2O3 buried oxide layers,” IEEE Electron Device Lett., vol.
32, p. 1218, 2011.
[2] H.-C. Chin, X. Liu, X. Gong, and Y.-C. Yeo, “Silane and ammonia surface passivation technology for high-mobility In0.53Ga0.47As MOSFETs,” IEEE Trans.
Electron Devices, vol. 57, p. 973, 2010.
[3] U. Singisetti, M. A. Wistey, G. J. Burek, A. K. Baraskar, B. J. Thibeault, A. C.
Gossard, M. J. W. Rodwell, B. Shin, E. J. Kim, P. C. McIntyre, B. Yu, Y. Yuan, D.
Wang, Y. Taur, P. Asbeck, and Y.-J. Lee,“In0.53Ga0.47As channel MOSFETs with self-aligned InAs source/drain formed by MEE regrowth,” IEEE Electron Device Lett., vol. 30, p. 1128, 2009.
[4] N. Goel, D. Heh, S. Koveshnikov, I. Ok, S. Oktyabrsky, V. Tokranov, R.
Kambhampatic, M. Yakimov, Y. Sun, P. Pianetta, C. K. Gaspe, M. B. Santos, J.
Lee, S. Datta, P. Majhi, and W. Tsai, “Addressing the gate stack challenge for high mobility InxGa1−xAs channels for NFETs,” in IEDM Tech. Dig., p.1, 2008.
[5] M. D. Pashley, K. W. Haberern, R. M. Feenstra, and P. D. Kirchner, “Different Fermi-level pinning behavior on n- and p-type GaAs(001),” Phys. Rev. B, vol. 48, p. 4612 , 1993.
[6] A. M. Sonnet, C. L. Hinkle, M. N. Jivani, R. A. Chapman, G. P. Pollack, R. M.
Wallace, and E. M. Vogel, “Performance enhancement of n-channel inversion type InxGa1-xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer,” Appl. Phys. Lett., vol. 93, p.
32
122109 ,2008.
[7] É . O’Connor, B. Brennan, V. Djara, K. Cherkaoui, S. Monaghan, S. B. Newcomb, R. Contreras, M. Milojevic, G. Hughes, M. E. Pemble, R. M. Wallace, and P. K.
Hurley, “A systematic study of (NH4)2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers,” J. Appl. Phys., vol. 109, no. 2, p. 024 101-1, 2011.
[8] B. Brennan, M. Milojevic, C. L. Hinkle, F. S. Aguirre-Tostado, G. Hughes, and R.
M. Wallace, “Optimisation of the ammonium sulphide (NH4)2S passivation process on In0.53Ga0.47As,” Appl. Surf. Sci., vol. 257, p. 4082, 2011.
[9] É . O’Connor, S. Monaghan, K. Cherkaoui, I. M. Povey, and P. K. Hurley,
“Analysis of the minority carrier response of n-type and p-type Au/Ni/Al2O3/In0.53Ga0.47As capacitors following optimized (NH4)2S treatment,”
Appl. Phys. Lett., vol. 99, p. 212901-1, 2011.
[10] Yen-Ting Chen, Yanzhen Wang, Fei Xue, Fei Zhou, and Jack C. Lee, “Physical and Electrical Analysis of Post-HfO2 Fluorine Plasma Treatment for the Improvement of In0.53Ga0.47As MOSFETs’ Performance,” IEEE Trans. Electron Devices, vol. 59, p. 139, 2012.
[11] M. Milojevic, R. Contreras-Guerrero, E. O’Connor, B. Brennan, P. K. Hurley, J.
Kim, C. L. Hinkle, and R. M. Wallace, “In-situ characterization of Ga2O passivation of In0.53Ga0.47As prior to high-κ dielectric atomic layer deposition,”
Appl. Phys. Lett., vol. 99, p. 042904-1, 2011.
[12] F. Zhu, H. Zhao, I. Ok, H. S. Kim, J. Yum, J. C. Lee, N. Goel, W. Tsai, C. K.
Gaspe, and M. B. Santos, “Effects of anneal and silicon interface passivation layer thickness on device characteristics of In0.53Ga0.47As metal–oxide–
semiconductor field-effect transistors,” Electrochem. Solid State Lett., vol. 12, p.
33 layer,” Appl. Phys. Lett., vol. 97, p. 052904-1, 2010.
[14] S. Monaghan, A. O’Mahony, K. Cherkaoui, É. O’Connor, I. M. Povey, M. G.
Nolan, D. O’Connell, M. E. Pemble, P. K. Hurley, G. Provenzano, F. Crupi, and S. B. Newcomb, “Electrical analysis of three-stage passivated In0.53Ga0.47As capacitors with varying HfO2 thicknesses and incorporating an Al2O3 interface control layer,” J. Vac Sci. Technol. B, vol. 29, p. 01A807-1, 2011.
[15] Shahrjerdi, D., Rotter, T., Balakrishnan, G., Huffaker, D., Tutuc, E., Banerjee, S.K., “ Fabrication of Self-Aligned Enhancement-Mode In0.53Ga0.47As MOSFETs With TaN/HfO2/AlN Gate Stack,” IEEE Trans. Electron Devices, vol. 29, p. 557, 2008.
[16] S. Barraud, O. Bonno, and M. Casse, “The influence of Coulomb centers located in HfO2/SiO2 gate stacks on the effective electron mobility,” J. Appl. Phys., vol.
104, p. 073725, 2008.
[17] S.M. George, “Atomic Layer Deposition: An Overview”, Chem. Rev., vol. 110, p.
111, 2010.
[18] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, “Surface passivation of III-V compound semiconductors using atomic-layer-deposition-grown Al2O3,” Appl. Phys. Lett., vol. 87, p. 252104-1, 2005.
[19] Cheng-Wei Cheng, John Hennessy, Dimitri Antoniadis, and Eugene A. Fitzgerald,
“Self-cleaning and surface recovery with arsine pretreatment in ex situ
34
atomic-layer-deposition of Al2O3 on GaAs,” Appl. Phys. Lett., vol. 95, p. 082106, 2009.
[20] T. D. Lin, H. C. Chiu, P. Chang, L. T. Tung, C. P. Chen, M. Hong, J. Kwo, W.
Tsai, and Y. C. Wang, “High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3/Ga2O3(Gd2O3) as gate dielectrics,” Appl. Phys. Lett., vol. 93, p. 033516, 2008.
[21] C. L. Hinkle, M. Milojevic, B. Brennan, A. M. Sonnet, F. S. Aguirre-Tostado, G.
J. Hughes, E. M. Vogel, and R. M. Wallace, “GaAs interfacial self-cleaning by atomic layer deposition,” Appl. Phys. Lett., vol. 94, p. 162101, 2009.
[22] E. H. Nicollian, J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. Wiley-Interscience, New York, 1982.
[23] Young-Chul Byun, Chee-Hong An, Seok-Hee Lee, Mann-Ho Cho, and Hyoungsub Kim, “Thermal Stability of ALD-HfO2/GaAs Pretreated with Trimethylaluminium,” J. Electrochem. Soc., vol. 159, p. G6, 2012.
[24] M. Passlack, “in Materials Fundamentals of Gate Dielectrics,” edited by A. A.
Demkov and A. Navrotsky (Springer, Dordrecht), p. 403, 2005.
[25] A. Stesmans and V. V. Afanas’ev, “Si dangling-bond-type defects at the interface of (100)Si with ultrathin layers of SiOx, Al2O3, and ZrO2,” Appl. Phys.
Lett., vol. 80, p. 1957, 2002.
[26] R. J. Carter, E. Cartier, A. Kerber, L. Pantisano, T. Schram, S. De Gendt, and M.
Heyns, “Passivation and interface state density of SiO2/HfO2- based/polycrystalline-Si gate stacks,” Appl. Phys. Lett., vol. 83, p. 533, 2003.
[27] Daniel M. Fleetwood, ““Border Traps” in MOS Devices,” IEEE Trans. on Nuclear Science, vol. 39, p. 269, 1992.
[28] E. J. Kim, E. Chagarov, J. Cagnon, Y. Yuan, A. C. Kummel, P. M. Asbeck, S.
35
Stemmer, K. C. Saraswat, and P. C. McIntyre, “Atomically Abrupt and Unpinned Al2O3/In0.53Ga0.47As Interfaces: Experiment and Simulation,” J. Appl. Phys., vol.
106, p. 124508, 2009.
[29] Yu Yuan, Lingquan Wang, Bo Yu, Byungha Shin, Jaesoo Ahn, Paul C. McIntyre, Peter M. Asbeck, Mark J. W. Rodwell, and Yuan Taur, “A Distributed Model for Border Traps in Al2O3- InGaAs MOS Devices,” IEEE Electron Device Lett., vol.
32, p. 485, 2011.
[30] Eun Ji Kim, Lingquan Wang, Peter M. Asbeck, Krishna C. Saraswat, and Paul C. McIntyre, “Border Traps in Al2O3/In0.53Ga0.47As (100) Gate Stacks and Their Passivation by Hydrogen Anneals,” Appl. Phys. Lett., vol. 96, p. 012906, 2010.
[31] CRC Press, CRC Handbook of Physics and Chemistry, 84th ed, Boca Raton, FL, 2003.
[32] Byungha Shin, Justin R. Weber, Rathnait D. Long, Paul K. Hurley, Chris G. Van de Walle, and Paul C. McIntyre, “Origin and Passivation of Fixed Charge in Atomic Layer Deposited Aluminum Oxide Gate Insulators on Chemically Treated InGaAs Substrates,” Appl. Phys. Lett., vol. 96, p. 152908, 2010.
[33] R. D. Long, B. Shin, S. Monaghan, K. Cherkaoui, J. Cagnon, S. Stemmer, P. C.
McIntyre, and P. K. Hurley, “Charged Defect Quantification in Pt/
Al2O3/In0.53Ga0.47As/InP MOS Capacitors,” J. Electrochem. Soc., vol. 158, p.
G103, 2011.
[34] V. Djara, K. Cherkaoui, M. Schmidt, S. Monaghan, E. O’Connor, I. M. Povey, D.
O’Connell, M. E. Pemble, and P. K. Hurley, “Impact of Forming Gas Annealing on the Performance of Surface-Channel In0.53Ga0.47As MOSFETs With an ALD Al2O3 Gate Dielectric,” IEEE Trans. on Electron Devices, vol. 59, p. 1084, 2012.
[35] Jenny Hu and H.-S. Philip Wong, “Effect of Annealing Ambient and Temperature on the Electrical Characteristics of Atomic Layer Deposition Al2O3/
36
In0.53Ga0.47As Metal-Oxide-Semiconductor Capacitors and MOSFETs,” J. Appl.
Phys., vol. 111, p. 044105, 2012.
[36] Chao-Ching Cheng, Chao-Hsin Chien, Guang-Li Luo, Chun-Hui Yang, Ching-Chih Chang, Chun-Yen Chang, Chi-Chung Kei, Chien-Nan, Hsiao, and Tsong-Pyng Perng, “Effects of Interfacial Sulfidization and Thermal Annealing on the Electrical Properties of an Atomic-Layer-Deposited Al2O3 Gate Dielectric on GaAs Substrate,” J. Appl. Phys., vol. 103, p. 074102, 2008.
[37] H. Ishii, N. Miyata, Y. Urabe, T. Itatani, T. Yasuda, H. Yamada, N. Fukuhara, M.
Hata, M. Deura, M., Sugiyama, M. Takenaka, S. Takagi, “High Electron Mobility Metal-Insulator-Semiconductor Field-Effect Transistors Fabricated on (111)-Oriented InGaAs Channel,” Appl. Phys. Exp., vol. 2, p. 121101, 2009.
[38] Noriyuki Miyata, Hiroyuki Ishii, Yuji Urabe, Taro Itatani, Tetsuji Yasuda, Hisashi Yamada, Noboru Fukuhara, Masahiko Hata, Momoko Deura, Masakazu Sugiyama, Mitsuru Takenaka, Shinichi Takagi, “Origin of Electron Mobility Enhancement in (111)-Oriented InGaAs Channel Metal-Insulator-Semiconductor Field-Effect-Transistors,” Microelectron. Eng., vol. 88, p.3459, 2011.
[39] Urabe, Y., Miyata, N., Ishii, H., Itatani, T., Maeda, T., Yasuda, T., Yamada, H., Fukuhara, N., Hata, M., Yokoyama, M., Taoka, N., Takenaka, M., Takagi, S.,
“Correlation between Channel Mobility Improvements and Negative Vth Shifts in III–V MISFETs: Dipole Fluctuation as New Scattering Mechanism,” IEDM, 2010 IEEE International, p.6.5.1, 2010.
[40] M. Deura, T. Hoshii, T. Yamamoto, Y. Ikuhara, M. Takenaka, S. Takagi, Y.
Nakano, M. Suguyama, “Dislocation-Free InGaAs on Si(111) Using Micro-Channel Selective-Area Metalorganic Vapor Phase Epitaxy,” Appl. Phys.
Exp., vol. 2, p. 011101, 2009.
[41] Noriyuki Taoka, Toyoji Yamamoto, Masatomi Harada, Yoshimi
37
Yamashita, Naoharu Sugiyama, and Shinichi Takagi, “Importance of Minority Carrier Response in Accurate Characterization of Ge Metal-Insulator-Semiconductor Interface Traps,” J. Appl. Phys., vol. 106, p.
044506, 2009.
[42] Noriyuki Taoka, Masafumi Yokoyama, Sang Hyeon Kim, Rena Suzuki, Takuya Hoshii, Ryo Iida, Sunghoon Lee, Yuji Urabe, Noriyuki Miyata, Tetsuji Yasuda, Hisashi Yamada, Noboru Fukuhara, Masahiko Hata, Mitsuru Takenaka, and Shinichi Takagi, “AC Response Analysis of C–V Curves and Quantitative Analysis of Conductance Curves in Al2O3/InP Interfaces,” Microelectron. Eng., vol. 88, p.1087, 2011.
[43] Roman Engel-Herbert, Yoontae Hwang, and Susanne Stemmer, “Comparison of Methods to Quantify Interface Trap Densities at Dielectric/III-V Semiconductor Interfaces,” J. Appl. Phys., vol. 108, p. 124101, 2010.
38
★Surface pretreatment
★Al
2O
3by ALD (100 cyc. & 250
oC)
★As-deposited or PDA (300
oC/120 s, 400
oC/120 s, 500
oC/120 s)
★Gate electrode (Ti/Pt) via shadow mask
★Backside contact
★FGA or PMA
Fig. 2.1 Process flow of (100)-oriented In0.53Ga0.47As channel MOSCAPs with different thermal treatments
Fig. 2.2 MOSCAPs structure with ALD-TMA/Al2O3/In0.53Ga0.47As (100)
-ACE (5 min) -IPA (5 min)
-HCl:H
2O = 1:10 (2 min) -TMA treatment 10 cyc.
InP (100)
In
0.53Ga
0.47As (100)_buffer layer In
0.53Ga
0.47As (100)_channel layer
Ti/Pt
TMA/Al
2O
339
Fig. 2.3 TEM image of the as-deposited ALD-TMA/Al2O3 on In0.53Ga0.47As with FGA
In
0.53Ga
0.47As Ti/Pt TMA/Al
2O
3~ 11 nm
40
★Surface pretreatment
★Al
2O
3by ALD (100 cyc. & 250
oC)
★As-deposited or PDA (300
oC/120 s, 400
oC/120 s, 500
oC/120 s)
★Gate electrode (Ti/Pt) via shadow mask
★Backside contact (Ti/Pt)
★FGA
Fig. 2.4 Process flow of (111)A-oriented p-In0.53Ga0.47As channel MOSCAPs with different PDA conditions
Fig. 2.5 MOSCAPs structure with ALD-TMA/Al2O3/In0.53Ga0.47As (111)A
-ACE (5 min) -IPA (5 min)
-HCl:H
2O = 1:10 (2 min) -TMA treatment 10 cyc.
p-InP (111)A
p-In
0.53Ga
0.47As (111)A_buffer layer p-In
0.53Ga
0.47As (111)A_channel layer
Ti/Pt
Ti/Pt
TMA/Al
2O
341 p-type Pt/Ti/TMA+Al2O3/In0.53Ga0.47As (100) MOSCAPs (as-deposited) (a) w/o FGA and (c) w/ FGA
42
43 Pt/Ti/TMA+Al2O3/In0.53Ga0.47As (100) MOSCAPs (as-deposited) with (a) FGA and (c) PMA
44 Pt/Ti/TMA+Al2O3/In0.53Ga0.47As (100) MOSCAPs (as-deposited) with (b) FGA and (d) PMA
45
(a)
(c)
Fig. 2.10 Map of the normalized conductance, (G/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with Al2O3 (as-deposited) on p-type In0.53Ga0.47As (100) after (a) FGA and (c) PMA
46
(b)
(d)
Fig. 2.11 Map of the normalized conductance, (G/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with Al2O3 (as-deposited) on n-type In0.53Ga0.47As (100) after (b) FGA and (d) PMA
47
Fig. 2.12 Schematic diagram of tunneling between border traps in gate dielectric and conduction band of semiconductor
Fig. 2.13 Band alignment between Al2O3 and common III-V compound semiconductors, and position of charge-state transition levels for dangling bonds in the oxide
Gate dielectric
Semiconductor
E
cE
vE
fE
c oxE－
48
49
-2 -1 0 1 2
0.0 0.2 0.4 0.6
1MHz
PDA 500 ℃ /120s, w/ FGA T=300K
Ca pa c ita nc e ( F/cm
2)
Gate Voltage (volt)
100Hz
(c)
Fig. 2.14 Multifrequency C-V curves (1 MHz to 100 Hz, 300K) for p-type Pt/Ti/TMA+Al2O3/In0.53Ga0.47As (100) MOSCAPs after post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) 300 oC (b) 400 oC (c) 500 oC
50
-2 -1 0 1 2
0.0 0.2 0.4 0.6
T=300K
PDA 300 ℃ /120s, w/ FGA
Ca pa c ita nc e ( F/cm
2)
Gate Voltage (volt)
100Hz
1MHz
(a)
-2 -1 0 1 2
0.0 0.2 0.4 0.6
T=300K
PDA 400 ℃ /120s, w/ FGA
Ca pa c ita nc e ( F/cm
2)
Gate Voltage (volt)
100Hz
1MHz
(b)
51
-2 -1 0 1 2
0.0 0.2 0.4 0.6
Ca pa c ita nc e ( F/cm
2)
Gate Voltage (volt)
T=300K
PDA 500 ℃ /120s, w/ FGA 100Hz
1MHz
(c)
Fig. 2.15 Multifrequency C-V curves (1 MHz to 100 Hz, 300K) for n-type Pt/Ti/TMA+Al2O3/In0.53Ga0.47As (100) MOSCAPs after post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) 300 oC (b) 400 oC (c) 500 oC
52
(a)
(b)
53
(c)
Fig. 2.16 Map of the normalized conductance, (G/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with ALD-TMA/Al2O3
on p-type In0.53Ga0.47As (100) after post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) 300 oC (b) 400 oC (c) 500 oC
54
(a)
(b)
55
(c)
Fig. 2.17 Map of the normalized conductance, (G/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with ALD-TMA/Al2O3
on n-type In0.53Ga0.47As (100) after post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) 300 oC (b) 400 oC (c) 500 oC
56
57
1328 1326 1324 1322
As-deposited w/ FGA
Inte ns ity (a .u.)
PDA 300℃ w/ FGA
PDA 400℃ w/ FGA
PDA 500℃ w/ FGA
Binding Energy (eV)
As 2p3/2
As-Ga As2O
As2O5 3
As-As-As
(c)
Fig. 2.18 X-ray photoelectron spectroscopy of ALD-TMA (10 cycles)/Al2O3 (10 cycles) on (100)-oriented In0.53Ga0.47As with post-metallization FGA under various PDA conditions (a) Ga 2p3/2 (b) In 3d5/2 (c) As 2p3/2
58
59
60
post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) as-deposited (b) 300 oC (c) 400 oC (d) 500 oC
(a)
(b)
61
(c)
(d)
Fig. 2.20 Map of the normalized conductance, (G/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with ALD-TMA/Al2O3 on p-type In0.53Ga0.47As (111)A after post-metallization FGA under different
62
63
1328 1326 1324 1322
Inte ns ity (a .u.)
As
2O
5
As
2O
3
As-As
As-Ga
As-As-deposited w/ FGA
PDA 300℃ w/ FGA
PDA 400℃ w/ FGA
PDA 500℃ w/ FGA
As 2p
3/2
Binding Energy (eV)
(c)
Fig. 2.21 X-ray photoelectron spectroscopy of ALD-TMA (10 cycles)/Al2O3 (10 cycles) on (111)A-oriented In0.53Ga0.47As with post-metallization FGA under various PDA conditions (a) Ga 2p3/2 (b) In 3d5/2 (c) As 2p3/2
64
Fig. 2.22 The band diagram of a n-type MOSCAP in depletion is shown in (a). A small ac signal of frequency f superimposing on a dc gate bias VG is applied, inducing band bending ψs in the semiconductor and interface trap response with time constant . (b) Equivalent circuit of MOSCAP in depletion. (c) Measured circuit.
65
Fig. 2.23 (a) & (b) Charge trapping characteristics for In0.53Ga0.47As under different temperature and corresponding measurement window with 100 Hz and 1 M Hz C-V measurement frequency
66
(a)
(b)
Fig. 2.24 Map of the normalized parallel conductance, (Gp/ω)/Aq, as a function of gate bias VG and frequency f measured at 300K for MOSCAPs with Al2O3 (as-deposited) on p-type In0.53Ga0.47As (100) after (a) FGA and (b) PMA
67
(a)
(b)
Fig. 2.25 Map of the normalized parallel conductance, (Gp/ω)/Aq, as a function of gate bias VG and frequency f measured at 300K for MOSCAPs with Al2O3 (as-deposited) on n-type In0.53Ga0.47As (100) after (a) FGA and (b) PMA
68 volt. The measurement is performed at 300K.
69 volts. The measurement is performed at 300K.
70 conductance method, showing that MOSCAPs with (a) FGA and (b) PMA.
The measurement is performed at 300K.
71
(a)
(b)
72
(c)
Fig. 2.29 Normalized parallel conductance, (Gp/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with ALD-TMA/Al2O3 on p-type In0.53Ga0.47As (100) after post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) 300 oC (b) 400 oC (c) 500 oC.
73
(a)
(b)
74
(c)
Fig. 2.30 Normalized parallel conductance, (Gp/ω)/Aq, as a function of gate bias VG
and frequency f measured at 300K for MOSCAPs with ALD-TMA/Al2O3 on n-type In0.53Ga0.47As (100) after post-metallization FGA under different PDA conditions in N2 ambience for 120 s (a) 300 oC (b) 400 oC (c) 500 oC.
75
PDA 300 ℃ /120s w/ FGA,T=300K Vg=1 Vg=-1
PDA 400 ℃ /120s w/ FGA,T=300K Vg=-1
(b)
76
10
210
310
410
510
60
1 2 3 4 5
G
p/ q
10
12eV
-1cm
-2)
Frequency (Hz)
PDA 500 ℃ /120s w/ FGA,T=300K Vg=1 Vg=-1
(c)
Fig. 2.31 Parallel conductance curves of MOSCAPs with Al2O3 on p-type In0.53Ga 0.47-As (100) with post-metallization FGA and under different PDA conditions for VG= -1 to 1 volt (a) 300 oC (b) 400 oC (c) 500 oC. The measurement is performed at 300K.
77
10
210
310
410
510
60
1 2 3
G
p/ q
10
12eV
-1cm
-2)
Frequency (Hz)
PDA 300 ℃ /120s w/ FGA,T=300K Vg=-1.5 Vg=0.5
(a)
10
210
310
410
510
60
1 2 3
G
p/ q
10
12eV
-1cm
-2)
Frequency (Hz)
Vg=0.5 Vg=-1.5
PDA 400 ℃ /120s w/ FGA T=300K
(b)
78
10
210
310
410
510
60
1 2 3
G
p/ q
10
12eV
-1cm
-2)
Frequency (Hz)
Vg=0.5 Vg=-1.5
PDA 500 ℃ /120s w/ FGA T=300K
(c)
Fig. 2.32 Parallel conductance curves of MOSCAPs with Al2O3 on n-type In0.53Ga 0.47-As (100) with post-metallization FGA and under different PDA conditions for VG= 0.5 to -1.5 volts.(a) 300 oC (b) 400 oC (c) 500 oC. The measurement is performed at 300K.
79
80
0.0 0.2 0.4 0.6
0 2 4 6 8 10 12
p type 300K n type 300K
D
it( 10
12eV
-1cm
-2)
E-E v (eV)
PDA 500 ℃ /120s w/ FGA
E v E c
(c)
Fig. 2.33 Al2O3/In0.53Ga0.47As (100) interface state distribution as determined from conductance method, showing that MOSCAPs with post-metallization FGA and under different PDA conditions (a) 300 oC (b) 400 oC (c) 500 oC for 120s. The measurement is performed at 300K.
81
(a)
(b)
82
(c)
(d)
Fig. 2.34 Normalized parallel conductance, (Gp/ω)/Aq, as a function of gate bias VG and frequency f measured at 300K for MOSCAPs with ALD-TMA/Al2O3 on p-type In0.53Ga0.47As (111)A after post-metallization FGA under different
83
84
Fig. 2.35 Parallel conductance curves of MOSCAPs with Al2O3 on p-type In0.53Ga 0.47-As (111)A with post-metallization FGA and under different PDA conditions for VG= -1 to 1 volt. (a) as-deposited (b) 300 oC (c) 400 oC (d) 500 oC.
85 different PDA conditions. The measurement is performed at 300K.
0.0 0.2 0.4 0.6
Fig. 2.37 The comparison of Dit profiles between (100) and (111)A
86
Table 2.1 The overviews of frequency dispersion of ALD-TMA/Al2O3 (100)-oriented In0.53Ga0.47As MOSCAPs (@VG = -2 for p-type or 2 volt for n-type)
As-deposited 0.226 2.959
300◦C /120s 0.233 2.484
87
Area ratio As-As/As-Ga As-/As-Ga As2O3/ As2O5
As-deposited 0.185 1.176
300◦C /120s 0.024 0.109 1.862 (111)A-oriented In0.53Ga0.47As under different thermal treatments
88
Chapter 3
Self-Aligned Metal Source/Drain In
0.53Ga
0.47As n-MOSFETs using Ni-InGaAs Alloy
3.1 Introduction
Lately, the performance improvement accompanied by device scaling has become tough owing to the increase in leakage current, short channel effects, and so on. In order to solve this scaling problem, several groups are dedicated to application of new materials for future generations [1-2]. Indium Gallium Arsenide (InGaAs) is considered to be a potential channel material for its high electron mobility. One of the challenges to achieve high drive current in MOSFETs is to develop stable and low-resistance ohmics contact to InGaAs. High S/D resistance results from low dopant solubility of III-V compound semiconductors, and metal S/D structure is one of the hopeful methods to reduce S/D resistance. In addition, self-alignment of the S/D contacts to the gate electrode is desirable for reduction of S/D access resistances and for achieving reduced transistor footprint [3]. In this respect, the requirements of S/D for scaled III-V MOSFETs can be satisfied by the self-aligned metal S/D using an alloy layer formed by the reaction of III-V and metals (Fig. 3.1), like silicides, with low sheet resistance and low Schottkey Barrier Height (SBH) against III-Vs. A self-aligned metallization process is also simple and similar to the salicidation process in Si CMOS technology
In this chapter, we made attempt to fabricate the self-aligned Ni-InGaAs
89
metallization process for InGaAs channel n-MOSFETs. The self-aligned metallization process consists of conversion of sputtered nickel (Ni) on InGaAs into a uniform Ni-InGaAs film by rapid thermal annealing (RTA), and removal of unreacted Ni by selective wet etching. The most critical parts of this technique is the selective etch of Ni over Ni-InGaAs, which can be quantified as the ratio of the etch rates of Ni and
where rNi and rNi-InGaAs are the etch rates of Ni and Ni-InGaAs respectively.
Many etch chemistries etch Ni at a rapid rate, such as Hydrochloric (HCl), Nitric Acid (HNO3), Aqua-Regia [ HCl:HNO3:H2O (3:1:2)], Sulfuric Peroxide Mixture (SPM) [H2SO4:H2O2 (4:1)], HCl:H2O2 (4:1), HCl:HNO3 (5:1), and HF:HNO3 (1:1). Here, we focus on HCl and HNO3 solutions performed at different temperature, and prefer the high selectivity etchant that etches Ni quickly but etches Ni-InGaAs slowly. The results are shown in Table 3.1, which is from reference [4]. The concentrated HCl (25
◦C) etching the Ni film at a rapid rate of approximately 61 nm/minute gives the highest selectivity of approximately 15.6. The consequences of this reference could be useful for the process of In0.53Ga0.47As channel n-MOSFETs with self-aligned Ni-InGaAs S/D.