p-In0.53Ga0.47As (Zn-doped, ~1 × 1017 cm-3) buffer layer and a 300 nm thick p-In0.53Ga0.47As (Zn-doped, ~1.23×1016 cm-3) channel layer are sequentially grown. In the beginning, 100 cycles thick Al2O3 and 420 nm thick SiO2 isolation layer were deposited on the substrates, and then the active area (AA) was patterned by optical lithography. After cleaned by acetone, IPA, and diluted HCl, the substrates were transferred to ALD chamber for the deposition of gate oxide. Then, 10 cycles TMA treatment was performed before the subsequent 100 cycles Al2O3 and 50 cycles HfO2 deposition at 250 oC. After the deposition of gate oxide, the samples were followed by PDA 300 oC for 120 s in N2. Ti/Pt (5 nm/ 100 nm) gate deposition by sputter and gate patterning were carried out. Following gate stack formation, a 30 nm Ni was also deposited by sputter and RTA was performed at 250 oC for 30 s and 300 oC for 60 s in N2 for the formation of Ni-InGaAs as S/D regions. Concentrated HCl was able to remove unreacted Ni with its good selectivity between Ni and Ni-InGaAs alloys.
Subsequently, 100 nm SiO2 was deposited as the passivation layer and contact holes were patterned by optical lithography. Finally, Ti/Pt for the S/D pad and back contact electrode was sputtered.
3.3 Failure analysis
The reason why the devices can’t work may be the junction parts of MOSFETs.
Even though we found the good rectifying behaviors (on/off ratio~ 105), shown in Fig.
3.3, from our junction characteristics (I-V curves), it might not be the characteristics of Ni-InGaAs/In0.53Ga0.47As junction. We speculate that this Schottky junction characteristics might be the Pt(metal pad)/p-In0.53Ga0.47As diode. Ideally, we can verify that whether the Ni-InGaAs is formed by SBH. In ideal case, the SBH for
91
electron of Ni-InGaAs/In0.53Ga0.47As and Pt/In0.53Ga0.47As contact is 0.7 eV and 1.1 eV, respectively. However, we observed that SBH is relatively independent of the work function of the metal from reference [2], shown in Fig. 3.4. The relative constancy of the barrier height with various work function metals is sometimes attributed to Fermi level pinning, where the Fermi level is almost pinned at the charge neutrality level (CNL). The CNL for In0.53Ga0.47As is near the conduction band, shown in Fig. 3.5, which also indicates that the SBH is almost pinned in the vicinity of the conduction band edge. The thermionic current-voltage relationship of Schottky barrier diode, neglecting series and shunt resistance, is given by
3
Where Is is the saturation current, A the diode area, A* Richardson’s constant, ΦB the effective barrier height, and η the ideal factor. Among the current-voltage methods, the ideal factor η and the effective barrier height ΦB are determined by the slope of the semilog I versus V curve and its intercept of zero bias (V=0), respectively. For the samples with RTA 250 oC for 30 s, η is 1.28 and ΦB is 0.16 eV, while η is 1.21 and ΦB
is 0.14 eV for the sample with RTA 300 oC for 60 s. This result corresponds to the fact that EF is pinned near the conduction band edge for the CNL of In0.53Ga0.47As.
Therefore, other methods such as TEM and energy dispersive X-ray (EDX) are used to judge whether Ni-InGaAs is formed. Fig. 3.6 shows the cross-sectional TEM image of self-aligned metal S/D structure. There is no obvious color difference at the S/D region part of substrate, which can distinguish Ni-InGaAs from In0.53Ga0.47As substrates. Evidence which Ni-InGaAs may not be formed is also seen by EDX analysis, demonstrated in Fig. 3.7 (a) and (b). The positions 1 and 2 where we did
92
EDX analysis are shown in Fig. 3.6. It is noted that the amounts of Ni in both graphs are few, which indicates that there is no formation of Ni-InGaAs at this region. One of the possible reasons that the Ni-InGaAs cannot be formed is the thin native oxides existing between Ni and In0.53Ga0.47As channel layer. Before loading to the sputter, the samples were cleaned by diluted HCl for 2 min. We suppose that the regrowth of native oxides happened during the loading time. Hence, surface pre-clean before deposition of Ni might be a critical point in order to avoid this uncertainty.
3.4 Summary
The good rectifying characteristics of Pt/p-In0.53Ga0.47As contacts results from EF
pinning near the conduction band edge even though its ideal SBH for electron is 1.1 eV. In addition, the critical reason why devices are unable to work is the non-formation of Ni-InGaAs alloy, verified by EDX analysis. The native oxides existing between the Ni and In0.53Ga0.47As substrate should be avoided, which may inhibit the formation of Ni-InGaAs alloy.
93
Reference (Chapter 3)
[1] Huaxin Guo, Xingui Zhang, Hock-Chun Chin, Xiao Gong, Shao-Ming Koh, Chunlei Zhan, Guang-Li Luo, Chun-Yen Chang, Hau-Yu Lin, Chao-Hsin Chien, Zong-You Han, Shih-Chiang Huang, Chao-Ching Cheng, Chih-Hsin Ko, Wann, C.H., Yee-Chia Yeo, “A New Self-Aligned Contact Technology for III-V MOSFETs,” VLSI Technology Systems and Applications (VLSI-TSA), p. 152, 2010.
[2] SangHyeon Kim, Masafumi Yokoyama, Noriyuki Taoka, Ryo Iida, Sunghoon Lee, Ryosho Nakane, Yuji Urabe, Noriyuki Miyata, Tetsuji Yasuda, Hisashi Yamada, Noboru Fukuhara, Masahiko Hata, Mitsuru Takenaka, and Shinichi Takagi, “Self-Aligned Metal Source/Drain InxGa1-xAs n-Metal–Oxide–
Semiconductor Field-Effect Transistors Using Ni–InGaAs Alloy,” IEDM, p. 596, 2010.
[3] Xingui Zhang, Ivana, Hua Xin Guo, Xiao Gong, Qian Zhou and Yee-Chia Yeoz,
“A Self-Aligned Ni-InGaAs Contact Technology for InGaAs Channel n-MOSFETs,” J. Electrochem. Soc., vol. 159, p. H511, 2012.
[4] Sujith Subramanian, Ivana, Qian Zhou, Xingui Zhang, Mahendran Balakrishnan and Yee-Chia Yeo, “Selective Wet Etching Process for Ni-InGaAs Contact Formation in InGaAs N-MOSFETs with Self-Aligned Source and Drain,” J.
Electrochem. Soc., vol. 159, p. H16, 2012.
94
Fig. 3.1 Schematic cross-sectional image and technology requirements of future III-V MOSFETs
● Ti/Pt deposition and gate patterning
● Ni-InGaAs S/D formation -S/D Ni deposition
-RTA 250 oC for 30 s or 300 oC for 60 s
-removal of unreacted Ni (selective etching by HCl)
● contact hole and metal pad (Ti/Pt)
● back contact (Ti/Pt)
Metallic alloy & selective etching
95
Fig. 3.2 Process flow and device structure of In0.53Ga0.47As channel n-MOSFET with self-aligned Ni-InGaAs source and drain
In0.53Ga0.47As (buffer layer)
InP
Ti/Pt
In0.53Ga0.47As (channel layer)
Ni-InGaAs Ni-InGaAs
FOX FOX
Al2O3 Ti/Pt
HfO2
96
-1.0 -0.5 0.0 0.5 1.0
10
-810
-710
-610
-510
-410
-310
-210
-110
010
110
210
3Curre nt Den s ity ( A/cm
2)
Applied Voltage (volt)
RTA 300°C/60s RTA 250°C/30s
Fig. 3.3I-V characteristics of metal/p-InGaAs diodes with different RTA conditions
Fig. 3.4 Schottky barrier height (SBH) for electron of a variety of metals/In0.53Ga0.47As contacts from [2]
97
Fig. 3.5 Energy level for charge neutrality level (CNL) in InxGa1-xAs
Fig. 3.6 The cross-section TEM image of self-aligned metal S/D structure. 1 and 2 show the positions where EDX analysis was done.
1
2
98
Element In Ga As Ni O Si P Cu
Weight (%) 28.30 12.57 29.82 0.36 0.98 0.86 0.37 26.74 Atomic (%) 18.18 13.30 29.37 0.45 4.50 2.27 0.87 31.05
(a)
Element In Ga As Ni O Si P Cu
Weight (%) 7.44 3.93 16.60 1.01 22.05 28.24 0.50 20.22 Atomic (%) 2.10 1.83 7.20 0.56 44.77 32.66 0.53 10.34
(b)
Fig. 3.7(a) and (b) show the EDX analysis at position 1 and 2, where the amounts of Ni are few.
99
Chemical Selectivity S (rNi/rNi-InGaAs)
HNO3 (1:10) 25 oC 4.6
HNO3 (1:20) 25 oC 4.4
36% HCl 25 oC 15.6
HCl (1:10) 25 oC 2.3
HCl (1:10) 50 oC 1.2
HCl (1:10) 70 oC 1.8
HCl (1:10) 90 oC 2.2
Table 3.1 Etch selectivity of Ni over Ni-InGaAs in different etchants. [4]
100
Chapter 4
Conclusion
In this thesis, Ti-Pt/Al2O3/In0.53Ga0.47As(100) MOS capacitors with different conditions of thermal treatments such as PMA, FGA, and PDA were investigated.
FGA is able to effectively suppress frequency dispersion in accumulation (p-type:
12.34%→8.96% & n-type: 8.08%→4.77%) and reduce some, but not all, midgap traps ( Dit (Et=0.382 eV):↓19.48% & Dit (Et=0.428 eV):↓22.28%), compared to PMA. Then, we discuss MOSCAPs under various PDA conditions with FGA to find the highest temperature limit of our gate stack. It is noted that MOSCAPs under PDA 500 oC for 120 s with FGA demonstrate the worst electrical characteristics such as extremely high frequency dispersion in accumulation (p-type: 8.96%→16.91% &
n-type: 4.77%→5.99%) and higher midgap traps (Dit (Et=0.377 eV):↑322.65% & Dit
(Et=0.487 eV): ↑117.56%) causing EF pinning. The XPS spectra of As 2p3/2 show that the area ratio of As2O3 to As2O5 becomes lower as the PDA temperature gets higher; therefore, lower extent of the As2O3 passivation of the Al2O3/In0.53Ga0.47As causes the degradation of interface between Al2O3 and In0.53Ga0.47As.
Next, Ti-Pt/Al2O3/p-In0.53Ga0.47As(111)A MOS capacitors under various PDA temperature with FGA were studied. The electrical characteristics of the capacitors can be improved by PDA 300 oC for 120 s with FGA, for example, the reduction of frequency dispersion in accumulation (14.57%→12.72%) and midgap traps (Dit (Et=0.347eV): ↓67%). The XPS spectra of As 2p3/2 show that the area ratio of As2O3
to As2O5 is the highest for the MOSCAPs under PDA 300 oC for 120 s with FGA, which indicates the lowest interface traps in all the samples. Subsequently, we
101
compare MOSCAPs with orientation (111)A to orientation (100). It is seen that MOSCAPs with (100)-oriented In0.53Ga0.47As substrates demonstrate better electrical characteristics than MOSCAPs with (111)A orientation. Despite the fact that Al2O3/In0.53Ga0.47As (111)A interface has lower As atoms of oxidation states than Al2O3/In0.53Ga0.47As (100) interface, the area ratio of As2O5 to As2O3 of orientation (111)Ais still higher than that (100). Hence, Dit of (111)A is much higher than that of (100).
Finally, the failure of self-aligned Ni-InGaAs S/D In0.53Ga0.47As n-MOSFETs is attributed to the non-formation of Ni-InGaAs according to the TEM images and EDX analysis. Surface pre-clean before the Ni deposition is very important, avoiding the regrowth of native oxides during the loading time preventing the formation of Ni-InGaAs. In the future, we hope our device can be successfully fabricated by solving these problems mentioned above. In addition, we suggest that the gate oxide, Al2O3, could be replaced by Al2O3 (thin)/HfO2 (thick) double layers or other high-κ oxides such as ZrO2, which EOT can further be scaled down. Devices with Si- or Ge- doped S/D with Ni-InGaAs contact are also a promising method to suppress the junction reverse leakage current significantly.
102